VLSI LAB-1 REPORT

LAB: VLSI Name: M.B.Vinay

Date: 09-Aug-2017 Id no: N130492

Day: Wednesday Class: ss-04

Roll no: 33

Basic Gates
And Gate

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Simulation

Elaborated Design
OR GATE
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Simulation

Elaborated Design
XOR-Gate
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Simulation

Elaborated Design
XNOR-GATE
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Simulation

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NAND GATE
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Elaborated Design
NOR-GATE
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Elaborated Design
Half adder
Code

Simulation

Elaborated Design
Full adder
Code

Simulation

Elaborated Design
Two by one mux
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Simulation

Elaborated Design
Four by one mux
Code

Simulation
Elaborated Design