LIST OF FIGURES

Figure No. Name of the Figure Page No

4.1 State transversal diagram of finite state machine 18

4.2 FSM for transition table 4.4 22
4.3 FSM for table 4.5 22
5.1 Finite state machine 27
5.2 Transitions in AC algorithm 30
5.3 Transition in proposed algorithm (AC_algorithm+merg-FSM) 31
6.1 Design Flow Chart 34
6.2 Bit File Burning 35
6.3 Internal structure of FPGA 36
6.4 FPGA structure 37
6.5 Internal structure of CPLD 39
6.6 FPGA Classification on user programmable technology 42
6.7 SRAM-controlled Programmable Switches. 43
6.8 Arrangement of slices within the CLB 45
6.9 Xilinx Virtex 5 LX50T 47
6.10 Xilinx iMPACT USB port & JTAG Header 49
6.11 Adept and IMPACT USB Ports 50
6.12 Power Supply 51
6.13 Flash Memory 52
6.14 USB host cypress CY7C67300 54
7.1 Basic simulation flow 57
7.2 Steps for simulation of a design 58
7.3 Basic Steps For Simulating With Multiple Libraries. 59
7.4 Creating a New Library Dialog 61
7.5 Work Library in the Workspace 62
7.6 Compile Source Files Dialog 63
7.7 Verilog Modules Compiled into work Library 63
7.8 Loading Design with Start Simulation Dialog 64

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Figure No. Name of the Figure Page No
7.9 Workspace Sim Tab Displays Design Hierarchy 64
7.10 Object Plane Displays Design Objects 65
7.11 Using the Popup Menu to Add Signals to Wave Window 66
7.12 Waves Drawn in Wave Window 66
7.13 Setting Breakpoint in Source Window 67
7.14 Restart Dialog 68
7.15 Blue Arrow Indicates Where Simulation Stopped. 69
7.16 Values Shown in Objects Window 69
7.17 Parameter Name and Value in Source Examine Window 69
7.18 The Main Window 70
7.19 Window/Pane Control Icons 71
8.1 Simulation result of pattern one matched 72
8.2 Simulation result of pattern two matched 73
8.3 Simulation result of pattern not matched 74
8.4 Design summary report of previous algorithm 75
8.5 Design summary report of proposed AC_algorithm 75

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 LIST OF TABLES
Table No. Name of the Table Page No

4.1 Set of transition rules for finite state machine 16

4.2 State Transition of q1 in Finite State Machine 16
4.3 Two output finite state machine 19
4.4 Acknowledgement and retransmission of the output 22
4.5 Acknowledgement and retransmission of the output 24
5.1 Transition table for the Fig. 5.1 state machine 28
5.2 Transition table of ac algorithm for fig 5.2 30
5.3 Transitions table of ac algorithm for fig 5.3 31
6.1 Distributed RAM configuration 46
6.2 Flash Memory pin Specification 53

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 LIST OF ACRONYMS
AC Aho-Corasick
ACK Acknowledgement
ALG Algorithm
CAD Computer Aided Design
CLK Clock
CPLD Complex Programmable Logic Device
DDR Double Data Rate
EDA Electronic Design Automation
FPGA Field Programmable Gate Array
FSM Finite State Machine
HDL Hardware Description Language
MUX Multiplexer
NIDS Network Intrusion Detection System
PHY Periphery
RTL Resistor Transistor Logic
SIDS Signature Based Intrusion Detection System
SIPO Serial In Parallel Out
TLM Transaction Level Modeling
VHSIC Very High Speed Integrated Circuits
VLSI Very Large Scale Integration

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