Title e.g.

8 Bit Registered Adder/Subtractor

Your Name, Matriculation Number

Date, Version

1. Features
add_sub8 design implementing a registered 8 bit two's complement adder/subtractor.
overflow/underflow detection.

2. Functional Specification
The add_sub8 design implements a registered 8 bit addition/subtraction. Both input operands
and the output result are registered on the positive edge of the clock. The adder output is 8
bits wide. If overflow/underflow is detected the overflow signal is set high.

2.1 Module Interface

The verilog module interface for add_sub8 is shown below:

module
add_sub8(result,overflow,a,b,add_sub,clk);

2.2 Ports
Input and Output Ports
Port Type Name Description
input a[7:0] input a in two's complement format
input b[7:0] input b in two's complement format
input clk clock signal
input add_sub Operation: 1 = add, 0 = subtract
output overflow Overflow/underflow signal: 1 = overflow, 0 = no overflow
output result[7:0] result of add/subtract operation in two's complement format

3. Design
Addition and subtraction of two's complement numbers are performed using a binary adder.
The subtraction operation a - b is achieved by performing the operation a + (-b), where -b is
generated by complementing b and adding one. Figure 1 shows a block diagram of the
add_sub8 two's complement adder/subtractor.

Figure 1: add_sub8 Block Diagram

The inputs a and b are stored in registers a_reg and b_reg at the positive edge of the clk
signal. The add_sub selector is also stored in a register. This stored value is used in the next
clock cycle as the carry-in to the adder and also to select b or the invert of b signal input to the
adder. The add/subtract operation takes one clock cycle with the result and overflow signal
available after the next positive clock edge. If the overflow signal is high an
overflow/underflow has been detected, and the value given by result is not a valid result of
the add/subtract operation.

3.1 Add anything that is appropriate to the report in

question here e.g. sub-component designs, pseudo-codes
(do not include Verilog code!)

4. Implementation Results
Present the results of your implementation here. This should include the logic resources
consumed by your design on FPGA, maximum speed achieved etc.
5. Evaluation and Final Conclusion
Discuss the results of your implementation here. This is your opportunity to show in-depth
understanding of the material. You can add extra features into your design, for instance,
discuss trade-offs etc.