LTC1264

High Speed, Quad Universal

Filter Building Block
U
FEATURES DESCRIPTIO
High Speed, Up to 250kHz Center Frequency The LTC 1264 consists of four identical, high speed 2nd
Four Identical Filters in a 0.3" Wide Package order switched-capacitor filter building blocks designed
Clock-to-Center Frequency Ratio of 20:1 for center frequencies up to 250kHz. Each building block,
Double-Sampling, Improved Aliasing together with three to five resistors, can provide 2nd order
Operates from 2.37V to 8V Power Supplies functions like lowpass, highpass, bandpass and notch.
Customized Version with Internal Resistors Available The center frequency of each 2nd order section is tuned via
Low Noise an external clock. The clock-to-center frequency ratio is
Low Harmonic Distortion internally set to 20:1, but it can be modified via external
Available in 24-Pin DIP and SO Wide Packages resistors.
U The aliasing performance of the LTC1264 is improved by
APPLICATIO S double-sampling each 2nd order section. Input signal
Digital Communications frequencies can reach up to twice the clock frequency
Spread Spectrum Communications before any alias products will be detectable.
Spectral Analysis For Q 5 and for TA < 85C, the maximum center
Loran Receivers frequency is 160kHz. For Q 2, the maximum center
Instrumentation frequency is 250kHz. Up to 8th order filters can be realized
, LTC and LT are registered trademarks of Linear Technology Corporation.
by cascading all four 2nd order sections.
All other trademarks are the property of their respective owners.
A customized monolithic version of the LTC1264 includ-
ing internal thin film resistors can be obtained.

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TYPICAL APPLICATIO
Clock-Tunable 8th Order Bandpass Filter, fCENTER = fCLK /20
50k
Gain vs Frequency
50k 100kHz Bandpass, f 3dB Bandwidth = fCENTER/10
IN INV B INV C
10k 10k
HPB/NB HPC/NC 10
50k 50k
BPB BPC 0
MAXIMUM POWER LPB LPC 10
fCENTER SUPPLY
160kHz 7.5V SB SC 20
LTC1264
120kHz 5V
GAIN (dB)

60kHz Single 5V AGND V 30

0.1F
V+ CLK fCLK 40
0.1F
SA SD 50
LPA LPD 60
50k OUT
BPA BPD 70
10k 50k
HPA/NA HPD/ND 80
10k 10k 100k 1M
INV A INV D FREQUENCY (Hz)
1264 TA02
50k
50k
1264 TA01

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LTC1264
W W W U U W U
ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
ORDER PART
Total Supply Voltage (V + to V ) .............................. 16V INV B 1 24 INV C
NUMBER
HPB/NB 2 23 HPC/NC
Input Voltage (Note 2) ........... (V + + 0.3V) to (V 0.3V) BPB 3 22 BPC
Output Short-Circuit Duration .......................... Indefinite LPB 4 21 LPC
LTC1264CN
SB 5 20 SC
Power Dissipation ............................................. 400mW AGND 6 19 V LTC1264CSW
Burn-In Voltage ...................................................... 16V V+ 7 18 CLK

Operating Temperature Range ............... 40C to 85C SA

LPA
8
9
17 SD
16 LPD
Storage Temperature Range ................ 65C to 150C BPA 10 15 BPD
Lead Temperature (Soldering, 10 sec).................. 300C HPA/NA 11 14 HPD/ND
INV A 12 13 INV D

N PACKAGE SW PACKAGE
24-LEAD PLASTIC DIP 24-LEAD PLASTIC SO (WIDE)
TJMAX = 110C, JA = 65C/W (N)
TJMAX = 110C, JA = 85C/W (S)

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25C.(Internal Op Amps) TA = 25C, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Operating Supply Range 2.375 8 V
Voltage Swings VS = 2.375V, RL = 5k 1.5 V
VS = 5V, RL = 5k 3.2 3.7 V
3.1 V
VS = 7.5, RL = 5k 6 V
Output Short-Circuit Current (Source/Sink) 3 mA
DC Open-Loop Gain 80 dB
GBW Product 7 MHz
Slew Rate 10 V/s

(Complete Filter) VS = 5V, fCLK = 1MHz, all sides mode 1, fO = 50kHz, Q = 5, TA = 25C, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Center Frequency Range, fO (Note 2) VS = 7.5V, TA < 85C, Q < 2 0.1 - 250 kHz
VS = 5V, TA < 85C, Q < 2 0.1 - 200 kHz
VS = 2.5V, TA < 85C, Q < 2 0.1 - 100 kHz
Clock-to-Center Frequency Ratio, fCLK /fO 20:1
Center Frequency Error (Note 4) VS = 7.5V 0.1 0.7 %
0.8 %
VS = 5V 0.2 0.8 %
1.0 %
VS = 2.375V 1.6 %
Clock-to-Center Frequency Ratio, VS 5V 0.4 0.8 %
Side-to-Side Matching 1.0 %
Q Accuracy VS = 5V 2.7 %
7.0 %
fO Temperature Coefficient fCLK < 2MHz 1 ppm/C
Q Temperature Coefficient fCLK < 2MHz 5 ppm/C
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 LTC1264
ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25C. (Complete Filter) VS = 5V, fCLK = 1MHz, all sides mode 1, fO = 50kHz,
Q = 5, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
DC Offset Voltage (Note 3) VOS1 (DC Offset of Input Inverter) 20 mV
VOS2 (DC Offset of First Integrator) 45 mV
VOS3 (DC Offset of Second Integrator) 45 mV
Clock Feedthrough VS = 7.5V (fCLK is a Square Wave) 160 VRMS
VS = 5V (fCLK is a Square Wave) 120 VRMS
VS = 2.375V (fCLK is a Square Wave) 90 VRMS
Maximum Clock Frequency VS = 7.5V, TA = 25C 6 MHz
Power Supply Current VS = 5V 9 14 23 mA
26 mA
Note 1: Absolute Maximum Ratings are those values beyond which the life Note 4: The center frequency fO, error is calculated as:
of a device may be impaired.
fO(measured) fO(ideal)
Note 2: Please refer to Typical Maximum Q vs Clock Frequency graphs. 100
fO (ideal)
Note 3: Calculations of output DC offsets of one 2nd order section. Also
see Block Diagram.

VOSN VOSBP VOSLP

MODE PINS 2, 11, 14, 23 PINS 3, 10, 15, 22 PINS 4, 9, 16, 21
1 VOS1[(1Q) + 1 ||HOLP ||] VOS3 /Q VOS3 VOSN VOS2
1b VOS1[(1/Q) + 1 + R2/R1] VOS3 /Q VOS3 (VOSN VOS2)(1 + R5/R6)
2 [VOS1(1 + R2/R1 + R2/R3 + R2/R4) VOS3(R2/R3)] VOS3 VOSN VOS2
[R4/(R2 + R4)] + VOS2[R2/(R2 + R4)]
3 VOS2 VOS3 VOS1[1 + R4/R1 + R4/R2 + R4/R3] VOS2(R4/R2)
VOS3(R4/R3)

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TYPICAL PERFOR A CE CHARACTERISTICS

Typical Maximum Q Typical Maximum Q Typical Maximum Q

vs Clock Frequency vs Clock Frequency vs Clock Frequency
26 26 20
A VS = 7.5V A VS = 5V A
24 24 VS = SINGLE 5V
22 TA 85C 22 TA 85C 18
TA 85C
20 20 16
TYPICAL MAXIMUM Q

TYPICAL MAXIMUM Q

A. MODES 1, 1b A. MODES 1, 1b
TYPICAL MAXIMUM Q

18 18 14 A. MODES 1, 1b
B. MODES 3, 3a B. MODES 3, 3a B. MODES 3, 3a
16 16
B B 12
14 14
12 12 10
B
10 10 8
8 8 6
6 6
4
4 4
2 2 2
0 0 0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 1.0 1.2 1.4 1.6 1.8 2.0
CLOCK FREQUENCY (MHz) CLOCK FREQUENCY (MHz) CLOCK FREQUENCY (MHz)
1264 G01 1264 G02
1264 G03

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 LTC1264
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TYPICAL PERFOR A CE CHARACTERISTICS
Typical Bandpass Gain Error Typical Bandpass Gain Error Typical Bandpass Gain Error
vs Clock Frequency vs Clock Frequency vs Clock Frequency
5 5 5
MODE 1 MODE 1 MODE 1
TYPICAL BANDPASS GAIN ERROR (dB)

TYPICAL BNADPASS GAIN ERROR (dB)

TYPICAL BANDPASS GAIN ERROR (dB)
Q=2 Q=4 VS = SINGLE 5V
4 TA = 25C 4 TA = 25C 4 TA = 25C

VS = 5V
3 3 3
VS = 5V Q=4

2 2 2
VS = 7.5V
Q=2
VS = 7.5V
1 1 1

0 0 0
2.0 2.4 2.8 3.2 3.6 4.0 2.0 2.4 2.8 3.2 3.6 4.0 1.3 1.4 1,5 1.6 1.7 1.8 1.9 2.0
CLOCK FREQUENCY (MHz) CLOCK FREQUENCY (MHz) CLOCK FREQUENCY (MHz)
1264 G04 1264 G05 1264 G06

Typical Bandpass Gain Error Ratio (fCLK /fO) vs

vs Clock Frequency Clock Frequency
5 20.5
MODE 3 VS = 5V BANDPASS OUT
TYPICAL BANDPASS GAIN ERROR (dB)

20.4 MODE 1
Q=4
4 TA = 25C 20.3 VS = 7.5V

20.2
VS = SINGLE 5V
Q = 10
3 20.1
fCLK /fO

20.0 Q=4
VS = 7.5V
2 19.9
19.8
Q=2
1 19.7
19.6
0 19.5
1 2 3 4 1 2 3 4
CLOCK FREQUENCY (MHz) CLOCK FREQUENCY (MHz)
1264 G15 1264 G11

Power Supply Current

Noise vs R2/R4 Ratio vs Supply Voltage
600 48
MODE 3 44
500 VS = 7.5V
40
POWER SUPPLY CURRENT (mA)

Q=2
f R2 36
fO = CLK
400 20 R4 32
NOISE (VRMS)

28
300 24
55C
20 25C
200 16 125C
12
100 8
4
0 0
0 0.2 0.4 0.6 0.8 1.0 0 2 4 6 8 10 12 14 16 18 20 22 24
RESISTOR RATIO (R2/R4) POWER SUPPLY VOLTAGE (V+ V )
1264 G12
1264 G14

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PI FU CTIO S
V +, V (Pins 7, 19): Power Supply Pins. The V + (Pin 7) and
the V (Pin 19) should each be bypassed with a 0.1F
capacitor to an adequate analog ground. The filters power
supplies should be isolated from other digital or high
voltage analog supplies. A low noise linear supply is
recommended. Using a switching power supply will lower
the signal-to-noise ratio of the filter. The supply during
power-up should have a slew rate less than 1V/s. When
V + is applied before V and V is allowed to go above
ground, a diode should clamp V to prevent latch-up.
Figures 1 and 2 show typical connections for dual and
single supply operation.
LTC1264
AGND (Pin 6): Analog Ground Pin. The filter performance
depends on the quality of the analog signal ground. For
either dual or single supply operation, an analog ground
plane surrounding the package is recommended. The
analog ground plane should be connected to any digital
ground at a single point. For dual supply operation, Pin 6
should be connected to the analog ground plane. For
single supply operation, Pin 6 should be biased at 1/2
supply and should be bypassed to the analog ground plane
with at least a 1F capacitor (Figure 2). For single 5V
operation and fCLK greater than 1MHz, pin 6 should be
biased at 2V. This minimizes passband gain and phase
variations.

ANALOG 1 24 ANALOG 1 24
GROUND GROUND
PLANE 2 23 PLANE 2 23

3 22 3 22
7.5V
4 21 * 4 21
+
5k
5 20 V *5 20*
0.1F
6 19 V +/2 6 19

7 LTC1264 18 + 7 LTC1264 18
7.5V 1F 5k V+
8 17 *8 17*
0.1F
9 16 9 16

10 15 10 15

11 14 11 14

12 13 12 13

DIGITAL DIGITAL
STAR STAR
GROUND 200 GROUND 200
SYSTEM SYSTEM
PLANE PLANE
GROUND GROUND
CLOCK CLOCK
SOURCE SOURCE

* OPTIONAL, 1N4148, 1N5819 1264 F01

* FOR MODE 3, THE S NODE PINS 5, 8, 1264 F02

17, 20 SHOULD BE TIED TO PIN 6

Figure 1. Dual Supply Ground Plane Connections Figure 2. Single Supply Ground Plane Connections

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LTC1264
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PI FU CTIO S
CLK (Pin 18): Clock Input Pin. Any TTL or CMOS clock HPB/NB, BPB, LPB, LPA, BPA, HPA, HPD, BPD, LPD,
source with a square wave output and 50% duty cycle LPC, BPC, HPC/NC (Pins 2, 3, 4, 9, 10, 11, 14, 15, 16,
(10%) is an adequate clock source for the device. The 21, 22, 23): Output Pins. Each 2nd order section of the
power supply for the clock source should not be the filters LTC1264 has three outputs which typically source 3mA
power supply. The analog ground for the filter should be and sink 1mA. Driving coaxial cables or resistive loads less
connected to clocks ground at a single point only. Table than 20k will degrade the total harmonic distortion perfor-
1 shows the clocks low and high level threshold values for mance of any filter design. When evaluating the distortion
a dual or single supply operation. or noise performance of a particular filter design imple-
Table 1. Clock Source High and Low Threshold Levels
mented with an LTC1264, the final output of the filter
should be buffered with a wideband noninverting high
POWER SUPPLY HIGH LEVEL LOW LEVEL
slew rate amplifier (Figure 3).
Dual Supply = 7.5V 2.18V 0.5V
Dual Supply = 5V 1.45V 0.5V
Dual Supply = 2.5V 0.73V 2.0V
Single Supply = 12V 7.80V 6.5V

Single Supply = 5V 1.45V 0.5V
LT1224
5k
+
A pulse generator can be used as a clock source provided
1264 F03
the high level on-time is greater than 0.2s. Sine waves are
not recommended for clock input frequencies less than Figure 3. Wideband Buffer
100kHz, since excessively slow clock rise or fall times
INV B, INV A, INV D, INV C (Pins 1, 12, 13, 24): Inverting
generate internal clock jitter (maximum clock rise or fall
Input Pins. These pins are the high impedance inverting
time 1s). The clock signal should be routed from the
inputs of internal op amps and they are susceptible to stray
right side of the IC package and perpendicular to it to avoid
capacitive connections to low impedance signal outputs
coupling to any input or output analog signal path. A 200
and power supply lines.
resistor between clock source and Pin 11 will slow down
the rise and fall times of the clock to further reduce charge SB, SA, SD, SC (Pins 5, 8, 17, 20): Summing Input Pins.
coupling (Figures 1 and 2). The summing pins connections determine the circuit
topology (mode) of each 2nd order section. Please refer to
Modes of Operation.

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ODES OF OPERATIO
For the definition of filter functions please refer to the
LTC1060 data sheet.
Mode 1
In Mode 1, the ratio of the external clock frequency to the
center frequency of each 2nd order section is internally
fixed at 20:1. Figure 4 illustrates Mode 1 providing 2nd
order notch, lowpass, and bandpass outputs. Mode 1 can
be used to make high order Butterworth lowpass filters; it
can also be used to make low Q notches and for cascading
2nd order bandpass functions tuned at the same center
frequency. Mode 1 is faster than Mode 3.
Please refer to the Maximum Frequency of Operation
paragraph under Applications Information for a guide to
the use of capacitor CC.
Mode 1b
Mode 1b is derived from Mode 1. In Mode 1b (Figure 5) two
additional resistors R5 and R6 are added to alternate the
amount of voltage fed back from the lowpass output into
the input of the SA (SB, SC or SD) switched-capacitor
summer. This allows the filters clock-to-center frequency
ratio to be adjusted beyond 20:1. Mode 1b maintains the
speed advantages of Mode 1 and should be considered an
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 LTC1264
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ODES OF OPERATIO
optimum mode for high Q designs with fCLK to fCUTOFF (or Mode 3
fCENTER) ratios greater than 20:1. In Mode 3, the ratio of the external clock frequency to the
Please refer to the Maximum Frequency of Operation center frequency of each 2nd order section can be
paragraph under Applications Information for a guide to adjusted above or below 20:1. Figure 6 illustrates Mode 3,
the use of capacitor CC. the classical state variable configuration, providing high-
pass, bandpass, and lowpass 2nd order filter functions.
CC Mode 3 is slower than Mode 1. Mode 3 can be used to
make high order all-pole bandpass, lowpass, and high-
R3 pass filters.
R2 Please refer to the Maximum Frequency of Operation
N S BP LP
paragraph under Applications Information for a guide to
R1
VIN the use of capacitor CC.
+

+ 1264 F04 Mode 2
1/4 LTC1264

AGND f
Mode 2 is a combination of Mode 1 and Mode 3, shown in
fi = CLK ; fO = fi; fn = fO
20 Figure 7. With Mode 2, the clock-to-center frequency ratio,
R2 R3
Q= R3
R2 ON
;H = ;H
R1 OBP
=
R1
fCLK /fO, is always less than 20:1. The advantage of Mode
HOLP = HON
2 is that it provides less sensitivity to resistor tolerances
than does Mode 3. As in Mode 1, Mode 2 has a notch
output which depends on the clock frequency, and the
Figure 4. Mode 1, 2nd Order Filter Providing Notch, notch frequency is therefore less than the center fre-
Bandpass and Lowpass Outputs
quency, fO.
Please refer to the Maximum Frequency of Operation
CC
paragraph under Applications Information for a guide to
the use of capacitor CC.
R6 R5
CC

R3

R2 R4
N S BP LP
R3
R1
VIN
+ R2
HP S BP LP
+ 1/4 LTC1264 1264 F05
R1
NOTE: R5 5k
VIN
+
AGND

f R6
fi = CLK ; fO = fi ;f =f
20 (R6 + R5) n O + 1/4 LTC1264 1264 F06

Q = R3 R6 ; H = R2 ; H =
R3
R2 (R6 + R5) ON R1 OBP
R4 ; Q = 1.005( R2) R4 ( 1 6.42R4
R1

( )
f R2 R3 R2 1
AGND fi = CLK ; fO = fi
)
R2 R6 + R5 20 R3
HOLP =
R1 R6

R3 1 R4
HOHP = R2 ; HOBP =
( )
; HOLP =
R1 R1 R3 R1
Figure 5. Mode 1b, 2nd Order Filter Providing Notch, 1
6.42R4
Bandpass and Lowpass Outputs
Figure 6. Mode 3, 2nd Order Section Providing
Highpass, Bandpass and Lowpass Outputs

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LTC1264
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ODES OF OPERATIO
CC
tors RH and RL to create a notch. This is shown in Figure
8. Mode 3a is more versatile than Mode 2 because the
R4
notch frequency can be higher or lower than the center
R3 frequency of the 2nd order section. The external op amp
R2
of Figure 8 is not always required. When cascading the
N S BP LP sections of the LTC1264, the highpass and lowpass
VIN
R1

outputs can be summed directly into the inverting input of
+
the next section.

+ 1/4 LTC1264
1264 F07
Please refer to the Maximum Frequency of Operation
AGND paragraph under Applications Information for a guide to
the use of capacitor CC.
1 + R4 ; f = f
fCLK R2
fi = ;f =f
20 O i n O

Mode 2n
Q = 1.005
R3
( ) 1 + R2R4 1 1R3
R2
( 6.42R4 ) This mode extends the circuit topology of Mode 3a to
R2
(AC GAIN, f > fn); HOHPn = R2
1 Mode 2 (Figure 9) where the highpass notch and lowpass
( )
HOHP = (DC GAIN, f < fn)
R1 R1 1 + R2
R4
outputs are summed through two external resistors RH
R3 1 and RL to create a lowpass output with a notch higher in
( )
HOBP = ; HOLP = HOHPn
R1
1
R3
6.42R4
frequency than the notch in Mode 2. This mode, shown in
Figure 8, is most useful in lowpass elliptic designs. When
Figure 7. Mode 2, 2nd Order Filter Providing Highpass
cascading the sections of the LTC1264, the highpass
Notch, Bandpass and Lowpass Outputs notch and lowpass outputs can be summed directly into
the inverting input of the next section.
Mode 3a Please refer to the Maximum Frequency of Operation
This is an extension of Mode 3 where the highpass and paragraph under Applications Information for a guide to
lowpass output are summed through two external resis- the use of capacitor CC.

CC

R f = f R4
R4 f R R2
fi = CLK ; fn = fi H
; O i
20 L
R3
Q = 1.005 ( R3)
R2 R4
R2 1
R2
HP S BP LP ( 6.42R4
1
R3
)
(f = ) = ( )( R2 ) ; H (f = 0) = ( )( R4 )
R1 R G R G
H OHPn OLPn
VIN RG
R R1
H R R1L
+

+ RL
HIGHPASS
1/4 LTC1264
RH OR LOWPASS
AGND
NOTCH OUTPUT
+
EXTERNAL OP AMP OR
INPUT OP AMP OF THE
LTC1264, SIDES A, B, C, D 1264 G08

Figure 8. Mode 3a, 2nd Order Filter Providing a Highpass Notch or Lowpass Notch Output

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 LTC1264
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ODES OF OPERATIO
CC

f
fi = CLK ; fn = fi 1 + RH
R4 20 RL

R2
R3 fO = fi 1+
R4

R2
HP S BP LP
(
R R
HOLPn (f = 0)= G + G R2
RH RL R1 )( ) ( 1
1 + R2 )
R4
R1
Q = 1.005( R3R2) 1 + R2R4 1

( )
VIN
+ RG R3

1
6.42R4

+ RL
LOWPASS
RH NOTCH
AGND
OUTPUT
+
1/4 LTC1264 EXTERNAL OP AMP OR
INPUT OP AMP OF THE
LTC1264, SIDES A, B, C, D 1264 G09

Figure 9. Mode 2n, 2nd Order Filter Providing a Lowpass Notch Output

W
BLOCK DIAGRA
HPA/NA BPA LPA
11 10 9 7 V+
INV A 12
18 CLK
+
+ +
19 V
AGND 6 +
8
HPB/NB BPB LPB
SA
2 3 4
INV B 1
+
+ +
+
5
HPC/NC BPC LPC
SB
23 22 21
INV C 24
+
+ +
+
20
HPD/ND BPD LPD
SC
14 15 16
INV D 13
+
+ +
+
17
1264 BD
SD

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LTC1264
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APPLICATI S I FOR ATIO
Operating Limits
The Typical Maximum Q vs Clock Frequency and Band-
pass Gain Error graphs, under Typical Performance Char-
acteristics, define an upper limit of operating Q for each
LTC1264 2nd order section. These graphs indicate the
power supply, fCLK and Q value conditions under which a
filter implemented with an LTC1264 will remain stable
when operated at temperatures of 85C or less. For a 2nd
order section, a bandpass gain error of 3dB or less is
arbitrarily defined as a condition for stability.
When the passband gain error begins to exceed 1dB, the
use of capacitor CC will reduce the gain error (capacitor CC
is connected from the lowpass node to the inverting node
of a 2nd order section). Please refer to Figures 4 through
9. The value of CC can be best determined experimentally,
and as a guide it should be about 5pF for each 1dB of gain
error and not to exceed 15pF. When operating LTC1264
very near the limits defined by the Typical Performance
Characteristics graphs, passband gain variations of 2dB
or more should be expected.
Speed Limitations
To avoid op amp slew rate limiting, the signal amplitude
should be kept below a specified level as shown in Table 2.
Table 2. Maximum VIN vs VS and Clock
VS MAXIMUM CLOCK MAXIMUM VIN
7.5V 4MHz to 5MHz 0.5VRMS fIN 400kHz
5V 3MHz to 4MHz 0.5VRMS fIN 250kHz
Single 5V 1MHz to 2MHz 0.35VRMS fIN 160kHz
Clock Feedthrough
Clock feedthrough is defined as the RMS value of the clock
frequency and its harmonics that are present at the filters
output pins. The clock feedthrough is tested with the
filters input grounded and it depends on PC board layout
and on the value of the power supplies. With proper layout
techniques, the typical values of clock feedthrough are
listed under Electrical Characteristics.
Any parasitic switching transients during the rise and fall
edges of the incoming clock are not part of the clock
10
feedthrough specifications. Switching transients have fre-
quency contents much higher than the applied clock; their
amplitude strongly depends on scope probing techniques
as well as grounding and power supply bypassing. The
clock feedthrough, if bothersome, can be greatly reduced
by adding a simple RC lowpass network at the final filter
output. This RC will completely eliminate any switching
transients.
Wideband Noise
The wideband noise of the filter is the total RMS value of
the devices noise spectral density and it is used to
determine the operating signal-to-noise ratio. Most of its
frequency contents lie within the filter passband and it
cannot be reduced with post filtering.
The total wideband noise (VRMS) is nearly independent of
the value of the clock. The clock feedthrough specifica-
tions are not part of the wideband noise.
For a specific filter design, the total noise depends on the
Q of each section and the cascade sequence. Table 3
shows typical 2nd order section noise (gain = 1) for Q
values and supplies operating at 25C. Noise increases by
20% at the highest operating temperatures.
Table 3. 2nd Order Section Noise (VRMS) for Modes 1, 1b,
2 or 3 (R2 = R4)
Q VS = 2.5V VS = 5V VS = 7.5V
1 40VRMS 50 60
2 50VRMS 60 75
3 60VRMS 75 95
4 75VRMS 90 115
5 90VRMS 110 135
Aliasing
Aliasing is an inherent phenomenon of switched-capacitor
filters and it occurs when the frequency of input signals
approaches the sampling frequency. The input signals
that produce the strongest aliased components have a
frequency, fIN, such as (fSAMPLING fIN) falls into the
filters passband. For the LTC1264 the sampling fre-
quency is twice fCLK. If the input signal spectrum is not
band-limited, aliasing may occur.
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 LTC1264
UO U W U
APPLICATI S I FOR ATIO
For example, for an LTC1264 bandpass filter with fCENTER Table 4. Bandpass Design Specifications (fCENTER is center
frequency of passband.)
= 100kHz and fCLK = 2MHz, a 3.9MHz, 10mV input will
produce a 100kHz, 10mV output. A 1st or 2nd order PASSBAND PASSBAND STOPBAND ATTENU-
RIPPLE WIDTH WIDTH ATION
prefilter will reduce aliasing to acceptable levels in most (dB) (Hz) (Hz) (dB)
cases. 3dB for Butterworth fCENTER /20 5 Passband 40 to 60
0.1 for Chebyshev fCENTER /20 5 Passband 40 to 60
A GUIDE TO BANDPASS DESIGN Note: Reducing passband ripple or attenuation will decrease Q values. The
filter order may also increase.
Filter design tools like FCAD require design specification
inputs such as passband ripple, attenuation, passband Table 5. Calculated Filter Parameters
width and stopband width in order to calculate filter STAGE fO Q
parameters fO, Q, fn or poles and zeroes. The results of 1 38.1201kHz 4.3346
these filter approximations most often require Q values 2 41.9726kHz 4.3346
which make excessive demands on the gain-bandwidth 3 35.6418kHz 10.5221
products of active filter realizations. The active filter de- 4 44.8911kHz 10.5221
signer should define a gain response so that the filters
mathematical approximation has practical requirements. Table 6. Calculated Mode 1b Resistors to Nearest 1% Value
Table 4 is a guide to practical design specifications for Using Table 5 Filter Parameters and Figure 10 Equations
realizing bandpass filters with LTC1264 (please also refer STAGE R1 R2 R3 R5 R6
to the Typical Maximum Q vs Clock Frequency and Band- 1 52.3k 10k 56.2k 5k 6.98k
2 47.5k 10k 51.1k 5k 11.8k
pass Gain Error graphs under Typical Performance Char- 3 56.2k 10k 147k 5k 5.11k
acteristics). 4 44.2k 10k 118k 5k 20.5k

A Bandpass Design Example

Filter Type: Bandpass R2 = 10k
R5 = 5k
Filter Response: Butterworth f
fi = CLK
Passband Ripple: 3dB 20

Attenuation: 60dB R1 = R3 (FOR BANDPASS)

HOBP
Center Frequency: 40kHz (fCENTER) R6 =
R5fO
2

Passband Width: 10kHz ( fi2

fO
2
)

Stopband Width: 60kHz
( ) ( )
2
2 fO fCENTER
HOBP = Q +1
fCENTER fO
Implementing the Bandpass Design
R3 = R2Q

(
R6
With the LTC1264 in Mode 1b, Butterworth and Chebyshev R6 + 5 )
bandpass designs with fCLK to fCENTER ratios greater than 1264 F10

20:1 are possible. Figure 10. Equations for Resistors in Mode 1b Operation
First choose the clock frequency which in Mode 1b must
be greater than 20 times the bandpass center frequency of
40kHz. For this example, lets choose fCLK to be 1MHz.
Table 6 lists the resistors for for the bandpass design
example and Figure 11 shows the complete circuit.

1264fb

11
LTC1264
UO U W U
APPLICATI S I FOR ATIO
R1 first stage and decreasing the R1 resistor of the last stage
R1 by the same amount (multiplying the R1 resistor of the
IN
R2
INV B INV C
R2
first stage and dividing the R1 resistor of the last stage by
R3
HPB/NB HPC/NC
R3
2 for narrowband filter, and by 5 for wideband filter is a
STAGE 1 BPB BPC STAGE 2
good rule of thumb). This adjustment may, however,
R5
LPB LPC
R5
increase the filters passband noise.
SB SC
LTC1264
R6 AGND V R6
1.0
R6 V+ CLK fCLK R6 MODE 1b
0.5 VS = 7.5V
SA SD fCLK = 1MHz
R5 R5 0
fCLK /fCENTER = 25:1
LPA LPD 0.5
STAGE 3 BPA BPD STAGE 4 1.0

GAIN (dB)
R3 R3
HPA/NA HPD/ND 1.5
R2 R2
INV A INV D 2.0
OUT
R1 2.5
R1
3.0
1264 F11
3.5
4.0
Figure 11. Mode 1b Bandpass Filter 30 32 34 36 38 40 42 44 46 48 50
FREQUENCY (kHz)
1264 F12

Figures 12 and 13 show the gain response graphs of the

Figure 12. Passband Gain vs Frequency
40kHz Butterworth bandpass design described above. The 40kHz Butterworth Bandpass
passband gain response graph (Figure 12) shows a 40kHz
gain of 0.4dB and a tilted passband from 37kHz to 43kHz.
These errors are due to the 1% resistors used and the side- 10
MODE 1b
to-side matching of the LTC1264 fCLK-to-fCENTER ratio 0 VS = 7.5V
fCLK = 1MHz
which typically is 0.4%. To adjust for 0dB gain at 40kHz, 10
fCLK /fCENTER = 25:1
20
reduce the value of R1 in the first stage by 5%. To adjust
for a flat passband, adjust by 1% the value of R6 in stages 30
GAIN (dB)

40
3 and 4. Adjusting R6 compensates for the side-to-side
50
matching errors. Please refer to Figure 5 equations defin- 60
ing fO and Q as a function of R6. 70

The sequence of 2nd order stages and the bandpass gain 80

HOBP of each stage will determine the gain peaks at the 90

10 18 26 34 42 50 58 66 74 82 90
filters intermediate outputs. A given internal output can FREQUENCY (kHz)
1264 F13

have several dB more gain than the final filter output. Gain
peaks occur around the corners of the passband. The gain Figure 13. Gain vs Frequency
peaks can be reduced by increasing the R1 resistor of the 40kHz Butterworth Bandpass

1264fb

12
 LTC1264
UO
TYPICAL APPLICATI S
Linear Phase Clock-Tunable to 400kHz, Dual 4th Order Lowpass Filter Gain vs Frequency
R1
0
R1 OUT 1
IN 1 INV B INV C 10
R2 R2
HPB/NB HPC/NC 20
R3 R3
BPB BPC 30
R4 R4

GAIN (dB)
LPB LPC
C 40
C
SB SC
LTC1264 50
0.1F
AGND V 8V
0.1F 60
8V V+ CLK fCLK
C C 70
SA SD
R4
LPA LPD 80
R3 R4 10k 100k 1M
BPA BPD FREQUENCY (Hz)
R2 R3 1264 TA04b
HPA/NA HPD/ND
R1 R2
IN 2 INV A INV D
OUT 2
R1

LTC1264 SIDE B C A D fCLK f 3dB (VS = 8V)

MODE 2 2 2 2 2MHz 125kHz
R1 17.8k 20k 17.8k 20k 3MHz 200kHz
R2 27.4k 27.4k 27.4k 27.4k 4MHz 275kHz
R3 19.6k 21k 19.6k 21k 5MHz 400kHz
R4 51.1k 75k 51.1k 75k TA 50C
1264 TA04a
C 5pF 5pF 5pF 5pF

Clock-Tunable, fCENTER = fCLK /20, 100kHz, 4th Order Bandpass and Notch Filters Gain vs Frequency
R1
10
R1
BANDPASS IN 0
INV B INV C
R2 R2
10
HPB/NB HPC/NC
R3 R3
BPB 20
BPC
GAIN (dB)

LPB BANDPASS OUT 30

LPC

SB 40
0.1F SC
LTC1264
AGND V 7.5V 50
fCLK 0.1F 60
7.5V V+ CLK 2MHz
70 VS = 7.5V
SA SD fCLK = 2MHz
LPA LPD NOTCH OUT 80
R3 10k 100k 1M
R3
BPA BPD FREQUENCY (Hz)
R2 R2 1264 TA05b
HPA/NA HPD/ND
R1 C C
NOTCH IN INV A INV D
R1

LTC1264 SIDE B C A D
MODE 1 1 1 1
R1 20k 20k 10k 10k
R2 10k 10k 10k 10k
R3 20k 20k 20k 20k
C 10pF 10pF 1264 TA05a

1264fb

13
LTC1264
UO
TYPICAL APPLICATI S
100kHz, 8th Order Notch Filter, fCLK /fCENTER = 20:1 Gain vs Frequency
R1
10

C 0
R1
IN INV B INV C 10
R2 R2
HPB/NB HPC/NC 20
R3 R3

GAIN (dB)
BPB BPC 30
LPB LPC 40

0.1F SB SC 50
LTC1264
AGND V 7.5V 60
fCLK 0.1F VS = 7.5V
7.5V V+ CLK 70
2MHz fCLK = 2MHz
SA SD 80
10k 100k 1M
LPA LPD OUT
R3 FREQUENCY (Hz)
R3
1264 TA06b
BPA BPD
R2 R2
HPA/NA HPD/ND LTC1264 SIDE B C A D
C MODE 1 1 1 1
INV A INV D R1 36.5k 3.92k 7.5k 9.09k
R1 R2 10k 10k 10k 10k
R1 R3 50k 27.4k 50k 50k
C 30pF 30pF
1264 TA06a

Clock-Tunable, 8th Order Elliptic Lowpass Filter, fCLK /fCUTOFF = 20:1 Gain vs Frequency
RL
0
RH VS = 7.5V
10 fCLK = 2MHz
R1
IN INV B INV C 20
R2 R2
HPB/NB HPC/NC
R3 R3 30
GAIN (dB)

BPB BPC
R4 R4 40
LPB LPC
C 50
0.1F SB SC
LTC1264
60
AGND V 7.5V

7.5V V+ CLK 70
C 0.1F RL RH
SA SD 80
R4 fCLK 10k 100k 1M
LPA LPD 2MHz FREQUENCY (Hz)
R3 R4 1264 TA03b
BPA BPD
R2 R3
HPA/NA HPD/ND
R2
INV A INV D
OUT LTC1264 SIDE B C A D
RH
MODE 3a 2n 2n 3
RL R1 27.4k
R2 23.7k 20k 20k 29.4k
R3 20k 37.4k 37.4k 19.1k
1264 TA03a POWER SUPPLY MAXIMUM fCLK R4 28k 100k 100k 48.7k
7.5V 3.6MHz (C = 10pF) RH 137k 100k 130k
5V 2.0MHz (C = 10pF) RL 27.4k 31.6k 24.3k
SINGLE 5V 1.6MHz (C = 10pF) C 3pF 3pF
1264fb

14
 LTC1264
U
PACKAGE DESCRIPTIO
N Package
24-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
1.280*
(32.512)
MAX
24 23 22 21 20 19 18 17 16 15 14 13

.255 .015*
(6.477 0.381)

1 2 3 4 5 6 7 8 9 10 11 12

.300 .325 .130 .005 .045 .065

(7.620 8.255) (3.302 0.127) (1.143 1.651)

.020
(0.508)
MIN .065
(1.651)
.008 .015 TYP
(0.203 0.381) N24 0405
.120
+.035 .100 .018 .003
.325 .015 (3.048)

( )
MIN (2.54) (0.457 0.076)
+0.889 BSC
8.255
0.381
NOTE:
INCHES
1. DIMENSIONS ARE
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)

SW Package
24-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)

.030 .005 .050 BSC .045 .005

TYP .598 .614
(15.190 15.600)
N NOTE 4
24 23 22 21 20 19 18 17 16 15 14 13

N
.420 .325 .005
MIN

NOTE 3 .394 .419

(10.007 10.643)

1 2 3 N/2
N/2

RECOMMENDED SOLDER PAD LAYOUT

.291 .299 1 2 3 4 5 6 7 8 9 10 11 12
(7.391 7.595)
NOTE 4
.093 .104 .037 .045
.010 .029 45 (0.940 1.143)
(2.362 2.642)
(0.254 0.737)
.005
(0.127)
RAD MIN 0 8 TYP

.050
(1.270) .004 .012
.009 .013
NOTE 3 BSC (0.102 0.305)
(0.229 0.330) .014 .019
.016 .050
(0.356 0.482)
(0.406 1.270)
NOTE: TYP
INCHES
1. DIMENSIONS IN S24 (WIDE) 0502
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
1264fb

15
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC1264
UO
TYPICAL APPLICATI
8th Order Bandpass Filter, Linear Phase
RH

RL
R1
VIN INV B INV C LTC1264 SIDE B C A D
R2 R2 MODE 3a 3 3a 3
HPB/NB HPC/NC R1 97.6k 32.4k
R3 R3
BPB BPC R2 10.7k 12.4k 10.7k 10.0k
R4 R4 R3 39.2k 39.2k 12.4k 29.4k
LPB LPC R4 13.3k 10.7k 11.5k 10.0k
C RH 53.6 27.4k
0.1F SB SC
LTC1264 RL 15.0k 100.0k
AGND V 7.5V
0.1F
7.5V V+ CLK 1MHz fCLK C
1MHz 0pF
SA SD 1.5MHz 5pF
R4 R4
LPA LPD 2.0MHz 10pF
R3 R3 1264 TA07a
BPA BPD
R2 R2
HPA/NA HPD/ND

INV A INV D
VOUT
RH
R1

RL

50kHz Bandpass Filter, Linear Phase

Gain vs Frequency Passband Gain and Group Delay
10 3 124
VS = 7.5V
0 0 114
fCLK = 1MHz GAIN
10 3 104
20 6 94

GROUP DELAY (s)

30 9 84
GAIN (dB)

GAIN (dB)

DELAY
40 12 74
50 15 64
60 18 54
70 21 44
80 24 34
90 27 24
10k 100k 1M 40 42 44 46 48 50 52 54 56 58 60
FREQUENCY (Hz) FREQUENCY (kHz)
1264 TA07b
1264 TA07c

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1264fb

Linear Technology Corporation LT/LT 0805 REV B PRINTED IN USA

16 1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 FAX: (408) 434-0507
www.linear.com LINEAR TECHNOLOGY CORPORATION 1993