COMPUTER ORGANIZATION & ARCHITECTURE (EMT475/3)

LAB 1: Combinational Logic: Designing and Simulation of Arithmetic Logic

Unit ALU using VHDL
Outcome:
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1) Identify the operation techniques
2) Demonstrate the use of architecture types
3) Identify and describe the operation of an ALU
4) Develop a simple VHDL program in Altera Quartus II software

Introduction
Dataand signals can be represented in various forms. Previously, we have studied and exercised in Pre-
Lab that typing an architecture for an entity is by assigning a signal and data to a certain port declared as
in a dataflow process.In fact the forms of behavioral written formats can either be concurrent or sequential
.Below we will discuss the types of approach that can be used to type a VHDL behavioral approach in
the architecture.

A VHDL architecture contains a set of concurrent statements. Each statement defines one of the connect
ed block or processes that describe the overall behavior or structure of a design. For a structured stateme
nt, we use the port mapping techniques and instantiation declarations as described in Pre-Lab.

When we say concurrent, this means that for each block or process are done and executed cont
inuously. The modeling choices for a behavioral approach can be described as follows:

1. Dataflow Style or concurrent assignment statement

2. Procedural Style or sequential assignment statement

Both of these styles are the two main concurrent statements and can either be apart or nested together in
side an architecture. Nesting of statements:

1. Concurrent statements inside a concurrent statement

2. Sequential statements inside a concurrent statement
3. Sequential statements inside a sequential statement

For the purpose of this lab we will learn some of the modeling techniques commonly used.

Concurrent Assignment Statement

1. Simple signal assignments
Target <= expression;

2. Conditional signal assignments

Target <= {expression WHEN condition ELSE}
expression;

3. Selected signal assignments

With choice_expression select
Target <= {expression WHEN choices}
expression WHEN choices;

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Sequential Assignment Statement

Done inside a process after the declaration and begininng of the architecture.

1. If statement
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Process (sensitivity_list, [sensitivity_list])
Begin
If condition then
{sequential statement;}
Elsif condition then
{sequential statement;}
Else
sequential statement;}
End if;
End process;

2. Case statement

Process (sensitivity_list, [sensitivity_list])

Begin
Case (expression) is
When (choices) =>
{sequential statement;}
{When (choices) =>
{sequential statement;}}
End case;
End process;

Example: ALU Design (Please perform this part before attending lab session)
One essential function of most computers and calculators is the performance of arithmetic operations.
These operations are all performed in the Arithmetic Logic Unit or ALU inside the CPU of a computer,
where logic gates and registers are combined so that they can add, subtract, multiply and divide binary
numbers.

Figure 1

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Figure 1 illustrates a block diagram of major elements included for atypical ALU. The main purpose of the
ALU is to accept binary data that are stored in the memory and to execute arithmetic and logic operations
according to instructions from the control unit as in Figure 2.

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Figure 2

The VHDL model (Figure 2) for the function table (Table 1) can be designed as follows:

Figure 3

1. Open new project in Altera Quartus II software (refer Pre-Lab)

2. Write down the VHDL code given in Figure 3 and run the code compilation.
3. Generate the waveform for the simple_alu design and verify the functionality.

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Task / Assignment:
Design an 8 bit Arithmetic Logic Unit (ALU) that could perform the operation list in the Table 1:

Table 1: Opcode and its operation Page | 4

Opcode Operation
00 A+B
01 AB
10 A and B
11 A or B

Write down the VHDL code and generate the waveform. Verify your work by demonstrate the
coding and waveform to Lab Instructor.

* You are advice to save your work as you will use back the design later

LAB REPORT
Cover page
Introduction (describe briefly on ALU less than 200 words)
Objectives
Methodology: VHDL Model/Coding & explanation
Results & discussion
Example: ALU design (4-bit ALU)
Waveform
RTL Viewer
Task/Assignment (8-bit ALU)
Waveforms
RTL Viewer
Conclusion

REMINDER
Please uses Lab Report Template as provided in Portal.
Please submit lab report within ONE (1) week after your lab session.
If you failed to follow the rules, Deduction Mark Penalty will be applied.

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