Cairo Electronics and

University Electrical
Faculty of Communications
Engineering Engineering Department

EEC 506 VLSI Computer-Aided Design

MSc/PhD Program 1437-1438 (2016-2017) - Term 1
Major Exam 90 Minutes


Question 1 Layout Compaction


a. [2 marks] Sketch the Constraint Graph of X-direction layout compaction generated

from the irredundant constraints of the following modules whose dimensions and

vertical positions are indicated as shown, given that the minimum separation is 2.
7 8
3 4
5 6 23

25 23

9 1
1 2
52 34

b. [3 marks] Use the longest-path algorithm to find the minimum width of the layout compaction
problem given in part (a).

Question 2 Placement and Partitioning

[5 marks] Use Kernighan and Lin heuristic partitioning algorithm to improve the cut cost of the
following initial 2-way graph partition, where { } and { } until no further
improvement is possible.

2

a a
3
4 1

2
3
a a
2 4 2

3
c
a a
Question 3 Floorplanning

a. [3 marks] Find the best shape(s) for the H-Cut Slicing floorplan of the two flexible-shape
modules A and B, where A is 35 or 44 or 53, and B is 45 or 54 or 63.

b. [4 marks] Sketch the tree representation of the slicing floorplan given by the following polish expression

| | | |

where and are 12 4,

and are 4 4,

and are 4, and

and are .

Sketch the 2D layout of the given floorplan, and determine its minimum total area.

Question 4 Routing

a. [3 marks] Use Hadlocks routing algorithm to find the shortest path between S and T in the
following grid graph.

b. [5 marks] Use the left-edge algorithm to solve the following 2-layer channel routing problem, and
find the minimum number of tracks.

1 0 8 2 0 1 5 6 3 5 8 0

2 9 6 3 7 0 2 7 4 6 9 4