Properties of heterojunction diode based on and its application for

phase change random access memory

Li Tang, Peng Zhou, Haijun Wan, Gang Jin, B. A. Chen, Ting-ao Tang, and Yinyin Lin

Citation: Journal of Applied Physics 105, 061627 (2009); doi: 10.1063/1.3055417

View online: http://dx.doi.org/10.1063/1.3055417
View Table of Contents: http://aip.scitation.org/toc/jap/105/6
Published by the American Institute of Physics
 JOURNAL OF APPLIED PHYSICS 105, 061627 2009

Properties of p-n heterojunction diode based on Ge2Sb2Te5 and its

application for phase change random access memory
Li Tang, Peng Zhou,a Haijun Wan, Gang Jin, B. A. Chen, Ting-ao Tang, and Yinyin Linb
ASIC and System State Key Laboratory, School of Microelectronics, Fudan University, Shanghai
200433, Peoples Republic of China
Received 29 June 2008; accepted 25 October 2008; published online 16 March 2009
Heterojunction diodes are fabricated using p-type Ge2Sb2Te5 and low doped n-type silicon wafer.
Rectification is observed with a ratio of forward-to-reverse current as high as 104 and 103 for
crystal-Ge2Sb2Te5 / n-Si junction and amorphous-Ge2Sb2Te5 / n-Si junction, respectively. The
approximate equilibrium energy-band diagrams for both crystal-Ge2Sb2Te5 / n-Si heterojunction
diodes and amorphous-Ge2Sb2Te5 / n-Si heterojunction diodes are proposed to explain the properties
of the p-Ge2Sb2Te5 / n-Si heterojunction diode. Properties of a p-n heterojunction diode based on
Ge2Sb2Te5 are proposed to apply in 0T1R cross-point structure array for reliable read operation and
for decreasing the sneaking current. 2009 American Institute of Physics.
DOI: 10.1063/1.3055417

I. INTRODUCTION diode has a W/p-GST/n-Si/Al structure. First, the n-type sili-

con wafer a the thickness of 300 m, whose doping concen-
Recently, phase change random access memory
tration is about 6.92 1014 cm3, is selected as n-type semi-
PCRAM has been the subject of considerable interest as a
conductor. Its crystal orientation is 100. The fabrication
potential for next-generation nonvolatile solid-state memory
process is described as follows. The n-type silicon wafer was
technology for its advantages, such as high resistance con-
first cleaned by RCA clean process. Then, the lithography
trast, fast program/read speed, good endurance, and compat-
process was done for the diodes area definition. The GST
ibility with complementary metal-oxide semiconductor
film with the thickness of 235 nm was deposited on the
technology.14 Phase change material is transformed to the
n-type silicon wafer by rf sputtering the GST alloy target in
amorphous phase and crystal phase by applying current
a LAB600SP high vacuum multitarget magnetron sputtering
pulses. An electrical current of moderate intensity sustained
system with an Ar working pressure of 8.0 103 mbar. Fur-
long enough to trigger the amorphous-to-crystalline transi-
ther, 80 nm of tungsten, used as top electrode, was sputtered
tion is used to write the information from 0 to 1. A pulse
in the same sputtering system by dc magnetron sputtering
of an electrical current of high intensity is used to erase the
with an Ar working pressure of 8.1 103 mbar. Aluminum
information by bringing the material back to its amorphous
was evaporated on the back side of the n-type silicon wafer
state by a melting-quenching process. One of typical phase
and a large area Ohmic contact was affirmatively formed
change material used in PCRAM is Ge2Sb2Te5 GST, which
between Al and the n-type silicon wafer. Finally, the GST
has good threshold and memory switching characteristics;5 it
film and tungsten film were patterned by the lift-off process.
has been considered as a p-type semiconductor.6 Since the
The sputtered GST film in the W/p-GST/n-Si/Al structure
cross-point structure was first proposed for use in magnetic
can be transformed from the amorphous phase to crystal
random access memory,7,8 it has become a hot research in
phase by 300 C annealing process for 10 min. Both
PCRAM for high-density data-storage application.9 How-
crystal-GST/n-Si and amorphous-GST/n-Si express the het-
ever, the sneaking current existing in the cross-point struc-
erojunction diode characteristics as GST in the crystal state
ture array of PCRAM greatly increases the power of
and amorphous state, respectively.
PCRAM, which further confines its low power application.
Figure 2b shows the circuit of the W/p-GST/n-Si/Al
The purpose of this paper is to report the electrical char-
structure as shown in Fig. 1a. A heterojunction diode would
acteristics of a heterojunction diode fabricated using GST as
be formed and thin film GST could also be used as resistance
the p-type material and to further propose its application in
switching element, so this structure could be equivalent to a
the cross-point structure array of PCRAM.
1D1R from the view of the circuit.

II. HETEROJUNCTION DIODE FABRICATION

In this experiment, we propose to employ GST as the

p-terminal of a heterojunction diode first and to relatively
use n-type silicon wafer as the n-terminal of the heterojunc-
tion diode. As shown in Fig. 1a, the p-n heterojunction

a
Electronic mail: pengzhou@fudan.edu.cn. FIG. 1. a The structure of the p-n heterojunction diode. b Circuit of the
b
Electronic mail: yylin@fudan.edu.cn. structure.

0021-8979/2009/1056/061627/3/$25.00 105, 061627-1 2009 American Institute of Physics

061627-2 Tang et al.
FIG. 2. Color online The I-V characteristics of heterojunction based on
Ge2Sb2Te5 and n-silicon. a Linear coordinate. b Log coordinate.
III. PROPERTIES OF HETEROJUNCTION DIODE
The current-voltage characteristic of the
W/p-GST/n-Si/Al structure was analyzed by a Keithley
4200.The forward voltage bias was applied on the top elec-
trode. The current-voltage characteristic shown in Fig. 2 can
be approximately regarded as the current-voltage character-
istic of p-GST/n-Si heterojunction for the W/p-GST and
n-Si/Al Ohmic contact formation. First, the diode cell with
an area of 180 180 m2 was measured by voltage sweep-
ing mode from 3 to +3 V. An annealling step with 300 C
conditions was subsequently carried out for 10 min, which
changes the diode cells GST from amorphous to crystalline.
Then, the same diode cell was repeatedly measured by volt-
age sweeping. Figure 2a shows the typical current-voltage
characteristic of a heterojunction diode with linear coordi-
nate, while Fig. 2b shows the current-voltage characteristic
with log coordinate of the same cell. The rectification is evi-
dently exhibited in both crystal-GST/n-Si junction and
amorphous-GST/n-Si junction. The ratio of the forward cur-
rent and the reverse current under the voltage of 2V was
about 104 and 103 for crystal-GST/n-Si junction and
amorphous-GST/n-Si junction respectively from Fig. 2b.
Compared with the forward current of amorphous GST/n-Si
junction, the forward current of crystal GST/n-Si junction is
larger, which is caused by lower resistivity of crystal-GST
than amorphous-GST. The turn-on voltage estimated from
Fig. 1a is about 1.1 V. Figure 3 shows the plot of a diode
factor against bias voltage of the heterojunction diode with-
out consideration of the series resistance effect caused by
FIG. 3. Color online The diode factor with different bias voltages of
p-GST/n-Si heterojunction diode.
J. Appl. Phys. 105, 061627 2009
FIG. 4. The approximate equilibrium energy-band diagram for the
p-GST/n-Si heterojunction diode. a Crystalline-GST/n-Si. b Amorphous
GST/n-Si.
GST and n-silicon. The diode factor of amorphous-GST/n-Si
heterojunction diode is larger than of crystal-GST/n-Si het-
erojunction diode.
From the view of the energy band, an approximate equi-
librium energy-band diagram for the p-GST/n-Si heterojunc-
tion diode is shown in Fig. 4. Amorphous GST, with a band
gap of 0.7 eV,6 has a high density of donor/acceptor defects
and presents p-type semiconductor characteristic, so that its
Fermi level EF is closely positioned above the valence band.
Crystal GST has relatively small band gap about 0.5 eV.
Acceptorlike traps are the major carriers in crystal GST,
which leads to present p-type semiconductor characteristic,
and its Fermi level EF is positioned slightly above the va-
lence band. The n-type silicon wafer, with 6.92
1014 cm3 carrier concentration, has the band gap of 1.14
eV that greatly mismatches with GST both for crystal and
amorphous. When forward voltage is applied on GST, elec-
trons can be easily transferred from the silicon conduction
band to the GST conduction band. On the contrary, when
forward voltage is applied in n-Si, carriers must conquer the
high energy barrier for transferring from the GST valence
band to the silicon valence band, which exhibits low reverse
current for the p-GST/n-Si heterojunction diode as shown in
Fig. 2. Compared to the crystal-GST/n-Si energy-band dia-
gram shown in Fig. 4b, the amorphous-GST/n-Si junction,
shown in Fig. 4a, has a higher energy barrier for carriers
transferring from the GST valence band to the silicon va-
lence band, so that the reverse current of the
amorphous-GST/n-Si heterojunction diode is larger than that
of crystal-GST/n-Si heterojunction diode as shown in Fig.
2b.
IV. HETEROJUNCTION DIODE APPLICATION
The p-GST/n-Si heterojunction diodes both for crystal-
line and amorphous states have good rectification character-
istics, which makes it usable in an array of PCRAM. Since
Chen et al.9 proposed the 0T1R cross-point structure tran-
sistor free resistance random access memory in PCRAM,
the area of the PCRAM cell could shrink to 4F2. However,
sneaking current is one of the prominent problems in the
0T1R cross-point structure in PCRAM, especially when it is
used in large block size. Figure 5a shows a 3 3 block
cross-point array of PCRAM. Phase change memory cells
locate between word and bit lines. If one of the cells, the
gray one shown in Fig. 5a, is selected to program, the cur-
061627-3 Tang et al.
FIG. 5. Color online The application of heterojunction in cross-point array
comprising phase change elements.
rent mainly passes the selected cell. However, dashed lines
marked in Fig. 5a other current paths would synchro-
nously pass other inactive cells, which is known as the
sneaking current. It can be obviously noticed that the sneak-
ing current paths greatly increase as the block size increases,
which confines the 0T1R cross-point structure only applied
in small size block arrays for PCRAM. At the same time, the
read operation of the selected cell will suffer substantial dis-
turbance from the sneaking current. Figure 5b shows a 3
3 block cross-point array of PCRAM with heterojunction
diodes located between word and bit lines. The heterojunc-
tion diode can be formed by the p-GST/n-Si junction. The
GST film is not only used as a resistive switching layer but
also a part of the heterojunction diode. By the application of
rectification characteristics of heterojunction diodes, the
sneaking current is reduced by orders of magnitude in down-
ward direction, raising the signal-to-noise ratio for more re-
liable read operation, eventually reducing the static power
consumption. The sneaking current greatly decreases as the
forward-to-reverse current ratio increases.
Further, if the properties of the p-n heterojunction diode
based on GST, such as forward-to-reverse current ratio,
could be improved, perhaps it will applied as switch element
in the 1T1RD structure, which eventually makes the con-
ventional 1T1R structure simple as the 0T1R structure.
J. Appl. Phys. 105, 061627 2009
V. CONCLUSIONS
The p-GST/n-Si junction with diodelike characteristic is
successfully fabricated. p-GST/n-Si heterojunction diodes
have consistent rectification in either the crystalline state or
amorphous state for GST. The approximate equilibrium
energy-band diagrams both for crystal-GST/n-Si heterojunc-
tion diodes and amorphous-GST/n-Si heterojunction diodes
are proposed to explain the properties of the p-GST/n-Si
heterojunction diode. The forward-to-reverse current ratio of
the heterojunction diode at 2 V is about 104 and 103 for
crystalline and amorphous GSTs, respectively, which applies
it in the 0T1R cross-point architecture of PCRAM for more
reliable read operation and for further reduction of the sneak-
ing current.
ACKNOWLEDGMENTS
The authors would like to thank all of their collaborators.
This work is supported by the National Natural Science
Foundation of China with the Contract Nos. 60706033 and
60676007 and the National Basic Research Program of
China Grant No. 2007CB935403.
1
S. Lai and T. Laway, Tech. Dig. - Int. Electron Devices Meet. 2001,
36.5.1.
2
M. Gill, T. Lowrey, and J. Park, Dig. Tech. Pap.-IEEE Int. Solid-State
Circuits Conf. 1, 202 2002.
3
S.-H. Lee Y. Jung, and R. Agarwal, Nat. Nanotechnol. 2, 630 2007.
4
D.-H. Kang, D.-H. Ahn, K.-B. Kim, J. F. Webb, and K.-W. Yi, J. Appl.
Phys. 94, 3536 2003.
5
T. A. Lowrey, S. J. Hudgens, W. Czubatyj, C. H. Dennison, S. A. Ko-
stylev, and G. Wicker, in Characteristics of OUM Phase Change Materi-
als and Devices for High Density Nonvolatile Commodity and Embedded
Memory Applications, MRS Symposia Proceedings No. 803 Materials
Research Society, Pittsburgh, 2004.
6
A. Pirovano, A. L. Lacaita, A. Benvenuti, F. Pellizzer, and R. Bez., IEEE
Trans. Electron Devices 51, 308 2004.
7
R. E. Scheuerlein, Proceeding of the Seventh International Nonvolatile
Memory Technology Conference, 1998 unpublished, p. 47.
8
S. S. P. Parkin, K. P. Roche, M. G. Samant, P. M. Rice, R. B. Beyers, R.
E. Scheuerlein, E. J. OSullivan, S. L. Brown, J. Bucchigano, D. W. Abra-
ham, Y. Lu, M. Rooks, P. L. Trouilloud, R. A. Wanner, and W. J. Gal-
lagher, J. Appl. Phys. 85, 5828 1999.
9
Y. C.Chen, C. F. Chen, C. T. Chen et al., Tech. Dig. - Int. Electron Devices
Meet., 2003, 905.