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QUESTIONS
2) What is UART?
7) What is CISC?
communication_________.
24) Which ports are used for address & data interface
49) When the stack pointer reaches ffh it rolls over to___________.
64) What is the error due to extra instruction included in the s/w
timing loop.
once.
Answers
‘C’ language.
extension.
________,__________,
________.
76) 76) The Idata memory specifier always refers to all _______
105) How many bytes of on-chip program memory did 8051 consist
of?
106) How many bytes of on-chip data memory did 8051 consist of?
__________.
________,_______,_______
access efficient.
functions.
150) The task with the highest priority of all task in the ______ state
is executed.
operation
126 b) 256 c) 64
a) 5 b) 1 c) 3
timers
Answers
a) 1 b) 5 c) 2
a) 5 b) 2 c) 1
a) 5 b) 2 c) 3
A) 2 b) 3 c) 4
a) 5 b) 4 c) 2
A) 2 b) 3 c) 4
Answers
a) 3 b) 5 c) 4
a) 5 b) 4 c) 3
a) 6 b) 5 c) 4
a) 4 b) 6 c) 5
A) 3 c) 2 c) 4
169) How many instruction that affect the over flow flag
a) 4 b) 5 c) 7
170) What are the instructions that affect the overflow flag
A) 2 b) 3 c) 4
a) 2 b) 4 c) 3
a) 8 b) 7 c) 5
a) 64 b) 128 c) 256
a) 256 b) 128 c) 64
a) 2 b) 3 c) 4
A) CH b) CL c) CH&CL
Answers
a) 32 b) 16 c) 64
A) 2 b) 4 c) 8
a) 4 b) 5 c) 6
a) 2 b) 3 c) 4
a) 5 b) 6 c) 8
a) 12 b) 10 c) 14
a) 256 b) 64 c) 128
ANSWERS
1) a.Inbuilt ADC.
b.Has counter arrays.
c.Has timers.
d.Serial data transfer.
2) Universal Asynchronous Receiver Trnsmitter.
3)RAM- 128 + 64KB
ROM- 4KB + 60KB
4)BANK 0,BANK 1, BANK 2,BANK 3.
5)40 pin IC.
6)8 bits.
7)Complex Instruction Set Computers. It is the design of
control unit through software.
8)It has 2 registers. They are PC,DPTR.
9)07H.
10)Bank selection bits.
11)Mode 3.
12)Software.
13)Software and Hardware.
14)Non-maskable.
15)five.
16)Serial buffer register.
17)Modes 2 & 3.
18)Sleeping mode.
19)Hardware reset.
Back
20)Harvard architecture.
21)Port 1.
22)Four ports.
23)Port 0.
24)Port 0 and Port 2.
25)Timer control register.
26)Special function register.
27)80h-ffh.
28)Direct addressing.
29)Reduced instruction set computers.
30)16 bytes.
31)Bank 1.
32)timer.
33)213-1.
34)216-1.
35)Mode 0,1,2,3.
36)Serial control register.
37)PD-power down mode and IDL-ideal mode.
38)8.
39)oscillator fail detector.
40)It acts as watching dog. It resets the controller when
the timer overflows occurs.
41)R0,R1.
42). Copy data from A to the external address in dptr.
43)A.
44)64 bytes.
45)256 bytes.
Back
151. C
152. A
153. B
154. A
155. C
156. A
157. B
158. C
159. A
160. B
161. A
Back
162. C
163. B
164. A
165. B
166. C
167. A
168. C
169. B
170. A
171. C
172. A
173. B
174. C
175. A
176. C
177. B
178. A
179. A
180. A
181. A
182. C
183. A
184. A
185. B
186. A
187. C
188. B
Back
189. A
190. C
191. C
192. A
193. C
194. B
195. C
196. A
197. C
198. B
199. A
200. B