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JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV B .Tech. I Sem., I Mid-Term Examinations, September - 2017
DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES
Objective Exam
Name: ______________________________ Hall Ticket No. A
Answer All Questions. All Questions Carry Equal Marks. Time: 20 Min. Marks: 10.
5. Which of the following is the basic building block to carryout DSP computations? [ ]
a) Multiplier b) Shifter c) MAC unit d) All
6. The maximum number of bits in a product of two unsigned numbers A (m bits) and B(n bits) is
[ ]
a) m+n b) m-n c) mn d) All
Cont..2
Code No: 117CM :2: Set No. 1
11. The reconstruction filter removes high frequency noise due to the _______________ output of D/A
converter.
13. The range of signed integer values that can be represented with the fixed point format is
_______________.
14. The ratio of the maximum value to the minimum value that the signal can take in the given number
representation scheme is called __________________.
15. _______________ are required to scale down or scale up operands and results to avoid errors resulting
from overflows and underflows during computations.
17. In __________________ addressing mode a memory operand is specified by providing its memory
address.
18. Simultaneous operation of different stages of an instruction execution by spitting it into steps handled by
individually designed units is called ___________.
20. The bit size of arithmetic logic unit (ALU) in CPU of TMS320C54xx DSPs is ___________.
-oOo-
Code No: 117CM Set No. 2
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV B .Tech. I Sem., I Mid-Term Examinations, September - 2017
DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES
Objective Exam
Name: ______________________________ Hall Ticket No. A
Answer All Questions. All Questions Carry Equal Marks. Time: 20 Min. Marks: 10.
2. Which of the following is the basic building block to carryout DSP computations? [ ]
a) Multiplier b) Shifter c) MAC unit d) All
3. The maximum number of bits in a product of two unsigned numbers A (m bits) and B(n bits) is
[ ]
a) m+n b) m-n c) mn d) All
Cont..2
Code No: 117CM :2: Set No. 2
11. The ratio of the maximum value to the minimum value that the signal can take in the given number
representation scheme is called __________________.
12. _______________ are required to scale down or scale up operands and results to avoid errors resulting
from overflows and underflows during computations.
14. In __________________ addressing mode a memory operand is specified by providing its memory
address.
15. Simultaneous operation of different stages of an instruction execution by spitting it into steps handled by
individually designed units is called ___________.
17. The bit size of arithmetic logic unit (ALU) in CPU of TMS320C54xx DSPs is ___________.
18. The reconstruction filter removes high frequency noise due to the _______________ output of D/A
converter.
20. The range of signed integer values that can be represented with the fixed point format is
_______________.
-oOo-
Code No: 117CM Set No. 3
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV B .Tech. I Sem., I Mid-Term Examinations, September - 2017
DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES
Objective Exam
Name: ______________________________ Hall Ticket No. A
Answer All Questions. All Questions Carry Equal Marks. Time: 20 Min. Marks: 10.
1. The maximum number of bits in a product of two unsigned numbers A (m bits) and B(n bits) is
[ ]
a) m+n b) m-n c) mn d) All
10. Which of the following is the basic building block to carryout DSP computations? [ ]
a) Multiplier b) Shifter c) MAC unit d) All
Cont..2
Code No: 117CM :2: Set No. 3
12. In __________________ addressing mode a memory operand is specified by providing its memory
address.
13. Simultaneous operation of different stages of an instruction execution by spitting it into steps handled by
individually designed units is called ___________.
15. The bit size of arithmetic logic unit (ALU) in CPU of TMS320C54xx DSPs is ___________.
16. The reconstruction filter removes high frequency noise due to the _______________ output of D/A
converter.
18. The range of signed integer values that can be represented with the fixed point format is
_______________.
19. The ratio of the maximum value to the minimum value that the signal can take in the given number
representation scheme is called __________________.
20. _______________ are required to scale down or scale up operands and results to avoid errors resulting
from overflows and underflows during computations.
-oOo-
Code No: 117CM Set No. 4
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV B .Tech. I Sem., I Mid-Term Examinations, September - 2017
DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES
Objective Exam
Name: ______________________________ Hall Ticket No. A
Answer All Questions. All Questions Carry Equal Marks. Time: 20 Min. Marks: 10.
8. Which of the following is the basic building block to carryout DSP computations? [ ]
a) Multiplier b) Shifter c) MAC unit d) All
9. The maximum number of bits in a product of two unsigned numbers A (m bits) and B(n bits) is
[ ]
a) m+n b) m-n c) mn d) All
Cont..2
Code No: 117CM :2: Set No. 4
11. Simultaneous operation of different stages of an instruction execution by spitting it into steps handled by
individually designed units is called ___________.
13. The bit size of arithmetic logic unit (ALU) in CPU of TMS320C54xx DSPs is ___________.
14. The reconstruction filter removes high frequency noise due to the _______________ output of D/A
converter.
16. The range of signed integer values that can be represented with the fixed point format is
_______________.
17. The ratio of the maximum value to the minimum value that the signal can take in the given number
representation scheme is called __________________.
18. _______________ are required to scale down or scale up operands and results to avoid errors resulting
from overflows and underflows during computations.
20. In __________________ addressing mode a memory operand is specified by providing its memory
address.
-oOo-