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Code No: 117CM Set No.

1
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV B .Tech. I Sem., I Mid-Term Examinations, September - 2017
DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES
Objective Exam
Name: ______________________________ Hall Ticket No. A
Answer All Questions. All Questions Carry Equal Marks. Time: 20 Min. Marks: 10.

I. Choose the correct alternative:

1. A digital signal processing system uses _____________ to process signals . [ ]


a) Computer b) digital processor c) Both d) None

2. ________________ is used to convert an analog signal to digital. [ ]


a) A/D converter b) D/A converter c) Both d) None

3. In double precision fixed point format, the size is ______ . [ ]


a) Same b) Double c) Triple d) Quadruple

4. If an algorithm involves summation of a large number of products, it prefer __________ format


[ ]
a) Fixed point format b) double precision fixed point format
c) Floating point format d) None

5. Which of the following is the basic building block to carryout DSP computations? [ ]
a) Multiplier b) Shifter c) MAC unit d) All

6. The maximum number of bits in a product of two unsigned numbers A (m bits) and B(n bits) is
[ ]
a) m+n b) m-n c) mn d) All

7. The status flag includes [ ]


a) Sign b) Carry c) zero d) All

8. In __________________ addressing mode a processor register provides the operand [ ]


a) Immediate b) Register c) direct d) Indirect

9. The features in which programmable DSPs are superior to advanced microprocessors is


_______________. [ ]
a) Low cost b) Low power c) Computational speed d) Real time I/O capability

10. The number of data memory spaces in TMS320C54xx DSPs is [ ]


a) 2 b) 3 c) 4 d) 5

Cont..2
Code No: 117CM :2: Set No. 1

II Fill in the Blanks

11. The reconstruction filter removes high frequency noise due to the _______________ output of D/A
converter.

12. A continuous time, continuous amplitude signal is ______________ signal.

13. The range of signed integer values that can be represented with the fixed point format is
_______________.

14. The ratio of the maximum value to the minimum value that the signal can take in the given number
representation scheme is called __________________.

15. _______________ are required to scale down or scale up operands and results to avoid errors resulting
from overflows and underflows during computations.

16. On-chip memories help in running DSP algorithms ________________.

17. In __________________ addressing mode a memory operand is specified by providing its memory
address.

18. Simultaneous operation of different stages of an instruction execution by spitting it into steps handled by
individually designed units is called ___________.

19. The number of data operands in TMS320C54xx DSPs is ___________.

20. The bit size of arithmetic logic unit (ALU) in CPU of TMS320C54xx DSPs is ___________.

-oOo-
Code No: 117CM Set No. 2
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV B .Tech. I Sem., I Mid-Term Examinations, September - 2017
DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES
Objective Exam
Name: ______________________________ Hall Ticket No. A
Answer All Questions. All Questions Carry Equal Marks. Time: 20 Min. Marks: 10.

I. Choose the correct alternative:

1. If an algorithm involves summation of a large number of products, it prefer __________ format


[ ]
a) Fixed point format b) double precision fixed point format
c) Floating point format d) None

2. Which of the following is the basic building block to carryout DSP computations? [ ]
a) Multiplier b) Shifter c) MAC unit d) All

3. The maximum number of bits in a product of two unsigned numbers A (m bits) and B(n bits) is
[ ]
a) m+n b) m-n c) mn d) All

4. The status flag includes [ ]


a) Sign b) Carry c) zero d) All

5. In __________________ addressing mode a processor register provides the operand [ ]


a) Immediate b) Register c) direct d) Indirect

6. The features in which programmable DSPs are superior to advanced microprocessors is


_______________. [ ]
a) Low cost b) Low power c) Computational speed d) Real time I/O capability

7. The number of data memory spaces in TMS320C54xx DSPs is [ ]


a) 2 b) 3 c) 4 d) 5

8. A digital signal processing system uses _____________ to process signals . [ ]


a) Computer b) digital processor c) Both d) None

9. ________________ is used to convert an analog signal to digital. [ ]


a) A/D converter b) D/A converter c) Both d) None

10. In double precision fixed point format, the size is ______ . [ ]


a) Same b) Double c) Triple d) Quadruple

Cont..2
Code No: 117CM :2: Set No. 2

II Fill in the Blanks

11. The ratio of the maximum value to the minimum value that the signal can take in the given number
representation scheme is called __________________.

12. _______________ are required to scale down or scale up operands and results to avoid errors resulting
from overflows and underflows during computations.

13. On-chip memories help in running DSP algorithms ________________.

14. In __________________ addressing mode a memory operand is specified by providing its memory
address.

15. Simultaneous operation of different stages of an instruction execution by spitting it into steps handled by
individually designed units is called ___________.

16. The number of data operands in TMS320C54xx DSPs is ___________.

17. The bit size of arithmetic logic unit (ALU) in CPU of TMS320C54xx DSPs is ___________.

18. The reconstruction filter removes high frequency noise due to the _______________ output of D/A
converter.

19. A continuous time, continuous amplitude signal is ______________ signal.

20. The range of signed integer values that can be represented with the fixed point format is
_______________.

-oOo-
Code No: 117CM Set No. 3
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV B .Tech. I Sem., I Mid-Term Examinations, September - 2017
DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES
Objective Exam
Name: ______________________________ Hall Ticket No. A
Answer All Questions. All Questions Carry Equal Marks. Time: 20 Min. Marks: 10.

I. Choose the correct alternative:

1. The maximum number of bits in a product of two unsigned numbers A (m bits) and B(n bits) is
[ ]
a) m+n b) m-n c) mn d) All

2. The status flag includes [ ]


a) Sign b) Carry c) zero d) All

3. In __________________ addressing mode a processor register provides the operand [ ]


a) Immediate b) Register c) direct d) Indirect

4. The features in which programmable DSPs are superior to advanced microprocessors is


_______________. [ ]
a) Low cost b) Low power c) Computational speed d) Real time I/O capability

5. The number of data memory spaces in TMS320C54xx DSPs is [ ]


a) 2 b) 3 c) 4 d) 5

6. A digital signal processing system uses _____________ to process signals . [ ]


a) Computer b) digital processor c) Both d) None

7. ________________ is used to convert an analog signal to digital. [ ]


a) A/D converter b) D/A converter c) Both d) None

8. In double precision fixed point format, the size is ______ . [ ]


a) Same b) Double c) Triple d) Quadruple

9. If an algorithm involves summation of a large number of products, it prefer __________ format


[ ]
a) Fixed point format b) double precision fixed point format
c) Floating point format d) None

10. Which of the following is the basic building block to carryout DSP computations? [ ]
a) Multiplier b) Shifter c) MAC unit d) All

Cont..2
Code No: 117CM :2: Set No. 3

II Fill in the Blanks

11. On-chip memories help in running DSP algorithms ________________.

12. In __________________ addressing mode a memory operand is specified by providing its memory
address.

13. Simultaneous operation of different stages of an instruction execution by spitting it into steps handled by
individually designed units is called ___________.

14. The number of data operands in TMS320C54xx DSPs is ___________.

15. The bit size of arithmetic logic unit (ALU) in CPU of TMS320C54xx DSPs is ___________.

16. The reconstruction filter removes high frequency noise due to the _______________ output of D/A
converter.

17. A continuous time, continuous amplitude signal is ______________ signal.

18. The range of signed integer values that can be represented with the fixed point format is
_______________.

19. The ratio of the maximum value to the minimum value that the signal can take in the given number
representation scheme is called __________________.

20. _______________ are required to scale down or scale up operands and results to avoid errors resulting
from overflows and underflows during computations.

-oOo-
Code No: 117CM Set No. 4
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV B .Tech. I Sem., I Mid-Term Examinations, September - 2017
DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES
Objective Exam
Name: ______________________________ Hall Ticket No. A
Answer All Questions. All Questions Carry Equal Marks. Time: 20 Min. Marks: 10.

I. Choose the correct alternative:

1. In __________________ addressing mode a processor register provides the operand [ ]


a) Immediate b) Register c) direct d) Indirect

2. The features in which programmable DSPs are superior to advanced microprocessors is


_______________. [ ]
a) Low cost b) Low power c) Computational speed d) Real time I/O capability

3. The number of data memory spaces in TMS320C54xx DSPs is [ ]


a) 2 b) 3 c) 4 d) 5

4. A digital signal processing system uses _____________ to process signals . [ ]


a) Computer b) digital processor c) Both d) None

5. ________________ is used to convert an analog signal to digital. [ ]


a) A/D converter b) D/A converter c) Both d) None

6. In double precision fixed point format, the size is ______ . [ ]


a) Same b) Double c) Triple d) Quadruple

7. If an algorithm involves summation of a large number of products, it prefer __________ format


[ ]
a) Fixed point format b) double precision fixed point format
c) Floating point format d) None

8. Which of the following is the basic building block to carryout DSP computations? [ ]
a) Multiplier b) Shifter c) MAC unit d) All

9. The maximum number of bits in a product of two unsigned numbers A (m bits) and B(n bits) is
[ ]
a) m+n b) m-n c) mn d) All

10. The status flag includes [ ]


a) Sign b) Carry c) zero d) All

Cont..2
Code No: 117CM :2: Set No. 4

II Fill in the Blanks

11. Simultaneous operation of different stages of an instruction execution by spitting it into steps handled by
individually designed units is called ___________.

12. The number of data operands in TMS320C54xx DSPs is ___________.

13. The bit size of arithmetic logic unit (ALU) in CPU of TMS320C54xx DSPs is ___________.

14. The reconstruction filter removes high frequency noise due to the _______________ output of D/A
converter.

15. A continuous time, continuous amplitude signal is ______________ signal.

16. The range of signed integer values that can be represented with the fixed point format is
_______________.

17. The ratio of the maximum value to the minimum value that the signal can take in the given number
representation scheme is called __________________.

18. _______________ are required to scale down or scale up operands and results to avoid errors resulting
from overflows and underflows during computations.

19. On-chip memories help in running DSP algorithms ________________.

20. In __________________ addressing mode a memory operand is specified by providing its memory
address.

-oOo-

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