The 741 opAmp

DC and Small Signal Analysis

Ravi Kumar Jatoth
Lecturer, Dept of ECE
NIT, Warangal
Overview: Five Parts of the 741
 Input Stage
 Biasing Currents
 Second Stage
 Output Stage
 Short Circuit Protection
 Overview: 741 Schematic

Figure 1: Equivalent circuit, 741 op-amp.

The 741 consists of input differential amplifier stage, gain stage, output stage and separate bias circuit.
 The 741 op-amp circuit. Q11, Q12, and R5 generate a reference bias current, IREF, Q10, Q9, and
Q8 bias the input stage, which is composed of Q1 to Q7. The second gain stage is composed f
Q16 and Q17 with Q13 acting as active load. The class AB output stage is formed by Q14 and Q20
with biasing devices Q18 and Q19 and an input buffer Q23. Transistors Q15, Q21, Q24, and Q22
serve to protect the amplifier against output short circuit and are normally off.
Input Diff-Amp

To gain
stage
 Input transistors Q1 & Q2: emitter followers  high Rid
 Q3 & Q4: common-base amplifier  large voltage gain
 Output currents from Q1 & Q2 are input currents to Q3
& Q4.
 Q5, Q6 & Q7 with R1, R2 & R3: active load for diff-amp
 Output (single-sided) taken at collector of Q4 & Q6
 Dc output voltage at collector Q6 is at lower potential
than inputs at bases Q1 & Q2.
 Dc voltage level shifts several times as signal passes
through the opamp  zero dc output voltage for zero
differential input.
 Two null terminals: for appropriate adjustments to
achieve zero dc voltage design goal.
 From Figure 2, V1 = 15 V, V2 = 0 V.
 Fig 2(a): B-E of Q2 reverse biased by approx.
14.3V
  npn have breakdown voltage of 3 - 6 V so Q2
suffers permanent damage.
 Fig 2(b): B-E of Q1 & Q3 are forward biased
  series combination of B-E junction of Q2 &
Q4 reverse biased by 13.6 V.
 Breakdown voltage of lateral pnp is about 50 V
  B-E of Q4 provides breakdown
protection.
 Voltage breakdown protection
•Q3 & Q4: lateral pnp devices  larger breakdown voltage (smaller current gain )

Figure 2: (a) Basic common-emitter differential pair with a large differential voltage and (b) 741 input stage, with a large
differential voltage.
Biasing
 The two pairs of transistors shown in red. One
transistor in each pair has its collector connected to its
base, as well as to the base of the other transistor. In
addition, the transistor emitters are connected
together, in this case to the V+ power source. The
transistor with the collector and base shorted together
is rendered as a diode, which shows bias for the other
transistor.
 This arrangement is known as a current mirror. The
two transistors are manufactured side by side on the
same silicon die, at the same time. Thus, they have
essentially identical characteristics. The controlling
transistor (on the left in each pair) will necessarily set
its emitter-base voltage to exactly that value that will
sustain the collector current it is carrying, even down
to fractions of a millivolt. In so doing, it also sets the
emitter-base voltage of the second transistor to the
same value. Since the transistors are essentially
identical, the second transistor will carry exactly the
same current as the first, even to an independent
circuit.
 The use of a current mirror on the input circuit allows
the inputs to accommodate large common-mode
voltage swings without exceeding the active range of
any transistor in the circuit. The second current mirror
in red provides a constant-current active load for the
output circuitry, again without regard for the actual
output voltage.
 A third current mirror, shown in blue, is a bit different.
That 5K resistor in series with the emitter of the
mirrored transistor limits its collector current to
virtually nothing. Thus, it serves as a high-impedance
connection to the negative power supply, providing a
reference without loading the input circuit. This
particular circuit is therefore able to provide the slight
base bias current needed for the PNP transistors in the
differential input circuit, while allowing those
transistors to operate correctly over a wide common-
mode input voltage range.
 The final odd circuit within the op amp is shown in green.
Here, the two resistors bias the transistor in what would seem
to be an unusual way, since there is no apparent signal input to
the base of the transistor. To understand its purpose, assume
zero base current for a moment, and a VBE of 0.625 volt. Ohm's
Law then requires a current of 0.625 ÷ 7.5K = 0.0833mA
through the 7.5K resistor. The same current must also flow
through the 4.5K resistor, which will therefore exhibit a voltage
drop of 0.0833mA × 4.5K = 0.375V. The total voltage across the
two resistors, then, and therefore across the transistor, is
0.625V + 0.375V = 1.0V. This, then, is a simple voltage reference,
providing an internal 1-volt difference without a connection to
either power supply, nor to ground. This circuit floats
internally, and provides its 1-volt bias regardless of the actual dc
output voltage of the overall circuit.
 Biasing (Q8 to Q12)
 Q12, Q11 & R5: dc current biasing 
provides IREF
 Q11, Q10 & R4: Widlar current source
for biasing of common-base transistors
(Q3 & Q4) and current mirror formed by
Q8 & Q9.
Gain Stage
Q16 & Q17: second
gain stage
 Q16: emitter follower  large Rin

 Q13: two transistors in parallel
  Q13A: ¼ area of Q12
  Q13B: ¾ area of Q12
 Q13B: provides bias current for Q17, and also
acts as an active load to produce high voltage
gain
 Q17: common-emitter
 To output stage
 From input stage
  output voltage at collector of
Q17 is input to the output stage
signal undergoes another dc
 level shift

 Capacitor C1: internal feedback

compensation (Miller compensation)
for stability
  connected between output and
input terminals of the gain stage
Output Stage
• Q14 & Q20: class-AB circuit of complementary emitter-
follower
•  to provide low Rout
• and current gain (for driving large
• load currents)
• Output of gain stage connected to base of Q22  emitter
follower, high Rin.
• Q13A: bias currents for Q22, Q18 & Q19
• Q18 & Q19  provide quiescent bias current in output
transistors Q14 & Q20.
• From gain stage
• Q15 & Q21: short-circuit protection  normally off.
• Q15 & Q21 conduct only when output is inadvertently
connected to ground and resulting in a very large output
current.
 DC Analysis
 To determine dc bias currents.
 Assumptions:
 non-inverting and inverting input terminals at
ground potential.
 dc supply voltages are +15 V and -15 V.
 VBE for npn = VEB for pnp = 0.6 V.
 In most cases dc base currents are
neglected.
 Bias Circuit and Input Stage

Figure 3: Bias circuit and input stage portion of 741 op-amp circuit.
DC Current flow in input stage

The dc analysis of the 741 input stage.

Another Example
Fig. 10.6 Small-signal analysis of the 741 input stage
 Conclusions
 The 741 is a versatile opAmp that can be
used in a multitude of different ways

 When you break it down into the different

components, it’s operation is actually
understandable and comprehendible