World Applied Sciences Journal 32 (11): 2297-2302, 2014

ISSN 1818-4952
IDOSI Publications, 2014
DOI: 10.5829/idosi.wasj.2014.32.11.1341

Test Data Compression Using a New Scheme Based on Extended Variable Length Codes
1
J. Robert Theivadas and 2V. Ranganathan

1
Reserach Scholar, Anna University, Chennai 600025, India
2
Sree Sastha Institute of Engineering and Technology, Chennai 600123, India

Abstract: The need of testing large amount of data in large ICs has increased the time and memory requirement
by many folds. Several test data compression schemes have been proposed for reducing the test data volume.
In this paper, we propose a novel, lossless, time and memory minimizing test data compression scheme based
on the fixed to variable length coding with limited number of code words. In our scheme, we divide the test
vectors into fixed length blocks and then compress them into variable length codes. We use this extended
variable length codes algorithm to make changes in the test vectors and to increase the compression ratio. The
generation of good compression ratio through our scheme is proved by the experimental results for the ISCAS-
89 benchmark circuits and the compressed test data. In comparison to the previous test data techniques based
on variable length codes, the outcome of our method has a reasonable effect on compression.

Key words: Test data compression Variable length codes Compression ratio

INTRODUCTION
According to Moores law, the integration level of
the microchips doubles every 18 to 24 months. As a
result, the volume of test data increases dramatically; the
test costs become higher; the contradiction between test
efficiency and test quality sharpens. The effective method
to reduce test data volume is test data compression [1].
There are three type of test data compressions viz.,
the Linear de-compression based schemes [4, 5], where
the de-compression of data is done using linear
operations; the Broadcast scan based schemes [6, 7],
where broadcast scan based scheme broadcasts the
same values in multiple scan chain; and the Code based
schemes [2, 3], where the code based schemes use data
compression codes to encode the test cubes.
Code-based scheme is widely used [8] in test data
compression as it transfers the specified bit-strings in test
data into a segment of code word. A certain encoding
scheme is used to encode the original test set. The length
of the encoded data is less than the original test set so
that the test data can be reduced.
The test set is divided into sequences of specific
law, which can be replaced with new code word generated
by some kinds of coding method. According to the
change rule of the length from the original sequence to
the code word, Code based test data compression can be
classified into four categories. First category is fixed to
fixed, these codes encode fixed size blocks of data using
smaller fixed size blocks of encoded data. The [14]
dictionary code is used for the fixed to fixed coding
scheme. Here the data transfer rate from the tester to
decoder is constant.
Second one is Fixed-to-Variable Codes; these codes
encode fixed size blocks of data using a variable number
of bits in the encoded data. The Huffman code [9-13] is
typically used for the fixed-to-variable coding scheme.
Huffman code is used in many compression techniques,
as it is one of the efficient codes for encoding the test
data. Selective Huffman codeword [15] adds symbols to
the Huffman tree (i.e.) addition of symbols with higher
frequency. One of the advantage of using selective
Huffman coding is, it is used to reduce the hardware
overhead of Huffman FSM. And this method gives good
result, but the hardware cost is high.
Third one is Variable-to-Fixed Codes; these codes
encode a variable number of bits using fixed size blocks
of encoded data. The run length code [16] is used for
variable-to-fixed coding scheme. The Almost
Instantaneous VF (AIVF) coding [18] is used to get good
compression ratio. The Suffix Tree-based VF (STVF)
coding [19] is used to get better compression ratio.

Corresponding Author: J. Robert Theivadas, Reserach Scholar, Anna University, Chennai 600025, India.
E-mail: roberttheivadas@gmail.com - drvrangan@gmail.com.
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 World Appl. Sci. J., 32 (11): 2297-2302, 2014
Fourth one is Variable-to-Variable codes; these
codes encode a variable number of bits using a variable
number of bits in the encoded data. The Golomb code [17]
is used for variable-to-variable coding scheme. This
Golomb code achieves greater compression ratio and the
overhead is small. In variable-to-variable code word one
of the difficulties is synchronizing the transfer of data
from the tester. The other variable-to-variable coding
schemes are alternation and run length code [21], FDR
code [20] and EFDR code [22].
In this paper, one of the new techniques is used to
compress the original test vectors. Here the original test
vectors are divided into fixed length blocks, which are
then compressed into variable code words. The technique
used in this paper is called the Extended Variable Run
Length Coding. Using this compression technique greater
compression will be achieved and decompression will be
performed. In decompression, the variable length code
words are decompressed in to fixed length code words
using FSM.
The organization of the paper is as follows - Section
2 explains the algorithm, flowchart and an example of the
proposed scheme; Section 3 explains the structure of the
de-compressor; Section 4 explains the experimental results
and analyzes of the compression ratio theoretically; and
Section 5 concludes the paper.
Encoding Rule: In this paper, the new test vector
compression scheme is used, so that the number of test
vectors will be reduced. The encoding rule consists of
various steps, which are explained below:
Step 1: The input given is the original test vectors.
Step 2: Divide the original test vectors into four bits.
Step 3: If all the bits in the original test vectors are
divided into four bits then the compression is
achieved using the compression rules.
Step 4: The compression rules are given below:
Rule 1: If the original test vector is 0000, then the
compressed test vector is 1.
Rule 2: If the original test vector is 0001, then the
compressed test vector is 01.
Rule 3: If the original test vector is 0010, then the
compressed test vector is 10.
Rule 4: If the original test vector is 0011, then the
compressed test vector is 11.
Rule 5: If the original test vector is 0100, then the
compressed test vector is 00.
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Rule 6: If the original test vector is 0101, then the
compressed test vector is 001.
Rule 7: If the original test vector is 0110, then the
compressed test vector is 010.
Rule 8: If the original test vector is 0111, then the
compressed test vector is 011.
Rule 9: If the original test vector is 1000, then the
compressed test vector is 100.
Rule 10: If the original test vector is 1001, then the
compressed test vector is x1.
Rule 11: If the original test vector is 1010, then the
compressed test vector is x0.
Rule 12: If the original test vector is 1011, then the
compressed test vector is 111.
Rule 13: If the original test vector is 1100, then the
compressed test vector is 000.
Rule 14: If the original test vector is 1101, then the
compressed test vector is x01.
Rule 15: If the original test vector is 1110, then the
compressed test vector is x10.
Rule 16: If the original test vector is 1111, then the
compressed test vector is 0.
Step 5: Then the process is repeated and all the bits in
the test vector is compressed.
Step 6: If all the bits are compressed, the process stops
otherwise it repeats from step 3
Here it uses fixed to variable length coding with
limited number of code words. This is one of the novel
test data compression scheme. The following example
shows how the algorithm works. Take C432 circuit, the
test vectors in C432 are divided into four bits. Some of the
test vectors from C432 are taken and explained below.
110101010101010101010101010101000111
100010001001011101110111011101110100.
The above test vectors are the original test vectors
which are divided into four bits. The 1101 is compressed
into x01, 0101 is compressed into 001, 0100 is compressed
into 00, 0111 is compressed into 011, 1000 is compressed
into 100, 1001 is compressed into x1.
X01 001 001 001 001 001 001 00 011
100 100 x1 011 011 011 011 011 00
Here the 72 bits are compressed into 51 bits.
 World Appl. Sci. J., 32 (11): 2297-2302, 2014
Table 1: Extended variable run length coding method
Run Length Test Data
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001
10 1010
11 1011
12 1100
13 1101
14 1110
15 1111
Fig. 1: Flow diagram of the compression technique.
Table 1 shows that fixed to extended variable run
length code
The above tabular column shows that the fixed length
code word and the variable length code words. These
code words are used to compress the original test vectors
in various benchmark circuits.
Codeword
1
01
10 Fig. 2: Structure of the de-compressor.
11
00
001
010
011
100
X1
X0
111
000
X01
X10
0
Fig. 3: Working diagram of Decompression FSM
Then the flow chart of the compression technique is
shown Figure 1.
Structure of Decompressor: After the compression
process, the test vectors must be de-compressed. Here
one of the new techniques is used to de-compress the test
vectors. And that technique consists of input which is the
compressed test vectors and it is given to the FSM. The
output obtained from the FSM is the original test vectors.
The block diagram and the working diagram of FSM
is shown Figure 2.
The working diagram of the FSM is shown Figure 3.
The working diagram of FSM is explained. Here 0 and
1 is considered when the given input 0 remains as such,
the output is 1111 and the given input 1 remains as 1, then
the decompressed value is 0000. Then the 0 to 1 transition
takes place, the 01 is decompressed to 0001 and when the
1 to 0 transition occurs, the 10 is decompressed to 0010.
When the 0 becomes 1, the value becomes 11 and when
the 1 becomes 0 the value becomes 00. If 11 is in 0 state
then the decompressed output of 11 becomes 0011. And
if 00 is in 1 state then the decompressed output of 00
becomes 0100. Then it makes the transition from 11 to 00,
the 010 is decompressed in to 0110. And it makes the
transition from 00 to 11; the 001 is decompressed in to
0101.
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When 11 changes to 1 state, the value becomes 011
and when the 00 changes to 0 state, the value becomes
100. If 011 is in 0 state then the decompressed output of
011 becomes 0111. And if 100 is in 1 state, then the
decompressed output of 100 becomes 1000. Then it makes
the transition from 011 to 100, the x0 is decompressed into
1010. And it makes the transition from 100 to 011; the x1 is
decompressed into 1001.
When 011 changes to 1 state, the value becomes 111
and when the 100 changes to 0 state, the value becomes
000. If 111 is in 0 state then the decompressed output of
111 becomes 1011. And if 000 is in 1 state, then the
decompressed output of 000 becomes 1100. Then it makes
the transition from 111 to 000, the x10 is decompressed
into 1110. And it makes the transition from 000 to 111; the
x01 is decompressed into 1101. So by this technique
greater compression and decompression has been
achieved.
run length coding technique. From Table 2, it is found that
the decrease of number of runs ranges 75% for different
test sets.
Then the extended run length coding scheme is used
to compress these new test vectors. The compression
ratio of the proposed scheme in comparison to the other
coding schemes is shown in Table 3. In these experiments,
runs of 0s and 1s are used. The first column of Table 3 is
the circuit name. The second column is the test size of
original test data. The compression effect of EVRL is
shown in the third column of Table 3. The compression
result of extended variable run length coding is also given
for comparison in Table 3. The other columns are sizes of
compressed test data and compression ratio of BM [2],
Golomb code [17], VIHC [15], EFDR [22], RL Huffman
coding [9] and FDR [23]. The Compression Ratio (CR) is
the ratio of the number of bits per sample before
compression to the encoded data rate.

RESULTS AND DISCUSSION
Here, the effectiveness of the proposed scheme is
verified by using experiment results. For comparison with
other schemes, the MinTest test sets provided by Duke
University of America are adopted, which are same as the
test vectors used in paper [23]. Experiments were
performed on the largest ISCAS 89 benchmark circuits
[24]. Table 2 shows the analysis of the number of runs on
the used test sets. The 1st column shows the circuit
name; the 2nd, the number of runs before the extended
variable run length code is applied; and the last, the
number of runs obtained after the extended variable run
length code is applied. It is found that the number of runs
is decreased reasonably by using this extended variable
TD -Tg
Compression Ratio= 100
TD
Where
TD is original length of test data and
TE is the length of compressed data [23].
From table 3, it is found that the new scheme has
effectively generated very good compression ratios when
compared to many run length coding schemes. The
average compression ratio (60.7583) achieved through our
technique is quite higher than that other compression
schemes
The above graphical representation clearly shows
that our new scheme generates high compression
ratio in comparison with other standard compression
algorithms.

Table 2: Analysis of the number of runs in test sets

Name of the circuit Runs before EVRL Runs after EVRL
s5378 20758 15570
S9234 25935 19452
S13207 163100 122325
S15850 57434 43077
S38417 59532 84864
S38584 161040 120780

Table 3: Comparison of compressed MINTEST test vector obtained by using different coding technique
Circuits Size of original test vector TD FDR Golomb Code VIHC EFDR RL Huffman Proposed Scheme
s5378 20578 20.54 15.72 25.29 34.74 36.56 59.9
S9234 25935 24.56 11.06 28.29 44.40 46.58 58.8
S13207 163100 42.57 37.35 56.16 60.37 66.59 59.37
S15850 57434 45.11 42.83 52.35 53.82 54.64 58.84
S38417 113152 58.8 59.14 60.92 62 63.33 68.34
S38584 161040 46.47 41.85 46.76 47.13 52.27 59.3
Average 39.675 34.6583 44.9617 50.41 53.3283 60.7583

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Fig 4: Comparison chart for different compression
schemes
CONCLUSION
Test data compression is an effective solution to
reduce the increasing test data in larger ICs. A new test
data compression scheme based on extended variable run
length code is proposed here. In this technique, the
original test vectors are divided into fixed length blocks;
and then, the fixed length blocks are compressed into
variable code words. This decreases the number of runs
and thereby enabling a better compression effect. It is
shows that this technique has the characteristic of high
compression ratio, which decreases the ATE memory, the
channel capacity requirements and the low hardware
overhead. Thus, it is an effective solution to test data
compression/decompression for IC design.
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