----------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 22:22:38 07/07/2017

-- Design Name:

-- Module Name: vending - Behavioral

-- Project Name:

-- Target Devices:

-- Tool versions:

-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;
entity vending is

Port ( clk : in STD_LOGIC;

sel1 : in STD_LOGIC;

sel2 : in STD_LOGIC;

sel3 : in STD_LOGIC;

sel4 : in STD_LOGIC;

R10 : in STD_LOGIC;

R20 : in STD_LOGIC;

cancel : in STD_LOGIC;

reset : in STD_LOGIC;

salida : out STD_LOGIC_VECTOR (2 downto 0));

end vending;

architecture Behavioral of vending is

type estados is (inicio, espera, snack, coffee, cold, candy, service, change);

signal ep: estados;

signal clk_1Hz_s: std_logic;

signal t,mo: integer range 0 to 5000;

signal s1,s2,s3,s4: integer range 0 to 5000:=10;

begin

process(clk,reset)

variable T: integer range 0 to 50000000;

begin

if reset='1' then

clk_1Hz_s <= '1';

elsif(rising_edge (clk)) then

T:=T+1;

if ( T<=1) then

clk_1Hz_s <= '1';

elsif( T<3) then

 clk_1Hz_s <= '0';

else

T:=0;

end if;

end if;

end process;

process(clk_1Hz_s,reset,R10,R20,ep,sel1,sel2,sel3,sel4,s1,s2,s3,s4)

begin

if ep=inicio then

mo<=0;

if((sel1='1' and s1>0) or (sel2='1' and

s2>0) or (sel3='1' and s3>0) or (sel4='1' and s4>0)) then

ep <= espera; t<=0;

elsif(sel1='1' or sel2='1' or sel3='1' or

sel4='1') then

ep <= service; t<=0;

else

ep<=inicio;

end if;

elsif(reset= '1') then

ep <= inicio;

elsif (rising_edge (clk_1Hz_s)) then

case ep is

when espera =>

t<=t+1;

if(R10='1' ) then
 mo<=mo+10;

end if;

if(R20='1' ) then

mo<=mo+20;

end if;

if(sel1='1' and mo>=30) then

ep<=snack;mo<=mo-30;s1<=s1-1;t<=0;

elsif(sel2='1' and mo>=40) then

ep<=coffee;mo<=mo-40;s2<=s2-1;t<=0;

elsif(sel3='1' and mo>=40) then

ep<=cold;mo<=mo-40;s3<=s3-1;t<=0;

elsif(sel4='1' and mo>=30) then

ep<=candy;mo<=mo-30;s4<=s4-1;t<=0;

elsif(cancel='1' or t=6) then

ep<=change;t<=0;

else

ep<=espera;

end if;

when snack =>

t<=t+1;

if(t=4) then

ep<=change;t<=0;

else

ep<=snack;

end if;

when coffee =>

t<=t+1;

if(t=4) then

ep<=change;t<=0;

else
 ep<=coffee;

end if;

when cold =>

t<=t+1;

if(t=4) then

ep<=change;t<=0;

else

ep<=cold;

end if;

when candy =>

t<=t+1;

if(t=4) then

ep<=change;t<=0;

else

ep<=candy;

end if;

when change =>

t<=t+1;

if(t=4) then

mo<=0;ep<=inicio;t<=0;

else

ep<=change;

end if;

when service =>

t<=t+1;

if(t=24) then

ep<=inicio;t<=0;s1<=10;s2<=10;s3<=10;s4<=10;
 else

ep<=service;

end if;

when others =>

ep<=inicio;

end case;

end if;

end process;

process(ep)

begin

case ep is

when inicio => salida <="000";

when espera => salida <="001";

when snack => salida <="010";

when coffee => salida <="011";

when cold => salida <="100";

when candy => salida <="101";

when change => salida <="110";

when service => salida <="111";

end case;

end process;

end Behavioral;
--------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 23:11:55 07/07/2017

-- Design Name:

-- Module Name: C:/Users/julio/Desktop/LAVADORA/exam/simu.vhd

-- Project Name: exam

-- Target Device:

-- Tool versions:

-- Description:

--

-- VHDL Test Bench Created by ISE for module: vending

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

-- Notes:

-- This testbench has been automatically generated using types std_logic and

-- std_logic_vector for the ports of the unit under test. Xilinx recommends

-- that these types always be used for the top-level I/O of a design in order

-- to guarantee that the testbench will bind correctly to the post-implementation

-- simulation model.

--------------------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;

ENTITY simu IS

END simu;

ARCHITECTURE behavior OF simu IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT vending

PORT(

clk : IN std_logic;

sel1 : IN std_logic;

sel2 : IN std_logic;

sel3 : IN std_logic;

sel4 : IN std_logic;

R10 : IN std_logic;

R20 : IN std_logic;

cancel : IN std_logic;

reset : IN std_logic;

salida : OUT std_logic_vector(2 downto 0)

);

END COMPONENT;

--Inputs

signal clk : std_logic := '0';

signal sel1 : std_logic := '0';

signal sel2 : std_logic := '0';

signal sel3 : std_logic := '0';

 signal sel4 : std_logic := '0';

signal R10 : std_logic := '0';

signal R20 : std_logic := '0';

signal cancel : std_logic := '0';

signal reset : std_logic := '0';

--Outputs

signal salida : std_logic_vector(2 downto 0);

-- Clock period definitions

constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: vending PORT MAP (

clk => clk,

sel1 => sel1,

sel2 => sel2,

sel3 => sel3,

sel4 => sel4,

R10 => R10,

R20 => R20,

cancel => cancel,

reset => reset,

salida => salida

);

-- Clock process definitions

clk_process :process

begin
 clk <= '1';

wait for clk_period/2;

clk <= '0';

wait for clk_period/2;

end process;

sel4_process :process

begin

sel4 <= '0';

wait for clk_period*36;

sel4 <= '1';

wait for clk_period*36;

end process;

sel3 <= '0';

sel2 <= '0';

sel1 <= '0';

cancel <= '0';

R10 <= '1';

R20 <= '1';

reset <= '0';

-- Stimulus process

stim_proc: process

begin

-- hold reset state for 100 ns.

wait for 100 ns;

wait for clk_period*10;

-- insert stimulus here

 wait;

end process;

END;