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COMPARATOR
Lecture Notes
( Dr. P. Subbanna Bhat)
Definition:
Compares the instantaneous values of two analog signals [ () and  ()] and
provides logical output to indicate their relative magnitudes (Logic 1 for    ;
Logic 0 for    ). Thus the comparator responds to analog inputs and provides a
digital output .

 

 

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Fig. 1 : Basic Comparator

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Schematic Representation:
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Schematically, the input stage is a high gain differential amplifier (amplifies the
difference between the inputs, but rejects the common mode component), followed by a
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decision making unit (latch), which ensures a sharp transition from one logic state to
another. The high gain of the analog amplifier stage may be achieved using one or more
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stages. The latch is usually followed by a buffer stage to handle large capacitive loads.
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High gain Buffer


Differential Stage
Latch
Amplifier

 

Fig. 2: Schematic of comparator

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Comparator Characteristics
The desired (ideal) and realistic (actual) input output characteristic of a comparator are
shown in Fig 3.

It is desirable that the output (of ideal Comparator) makes a sharp transition from Logic
0 to Logic 1, or vice versa, whenever the two input instantaneous values cross each
other. This implies infinite gain analog differential amplifier. However, typically a latch
is used as the decision making unit, which can achieve a sharp transition. The rise and
fall time is decided by the decision making stage.

The decision making stage a latch changes its state when the trigger input exceeds the
switching potential. This gives rise to input offset of the comparator. In addition, the

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PVT (VLSI manufacturing Process, supply Voltage and Temperature) variations, can
give rise to an unpredictable amount of offset voltage at the input of the differential
amplifier. The offset affects the accuracy of comparator decision. In order to reduce the

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effect of offset, the input signals are amplified considerably before feeding to the decision
making circuit. Usually, the differential signal after rejecting the common mode
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component ( 
   ) is amplified and fed to the Latch.

   
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Fig. 3: Comparator transfer characteristic


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The comparator is expected to respond only to the differential between the two inputs and
ignore the common mode component. In this sense it is similar to the Operational
Amplifier. However, there is vital difference between the OPAMP and comparator. The
OPAMP is always used as a linear mode circuit; that is, it is always operated with
sufficiently large negative feedback, to ensure linear mode operation. Whereas the
comparator is always used in open loop condition. This difference makes the design
strategy for the comparator quite different from that of the OPAMP.

The two stage OPAMP design has to take into account the stability issues under the
feedback conditions, and use compensation techniques as an essential part of the
amplifier design. Generally, the compensation techniques adopted, curtails the bandwidth
of the OPAMP. The comparator design is free from this constraint, and therefore can aim
and achieve much higher bandwidth for the input (amplifier ) stage .

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In order to achieve the desired high gain, both the OPAMP/Comparator use multiple
amplifier stages. While the closed loop stability of the OPAMP places a restriction on the
number of stages in an OPAMP (typically, the OPAMP uses not more than two stages);
while the comparator design is not encumbered by this constraint, can employ more
stages each of lower gain but higher and width - to achieve the targeted gain and
bandwidth.

The following discussion assumes the conceptual understanding of the following topics
1. MOSFET characteristics
2. Diode connected MOSFET
3. Current Mirror (Current repeater, Current amplifier,
4. MOSFET inverter
5. CMOS Inverter
6. Latch (Bistable multi )

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7. Differential amplifier
8. Operational transconductance amplifier (OTA)

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Comparator Circuit Architecture
The input stage differential transcoductance amplifier is shown in Fig. 4. The gain of this
stage is rather low (because of the diode connected PMOS load M3-M4)); the low node
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impedance ensures high speed (high bandwidth) operation. The fully differential output
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ensures rejection of the common mode component of the input signal. The current
mirrors (M6-M7) acting on the fully differential output of the first stage, can be used to
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impart a current gain ( by choosing a suitable W/L ratio). The diode connected NMOS
pair M8-M9, acts as low impedance load for this stage. The other NMOS pair (M10-
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M11) with cross connected gates act as normal logic inverters forming a latch the
decision circuit.
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The inverters pair forming the latch need to have a voltage gain larger than unity.
Considering the fact that the diode connected MOS ( M8-M9 ) act as the load on these
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inverters, the sizing of M10-M11 should be such as to ensure the inverter gain to be
larger than unity.

The output of the latch may require shaping, to be compatible with logic circuits. This is
usually done with the help of an amplifier. In the present case a single ended differential
amplifier is used for this purpose. However, since the input excursion to this differential
amplifier is limited, the latch output may require a level shifter to meet this requirement.
The diode connected MOS M12 acts as a level shifter DC bias. Note that the net current
flowing through M12 is a constant (independent of signal conditions).

In the event the comparator needs to drive a heavy load, the single ended differential
amplifier output may be fed to a buffer stage (cascaded pair of inverters).

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Fig. 4: Fully differential amplifier and Latch
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Fig. 5: Comparator circuit


Ref: Jacob Baker, CMOS Circuit Design, Layout, and Simulation ,Wiley India Edition,
Second Edition, 2005
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