Demonstration of electrical connectivity between self-assembled structures

Madhav Rao, John C. Lusth, and Susan L. Burkett

Citation: Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials,
Processing, Measurement, and Phenomena 31, 032002 (2013); doi: 10.1116/1.4802914
View online: http://dx.doi.org/10.1116/1.4802914
View Table of Contents: http://avs.scitation.org/toc/jvb/31/3
Published by the American Vacuum Society
Demonstration of electrical connectivity between self-assembled structures
Madhav Raoa)
International Institute of Information Technology, Bangalore, Karnataka 560100, India
John C. Lusth
Department of Computer Science, The University of Alabama, Tuscaloosa, Alabama 35487
Susan L. Burkett
Department of Electrical and Computer Engineering, The University of Alabama, Tuscaloosa, Alabama 35487
(Received 16 December 2012; accepted 10 April 2013; published 1 May 2013)
A novel way of three dimensional (3D) chip stacking has been designed in a view to improve heat
dissipation across the layers. Solder-based self assembled (SBSA) structures have been designed as
3D posts on simulated through silicon vias to demonstrate the concept. The fabrication of SBSA
structures using a low temperature solder alloy and dip soldering method is described. Previously,
two types of solderingface soldering and edge solderingwere studied to fabricate SBSA
structures. Face soldering refers to deposition of solder on the complete metal face whereas edge
soldering refers to selective deposition of solder on only the edges of the metal face. Mechanical
grinding of the 3D structures shows that face soldered SBSA structures were void free and robust
enough to be used as a connection post for chip stacking. Edge soldered SBSA structures collapsed
when grinding was performed. This suggests the edge soldered 3D structure may only be partially
filled. Face soldered SBSA structures provide a solder bump that serves as a connection path in the
integration of dissimilar electronic technologies. Cylindrical copper posts, developed in a previous
project, can be an effective approach to integrated circuit stacking. However, the SBSA post provides
more variety in size and shape and can serve as a reservoir for solder to aid in chip bonding. The
solder bumps are heat resistant, and uniform thicknesses were obtained across a large array of SBSA
structures. The electrical durability of SBSA posts were determined by completing I-V measurements
after thermal treatment. SBSA posts were subjected to thermal cycling with temperatures ranging
from room temperature to 300  C. The interconnected SBSA posts are shown to be stable until
165  C with little variation in measured resistance. V
C 2013 American Vacuum Society.

[http://dx.doi.org/10.1116/1.4802914]

I. INTRODUCTION coolant is formed. Rather than forming copper posts by a

Three dimensional (3D) integration offers several advan-
tages over conventional VLSI, including reduced signal
delay and power, as well as increased design flexibility. 3D
integration is viewed as a system-level architecture where
multiple layers of planar devices are stacked and intercon-
nected using through silicon vias (TSVs) in the z-direction.
TSVs eliminate the need to route planar interconnects to the
periphery of the chips and back again.1 3D integration allows
for combining dissimilar components, such as RF receivers,
graphic units, and memory logic, in different planes. This
technology has allowed the semiconductor industry to stack
many devices vertically with less concern about the place-
ment and space for wiring. However, existing 3D integration
methods present processing complexities as well as thermal
management issues. This paper proposes a novel approach to
form active supports between the layers in a 3D stack.
Various stacking methods for forming connections
between layers in a 3D stack have been proposed.2,3 One con-
cern in developing 3D stacking systems is thermal manage-
ment. One approach to providing heat dissipation involves
copper posts as supports and spacers between levels in a 3D
stack.4 Coupled with copper retaining walls, a channel for
a)
Electronic mail: mr@iiitb.ac.in
lengthy electroplating step, self assembly can be used to build
copper support structures. Researchers have successfully
used self assembly for a variety of applications511 involving
different materials6,1214 and at different scales1521 to form
3D structures. Self-folded structures have been formed with
the use of a large number of hinges in a manner similar to ori-
gami folding.22 These complex structures even exhibit bidir-
ectional curvature. Leong et al. provide an excellent review
describing fabrication of 3D structures using various self-
folding methods. Notable characteristics of each method are
discussed as well the resolution of the resulting structures.23
Using solder as a hinge in assembling microscale structures
was first demonstrated by Green et al.24 Solder based self as-
sembly (SBSA), refined by Harsh and Lee,20,25 is a simple
way to fabricate 3D structures. As demonstrated in Fig. 1, we
proposed the use of copper filled TSVs connecting SBSA
posts to the device side of a substrate.
SBSA can be used to construct arrays of 3D structures,
the base of which can be anchored to a silicon substrate.
This method combines conventional patterning with a simple
immersion step to deposit solder on 2D patterns. The pat-
terns are designed so that the base is surrounded by disjoint
metal faces deposited on top of a sacrificial layer. After sol-
der deposition, which joins the faces to the base, removal
of the sacrificial layer frees the faces with respect to the

032002-1 J. Vac. Sci. Technol. B 31(3), May/Jun 2013 2166-2746/2013/31(3)/032002/11/$30.00 C 2013 American Vacuum Society
V 032002-1
032002-2 Rao, Lusth, and Burkett: Demonstration of electrical connectivity between self-assembled structures
FIG. 1. (Color online) Schematic representation of SBSA structures and TSVs for 3D integration.
substrate; the faces remain attached to the base. Remelting
the solder, commonly referred to as reflow, allows the freely
hinged metal patterns to rotate and form a 3D structure.
To explore the feasibility of using SBSA structures as
active supports for 3D integration, a buried conduction chan-
nel between structures was constructed. The channel con-
nects two 3D structures, as shown in Fig. 2, to simulate a
structure on one layer vertically connected to another by
way of a TSV. The proposed architecture is intended to dem-
onstrate the electrical continuity between two SBSA struc-
tures. TSV fabrication and reliability have been investigated
in our laboratory.26,27 However, due to the time intensive na-
ture of TSV processing, a conducting channel connecting
two SBSA structures was developed by our group as a way
to test the proposed architecture. Adding a conducting chan-
nel requires an additional dielectric layer. This paper dis-
cusses the formation of 3D structures developed on
conducting channels using two sacrificial layers, MgO and
SiO2. We focus on two polyhedra serving as posts, a trun-
cated pyramid (which has a triangular base) and a truncated
square pyramid (whose base has four sides).
The electrical reliability of the structures was investigated
by thermal cycling. Thermal cycling can accelerate fatigue
failures, depending on temperature range, transfer time
between the temperatures, and the dwell times at an extreme
temperature.27 Currentvoltage (I-V) measurements for
SBSA structures exposed to thermal cycling were used to
assess the proposed architecture.
II. BACKGROUND
Advances in integrated circuit (IC) processing techniques
have led to high density 2D electronics. Today, in addition to
improvements in the 2D realm, a third dimension is being
investigated to increase density and performance. However, a
FIG. 2. (Color online) Schematic representation of two SBSA structures connected by way of a conducting channel.
J. Vac. Sci. Technol. B, Vol. 31, No. 3, May/Jun 2013
032002-2
fundamental issue that needs to be addressed is the RC delay
caused by lengthy on-chip wiring. 3D integration is believed
to be one answer to the wiring problem. Various approaches
include the following: die-to-die stacking, die-on-wafer
stacking, wafer-on-wafer stacking, package-on-package, and
combinations of techniques to increase device density. In
addition, 3D integration allows interconnection of multiple
hybrid layers.28 The hybrid layers, including compound semi-
conductor optoelectronic devices, can be integrated with sili-
con CMOS electronics or even organic devices. This
approach allows dissimilar materials containing circuitry that
has been optimized for a particular substrate. Electronic devi-
ces can then be stacked to achieve improved functionality in
a small space. Heterogeneous integration relies heavily on
metal filled TSVs for vertical connections.2931
The hybrid layers can be stacked using solder bump tech-
nology. High power density ICs in stacked layers can gener-
ate large amounts of heat within the stack.32,33 For these
reasons, thermal management schemes are being investi-
gated by various researchers. Microchannel liquid cooling is
one promising heat removal solution.32,34,35 The coolant
flow between stacked layers allows heat dissipation in a 3D
system. Liu4 demonstrated the use of 3D copper pillars
capped with tin to form a solder joint for integration of de-
vice layers. The copper pillars were fabricated on copper
filled TSVs patterned in each layer. Stacking was achieved
by flip chip bonding. This stacking architecture provides a
means to improve heat dissipation of 3D ICs by providing
microchannels for coolant to flow through. In a similar
approach, IBM demonstrated microchannel heatsinks, dis-
tributed among different device layers.2,3
The pillars developed by Liu were formed by electroplat-
ing copper and a small amount of tin inside a thick poly-
meric mold before removing the mold.36 This is a robust
method that results in an array of features fabricated in
032002-3 Rao, Lusth, and Burkett: Demonstration of electrical connectivity between self-assembled structures
parallel. However, formation of tall features requires long
electroplating times. In this paper, a novel self-assembly
approach is used to form an array of various 3D structures.
Because solder is used to assist in the folding process, the
3D structure will contain a bump of solder, providing an effi-
cient pillar ready for bonding to electronic stacks.
Following the work of Gracias et al.13 in using dip-
coating to apply solder, our group formed 3D structures of
various shapes and sizes attached to silicon substrates.3739
These structures offer a solder reservoir that can be exploited
in stacking device layers. 3D structures are formed by SBSA
using conventional microfabrication techniques and leverage
surface tension of molten solder. Arrays of 3D structures can
be produced in parallel and at low cost. The SBSA approach
requires a 2D metal pattern layout followed by immersion in
molten solder. A sacrificial oxide layer exists underneath the
2D pattern faces but not underneath the pattern base. Solder
reflow, after etching the sacrificial layer, initiates rotation of
the pattern faces by surface area minimization. The pattern
base remains attached to the silicon surface forming an anch-
ored 3D structure. The three major process components of
SBSA are highlighted in Fig. 3. The 2D patterns undergo
rotational transformation to form 3D structures and can be
clearly viewed in a video.40 One advantage in using SBSA
structures for 3D stacking is that the reflow step can be per-
formed at any time giving flexibility to the stacking
approach. The disadvantage is surface area of the die con-
sumed in forming the 2D metal patterns. Currently, the lay-
out footprint is larger than the final structure base
dimensions to provide room for the pattern faces; the spacing
between two SBSA structures cannot be less than the sum of
the base and twice the height. A cubic structure would be the
most efficient in terms of density. Truncated pyramids with a
square base would have a slightly lower spacing density.
III. EXPERIMENTAL PROCEDURES
Our group has developed a process flow for fabricating
various polyhedra37 by SBSA. We also studied solder
FIG. 3. (Color online) Schematic representation of the SBSA process illus-
trating: (a) dip soldering with too large a gap between free and fixed faces,
(b) solder bridging resulting from an ideal gap, and (c) folding of success-
fully bridged faces.
JVST B - Microelectronics and Nanometer Structures
032002-3
TABLE I. Dip solder processing parameters.
Parameters used in dip solder processing
Solder Alloy 44.7Bi-22.6Pb-8.3Sn-5.3Cd-19.1In
Dip Temperature 97  C
Dip time 90 s
Metal stack Evaporated Ti/electroplated Cu
Sacrificial layer Electron beam evaporated SiO2
thickness and roughness after dip soldering38 as well as sol-
der bridging.39 Based on our previous work, a low melting
point solder was chosen for this work. Process parameters for
dip soldering are shown in Table I. A number of variables
were found to influence solder bridging and the folding yield:
gap size, face thickness, number of faces, solder coverage,
face length, and face geometry. In general, small gap spac-
ings and thick metal pads favored solder bridging for all pat-
tern shapes. A gap spacing of 7.5 lm and metal pad thickness
of 4.9 lm provided the highest solder bridging yield. A
reduced number of faces resulted in improved folding. Face
counts of three and four provided the highest solder bridging
and folding yields. In addition, truncated faces showed a
much higher probability of folding compared to regular faces.
Given these considerations, four truncated faces with a metal
pad thickness of 4.9 lm and a gap spacing of 7.5 lm were
used to obtain 3D structures on an underlying conducting
channel. Other researchers investigating the self-folding pro-
cess for complex structures, such as dodecahedra, icosahedra,
and truncated octahedra, found compactness in the 2D pattern
to heavily influence folding yields41 and can be used as a
design criterion.42 Another interesting investigation describes
the hierarchy of assembly steps to form microcontainers.43
Placing SBSA structures on the conducting channel
required additional dielectric layers compared to our previ-
ous work. One dielectric layer separates the conducting
channel from the silicon substrate while a second dielectric
layer protects the conducting channel during the sacrificial
layer etch and provides an insulating layer above the chan-
nel. The dielectric materials and sacrificial layer need to be
different so that they are not removed in the etch step.
Magnesium oxide (MgO) was chosen for the sacrificial layer
since a SiO2 etchant would etch other dielectric layers.
Electron beam evaporation was used to deposit a MgO film
of 200 nm in thickness. A thermally grown SiO2 film,
200 nm thick, formed the bottom dielectric layer while an
electron beam evaporated SiO2 film, 100 nm thick, formed
the dielectric layer on top of the buried channel.
A lithography step followed by MgO etching provided an
anchored structure base. Titanium, 17 nm thick, was depos-
ited by evaporation to serve as an adhesion layer followed
by a copper seed layer, 75 nm thick. Pattern plating was pos-
sible using lithography. Copper, 4.9 lm thick, was deposited
using dc electroplating and formed the metal 2D patterns.
An additional lithography step was performed to mask the
MgO layer with photoresist, a material that has poor adhe-
sion to solder. Diced samples were treated with water soluble
flux maintained at room temperature. The flux was used to
032002-4 Rao, Lusth, and Burkett: Demonstration of electrical connectivity between self-assembled structures 032002-4

remove any metallic oxide from the patterns before applica-

tion of solder. A low temperature solder alloy (melting
point 47  C) was used for dip soldering. Our previous
work showed the best overall performance for this solder in
terms of bridging and folding yield. The samples were
dipped vertically in molten solder to deposit solder on the
2D metal patterns. The melt temperature was maintained at
97  C. While in solution, the samples were agitated for 90 s.
Dipping was followed by a deionized water rinse.
The sacrificial layer, underneath the metal faces, was
etched with magnesium oxide etchant. The etch frees the
surrounding faces from the substrate, while solder keeps the
faces attached to the fixed central metal base. The surround-
ing faces were hinged by solder in such a way that the metal
faces were able to lift away from the substrate plane and to-
ward the central metal base when solder reflow occurs.
Solder reflow was performed in a dilute aqueous hydrochlo-
ric acid solution maintained at 60  C.

A. MgO sacrificial layer

Because our previous work incorporated SiO2 as the sac-
rificial layer, experiments were conducted to determine the
suitability of MgO as a sacrificial layer. Specifically, solder
bridging and 3D assembly were investigated for structures
with the number of square faces varying from two to eight
(face length 300 lm). Additionally, solder bridging and
3D assembly were investigated for the truncated square pyr-
amid (150 lm nominal length and 300 lm width) patterns.
Solder bridging yield was determined by visual inspection
for proof of solder hinging a base and the surrounding faces.
Failures in solder bridging appeared markedly different from
successful bridging as shown in Fig. 4. The bridging yield
for 2D patterns of boxes of different face counts and trun-
cated square pyramids on both SiO2 and MgO sacrificial
layers were compared. For 2D patterns that exhibited suc-
cessful bridging, folding yields were determined for the pat-
terns on each sacrificial layer. FIG. 4. SEM images showing (a) successful bridging and (b) unsuccessful
bridging of a 2D truncated square pyramid. In (b), the arrow points to the
bridging failure.
B. Solder standoff height in a 3D structure
When the base and faces of a 2D metal pattern are com- for 30 min and allowed to cool to room temperature. The sol-
pletely covered with solder, the folded structure exhibits a der standoff height was determined by viewing the structure
solder bump on top of the structure. The height of the solder in a scanning electron microscope (SEM). The measure-
above the structure is referred to as the solder standoff ments were repeated for five structures to provide an average
height. The complete coverage of solder on 2D metal pat- and standard deviation in the standoff height.
terns is referred to as face-soldering. When resist is used to The standoff height of the truncated square pyramid was
mask the inside pattern areas, only 45 lm along the edges of validated using Surface Evolver, a software tool. Surface
the pattern will contain solder after dipping. We refer to this Evolver is an open-source program that predicts the optimal
process as edge soldering. Both face and edge-soldering are shape of a constrained surface subjected to various forces.44
illustrated in Fig. 5. It has previously been used to simulate the folding process
To assess the quality of the solder bump for both face and for hollow and patterned polyhedra that rely on liquid solder
edge-soldered structures, cross-sectional grinding was per- hinges45 and has been applied to predict the standoff height
formed on the 3D structures. A Struers benchtop system was of ball-grid array solder joints.46 In our work, surface tension
used with a platen speed of 300 rpm and silicon carbide pol- and gravity were modeled to determine the ultimate shape of
ishing paper. the pyramid. In determining the surface energy, one takes
To assess thermal stability, a folded truncated square pyr- into account surface tension and gravitational forces. The
amid was heated in a vacuum oven at five different tempera- total surface energy can be computed with the following
tures: room temperature, 120  C, 165  C, 225  C, and 300  C equation:

J. Vac. Sci. Technol. B, Vol. 31, No. 3, May/Jun 2013

032002-5 Rao, Lusth, and Burkett: Demonstration of electrical connectivity between self-assembled structures 032002-5

Unfortunately, Surface Evolver, while adequate for pre-

dicting solder bump height, is not powerful enough to model
the folding process in and of itself. Thus, it cannot be used to
predict whether or not a 2D structure of a given size and sol-
der deposition thickness will fold or not. Therefore, a ques-
tion that arises from this study, How small can one make an
SBSA structure?, appears to require empirical studies. One
simple study that can be performed in the near future is the
wettability by molten solder of nanoscale sized 2D patterns,
determining the point at which dip-soldering fails as a way
to deposit solder.

C. SBSA structures on an underlying conducting

channel
Conventional metal patterning and dip soldering was used
to obtain SBSA structures on an underlying channel to simu-
late TSVs. An underlying conducting channel of width
54 lm and a length of 1.8 mm was formed by depositing a
thin layer of Ti (17 nm) for adhesion followed by Cu
(100 nm). Both films were deposited by electron beam evap-
oration. Photolithography was used to pattern the resist
before metal deposition. A liftoff step using ultrasonic agita-
tion formed the conducting channel. SiO2, 100 nm thick, was
deposited by electron beam evaporation for the dielectric
layer. Lithography was used to create an opening in the
dielectric. Copper was evaporated to fill the opening and
provide metal contacts for the underlying channel.
Previous experiments39 showed significantly higher yields
for both truncated pyramids and truncated square pyramids.
Likely, the improved yields for these structures is due to the
lower energy needed to rotate the smaller faces and reduced
competition between faces when folding. An example of a
folded structure is shown in Fig. 6. In fact, the example illus-
trates a slight failure, the overfilling of the polyhedron with
solder. It is this type of error we wish to exploit for chip
stacking applications.

D. Currentvoltage characteristics
FIG. 5. SEM images of (a) face soldered and (b) edge soldered truncated I-V characteristics were obtained for the 3D structures
square pyramid 2D patterns. Face soldering involves complete coverage of
the 2D patterns while edge soldering limits solder deposition to the edges of
using a Signatone 1600 probe analyzer. Electrical continuity,
the folding faces.

U TdA qgzdA;
A A

where T is the surface tension, A is the face area, z is the sol-

der height, q is the solder density, g is the gravitational con-
stant, and U is the total energy. By default, Surface Evolver
uses gradient descent to find the minimum surface area. In
our model, solder bump height was made an optimizing pa-
rameter. The solder volume was estimated by multiplying
the area of the 2D truncated square pyramid pattern by the
thickness of the deposited solder layer, as determined by
inspection in a SEM. The height of the solder bump, as
determined by Surface Evolver, showed good agreement
with the actual height of the bump formed when the pyramid
was assembled. FIG. 6. SEM image showing successful folding of a 3D structure.

JVST B - Microelectronics and Nanometer Structures

032002-6 Rao, Lusth, and Burkett: Demonstration of electrical connectivity between self-assembled structures 032002-6

from solder bump to solder bump, was determined by prob-

ing two 3D structures connected through the conducting
channel. Two channel materials were investigated, copper
and gold. Copper is a convenient material to use for the
channel although without a diffusion barrier copper migra-
tion will be an issue. For that reason, gold was also used, as
it is inert and highly resistant to oxidation. Fabrication of the
gold channel followed a similar process described earlier,
except that chromium was used as the adhesion layer.
I-V measurements were obtained for 3D structures, con-
nected through the channel, subjected to the range of temper-
atures described in Sec. III B. The measurements were
obtained at room temperature once the samples were allowed
to cool. Samples were also exposed to thermal cycling with
a ramp rate of 2  C per minute until reaching 165  C. They
remained at this temperature for 30 min and were then
cooled to room temperature. I-V measurements were per-
formed after cycles 1, 2, 4, 10, and 20. Samples were also
thermally cycled in a similar manner until reaching 300  C.
The electrical stability was determined from data acquired
during these tests. Samples were cleaned of oxidation with
water-soluble flux before measuring.

IV. EXPERIMENTAL RESULTS

A. MgO sacrificial layer
As stated earlier, there is a need for an alternative sacrifi-
cial layer that will resist the etching of the SiO2 dielectric
layer. Bridging and folding yields were evaluated for SBSA
structures fabricated with two different sacrificial layers, FIG. 7. Cross sectional SEM images of (a) face-soldered and (b) edge-
MgO and SiO2. Experiments show very little difference in soldered structures that have been ground to expose their interiors. The col-
the yields for these layers. This suggests that a MgO film lapse of (b), which was fabricated to have a hollow interior, indicates that
was an acceptable alternative to SiO2 as a sacrificial layer. (a) may be free of large voids.

B. Solder standoff height in 3D structure square pyramid patterns. The model of the solder block is
refined to provide a minimum surface area shape. The height
To determine if the solder bump inside the 3D structure
of the solder block was varied in the program to obtain the
was solid and free of voids, the samples were mechanically
exact solder bump height of 72.1 lm as determined in an
lapped and inspected. Figure 7 shows cross sections of both
SEM image shown in Fig. 9(a). The top view and side view
face- and edge-soldered structures. We can infer that the
of the minimum surface area shaped solder obtained using
face-soldered structures were completely filled with solder
Surface Evolver are shown in Figs. 9(b) and 9(c). The solder
and the edge-soldered versions contained voids due to the
volume obtained by simulation was 7.95  106 lm3 as seen
fact that the edge-soldered structure, shown in (b), collapsed
in the 2D pattern. The volume obtained in the 2D model was
from the slightest amount of grinding. Since the face-
used in the 3D truncated square pyramid structure. The simu-
soldered version, shown in (a), stood up to the grinding, we
lated solder was again refined to obtain the minimum surface
believe it was essentially void free. Face-soldered structures
area constrained by metal walls in the 3D structure. The
are envisioned for use in chip stacking applications where
standoff height of 34.2 lm, obtained from Surface Evolver,
the solder reservoir can be used to stack hybrid layers.
was close to the experimental value of 34.6 lm for the
Solder standoff height was measured when the structure
reflowed truncated square pyramid structure as shown in
was exposed to different temperatures. Figure 8 indicates a
Fig. 10. This confirms that dip soldering parameters produce
relatively constant solder standoff height for all investigated
a constant and durable solder standoff height applicable for
temperatures. This suggests a durable and thermally resistant
chip stacking applications.
solder standoff height that can be used for chip stacking
applications. However, the solder bump was not subjected to
any forces other than gravity, so the integrity of the entire C. SBSA structures on underlying conducting
structure at higher temperatures after chip bonding should be channels
the subject of a future study. 3D structures were developed on an underlying conduct-
To validate the solder standoff height, the Surface ing channel. Figure 11 shows the SEM images of these 3D
Evolver tool was used to model the 2D and 3D truncated structures on the conducting channel. The folding yield of

J. Vac. Sci. Technol. B, Vol. 31, No. 3, May/Jun 2013

032002-7 Rao, Lusth, and Burkett: Demonstration of electrical connectivity between self-assembled structures 032002-7

FIG. 8. Solder standoff height showing (a) a SEM image of a face-soldered

truncated square pyramid and (b) measured heights for different
temperatures.

3D structures on the conducting channel was evaluated and

compared with the yield of 3D structures formed on bare sili-
con. Work still needs to be done in controlling solder volume
due to the varying thickness of deposition from dip-
soldering, as seen in Fig. 11(a). Figure 12 shows that the
yield of 3D structures on an underlying channel is independ-
ent of where they are formed (channel or bare silicon). The
yield is substantially higher for the truncated square pyramid
than the truncated pyramid and is consistent with our previ-
ous findings.39 These results suggest that the SBSA process
is a robust method and in the future can be extended to pro-
vide high yield 3D structures on metal-filled TSVs.

D. I-V characteristics
The truncated square pyramid structures developed on an
underlying channel were probed for electrical continuity.
Two different channel materials, copper and gold, were
used. The electrical resistance of two 3D structures devel-
oped on underlying copper and gold channels were found to
be 17.3 and 14.9 X, respectively, after calibrating the probe
resistance. The electrical connection between two 3D struc-
tures suggests successful formation of SBSA structures.
FIG. 9. (a) SEM image of solder deposited on a 2D truncated square pyramid
and Surface Evolver simulations showing (b) top view and (c) side view of
the solder bump on a 2D truncated square pyramid.
The 3D structures developed on the underlying channels
were exposed to various temperatures. I-V measurements
were performed on two interconnected 3D structures after
cooling the samples to room temperature. Figure 13(a)

JVST B - Microelectronics and Nanometer Structures

032002-8 Rao, Lusth, and Burkett: Demonstration of electrical connectivity between self-assembled structures
FIG. 10. (Color online) (a) SEM image of a small truncated square pyramid
after reflow (large pyramids in the background); (b) and (c) Surface Evolver
simulations showing top and side views of the same structure.
shows that for temperatures above 165  C, the current
decreases for a given voltage for structures on the copper
channel. The highest temperature treatment (300  C) shows
negligible current flow between SBSA structures through the
channel. The low current is attributed to the high tempera-
ture effects on a thin copper channel. Channel resistance val-
ues are shown in Table II. A rapid rise in resistance of the
J. Vac. Sci. Technol. B, Vol. 31, No. 3, May/Jun 2013
032002-8
FIG. 11. SEM images of (a) two truncated square pyramids, (b) two trun-
cated pyramids, and (c) a truncated pyramid and a truncated square pyramid,
that are connected by an underlying conducting channel. Note the structure
on the left in (a) has a larger volume of solder than the structure on the right.
copper channel is observed at 300  C. The increase in resist-
ance may be attributed to the high diffusivity of copper on
SiO2 at elevated temperatures as mentioned by Angyal
et al.47 There is no diffusion barrier present in the structures.
Another possibility could be the dissolution of copper into
the solder. Figure 13(b) suggests a linear I-V curve for
SBSA structures developed on a gold channel regardless of
032002-9 Rao, Lusth, and Burkett: Demonstration of electrical connectivity between self-assembled structures 032002-9

TABLE II. Resistance of underlying channels at different temperatures.

Resistance (X)

Temperature ( C) Copper channel Gold channel

27 6.0 8.0
120 6.0 8.2
165 7.2 8.4
225 315.0 9.0
300 1044.8 10.5

FIG. 12. (Color online) Folding yields of a truncated square pyramid and a
truncated pyramid developed on an underlying channel.

high temperature exposure. This shows that SBSA structures

form an electrically continuous set of elements on a gold
channel, even when exposed to high temperature. A linear
curve was observed for both high and low voltage bias indi-
cating the use of SBSA structures in high and low powered
3D integrated circuits.

FIG. 14. (Color online) I-V measurements for two truncated square pyramids
developed on: (a) a copper channel and (b) a gold channel after being ther-
mally cycled from room temperature to 165  C.

TABLE III. Resistance of 3D structures connected by an underlying channel

thermally cycled from room temperature to 165  C.

Copper channel Gold channel

resistance (X) with resistance (X)
Cycle count 3D structures with 3D structures

0 17.3 14.9
1 24.5 16.9
2 30.4 22.6
4 47.4 25.4
FIG. 13. (Color online) I-V measurements for two truncated square pyramids 10 55.1 25.8
developed on: (a) a copper channel and (b) a gold channel after thermal 20 83.9 27.8
treatments.

JVST B - Microelectronics and Nanometer Structures

032002-10 Rao, Lusth, and Burkett: Demonstration of electrical connectivity between self-assembled structures 032002-10

FIG. 15. (Color online) I-V measurements for two truncated square pyramids
developed on a gold channel after being thermally cycled from room tem-
perature to 300  C.

Electrical reliability of 3D structures when exposed to

thermal cycling was also investigated. 3D structures devel-
oped on a copper channel were thermally cycled from room
temperature to 165  C. Figure 14(a) depicts a decrease in the
magnitude of the slope with an increase in the number of
cycles, suggesting an increase in the resistance as cycle
count increases. The decreasing trend was observed across
all voltages. As expected, the lower resistance observed in
Fig. 14(b) suggests the 3D structures on a gold channel are
somewhat more resistant to thermal cycling from room tem-
perature to 165  C. The resistance is tabulated for copper and
gold channels in Table III.
The 3D structures on a gold channel were further ther-
mally cycled from room temperature to 300  C. Figure 15
depicts a linear I-V curve; the resistance increases as thermal
cycle count increases (see Table IV). At higher voltage
biases, conduction failures occurred for thermal cycle counts
of 4, 10, and 20.
It appears that SBSA structures are intolerant of thermal
cycling at 300  C. Figure 16 shows before (a) and after [(b),
(c)] SEM images of a truncated square pyramid having
undergone high temperature thermal cycling. Careful exami-
nation of (b) and (c) shows that the walls have been forced FIG. 16. (Color online) SEM images showing the effects of high temperature
outwards and the middle solder bump has slumped in places. thermal cycling on a truncated square pyramid: (a) before cycling; (b) and
This slumping is likely an indicator of the increased electri- (c) after cycling.
cal resistance. Possible failure mechanisms include the dis-
solution of copper into solder and possible dewetting of the been observed;48 it may be that hidden cracks are contribut-
solder from the base of the structure. In addition, an increase ing to our increases.
in electrical resistance due to solder cracks has previously
V. CONCLUSIONS
TABLE IV. Resistance of underlying gold channel thermally cycled from
Vertical integration of electronic devices provides the
room temperature to 300  C.
ability to increase functionality in a reduced amount of space
Cycle count Resistance (X) gold channel compared to the current two-dimensional approach. A sys-
tem leveraging copper posts to separate substrates for ther-
0 8.0
mal management and copper-filled TSVs for vertical
1 10.4
connections will advance electronic packaging schemes. In
2 11.0
4 11.6
this paper, we describe a 3D copper structure that naturally
10 12.2 provides a solder reservoir for connecting layers of elec-
20 13.2 tronic devices. Choosing the appropriate solder thickness on
the 2D metal pattern ensures a bump of solder will result in

J. Vac. Sci. Technol. B, Vol. 31, No. 3, May/Jun 2013

032002-11 Rao, Lusth, and Burkett: Demonstration of electrical connectivity between self-assembled structures 032002-11

10
the folded structure. We have demonstrated an electrical J. Y. Park, K. T. Kim, M. S. Sung, and J. J. Pak, in Proc. Int. Conf. on
path between 3D structures that are placed upon a conduct- Optical MEMS (IEEE, California University, Berkeley, CA, 2003), p. 79.
11
A. Azam, K. E. Laflin, M. Jamal, R. Fernandes, and D. H. Gracias,
ing channel as a way to simulate electrical connections Biomed. Microdevices 1, 51 (2011).
between the structure and TSVs. This proof-of-concept was 12
J.-Z. Cheng, Z.-Y. Sun, C.-X. Zhang, L.-J. An, and Z. Tong, J. Chem.
considered necessary before pursuing the integration of Phys. 128, 074904 (2008).
13
D. H. Gracias, V. Kavthekar, J. C. Love, K. E. Paul, and G. M.
SBSA structures with the very labor intensive TSVs.
Whitesides, Adv. Mater. 14, 235 (2002).
In terms of a suitable sacrificial layer for the SBSA pro- 14
K. Suzuki, H. Yamada, H. Miura, and H. Takanobu, Microsyst. Technol.
cess, MgO was found to be an acceptable sacrificial layer. 13, 1047 (2007).
15
The solder standoff height remained relatively constant after R. T. Schweller, Ph.D. dissertation (Northwestern University, USA, 2007).
16
A. Benitez, J. Esteve, and J. Bausells, in Proc. of the IEEE MEMS Conf.
exposure to different temperatures. The solder volume calcu- (IEEE, Amsterdam, Netherlands, 1995), p. 404.
lation, using Surface Evolver, validated the observed stand- 17
N. B. Bowden, Ph.D. dissertation (Harvard University, USA, 1999).
18
off height of solder deposited on a 2D pattern. Mechanical G. M. Whitesides and B. Grzybowski, Science 295, 2418 (2002).
19
grinding results demonstrated void-free solder filling for a R. Knuesel, S. Bose, W. Zheng, and H. O. Jacobs, in Materials Research
Society Symposium Proc. (Cambridge University Press, Cambridge, UK,
face-soldered truncated square pyramid structure. 2007), p. 313.
The fabrication of 3D structures by the SBSA method is 20
K. F. Harsh, V. M. Bright, and Y. C. Lee, in Proc. Electronic Components
not significantly affected by underlying patterns. Truncated 21
and Technology Conf. (IEEE, Las Vegas, NV, 2000), p. 1690.
square pyramids and truncated pyramids on an underlying T. L. Breen, J. Tien, S. R. J. Oliver, T. Hadzic, and G. M. Whitesides,
Science 284, 948 (1999).
channel show similar yields as compared to those fabricated 22
N. Bassik, G. M. Stern, and D. H. Gracias, Appl. Phys. Lett. 95, 091901
on a silicon substrate. This suggests that, in the future, 3D (2009).
23
structures can be developed on copper filled TSVs patterned T. G. Leong, A. M. Zarafshar, and D. H. Gracias, Small 6, 792 (2010).
24
on a silicon wafer, without compromising yield. The 3D P. W. Green, R. R. A. Syms, and E. M. Yeatman, Microelectro Syst. 4,
170 (1995).
structures are observed to be electrically stable at different 25
K. Harsh and Y. C. Lee, Proc. SPIE 3289, 177 (1998).
temperature treatments, provided the underlying conducting 26
I. U. Abhulimen, S. Polamreddy, S. L. Burkett, L. Cai, and L. Schaper,
channel remains stable at these temperatures. The solder- J. Vac. Sci. Technol. B 25, 1762 (2007).
27
A. Kamto, Y. Liu, L. Schaper, and S. L. Burkett, Thin Solid Films 518,
filled 3D structure on a gold channel showed linear I-V char-
1614 (2009).
acteristics when thermally cycled from room temperature to 28
R. Aschenbrenner, in 7th Int. Conf. on Electronic Packaging Technology
165  C. Thermal cycling from room temperature to 300  C (IEEE, Shanghai, China, 2006), pp. 13.
29
results in crack formation in the solder alloy and reduces the A. Jain, R. Jones, R. Chatterjee, and S. Pozder, IEEE Trans. Components
Packaging Technol. 33, 56 (2010).
thermoelectric stability of the SBSA structures. 30
S. C. Johnson, Semicond. Int. 33, 12 (2010).
31
Advanced Electronic Packaging (IEEE Press Series on Microelectronic
ACKNOWLEDGMENTS Systems, 2nd ed.), edited by R. K. Ulrich and W. D. Brown (Wiley-
Interscience, New York, 2006).
The authors would like to acknowledge the support of 32
H. Mizunuma, Y.-C. Lu, and C.-L. Yang, IEEE Trans. Computer-Aided
The University of Alabama Central Analytical and the Des. Integr. Circuits Syst. 30, 1293 (2011).
33
Microfabrication Facilities. This research was sponsored by J. Cong and Y. Zhang, in IEEE/ACM Int. Conf. on Computer-Aided
Design (IEEE, San Jose, CA, 2005), pp. 745752.
the Army Research Laboratory and was accomplished under 34
D. Tuckerman and R. Pease, IEEE Electron Device Lett. 2, 126 (1981).
Cooperative Agreement Number W911NF-10-2-0093. The 35
N. Lei, A. Ortega, and R. Vaidyanathan, in Proc. ASME (ASME, New
views and conclusions contained in this document are those York, 2007), Vol. 42789, pp. 2943.
36
of the authors and should not be interpreted as representing L. Schaper, Y. Liu, S. L. Burkett, A. Kamto, G. Jampana, S. Jacob, and
I. U. Abhulimen, in IEEE 9th VLSI Packaging Workshop (IEEE, Kyoto,
the official policies, either expressed or implied, of the Army Japan, 2008), pp. 145148.
Research Laboratory or the U.S. Government. 37
M. Rao, J. C. Lusth, and S. L. Burkett, J. Vac. Sci. Technol. B 27, 76
(2009).
38
M. Rao, J. C. Lusth, and S. L. Burkett, J. Vac. Sci. Technol. B 29, 042003
1
E. Beyne and B. Swinnen, in IEEE Int. Conf. IC Design and Technology (2011).
39
(IEEE, Austin, TX, 2007), p. 1. M. Rao, J. C. Lusth, and S. L. Burkett, J. Vac. Sci. Technol. B 30, 032001
2
D. Sekar, C. King, B. Dang, T. Spencer, H. Thacker, P. Joseph, M. Bakir, (2012).
40
and J. Meindl, in Proc. Int. Interconnect Technol. Conf. (IEEE, M. Rao, Available: http://beastie.cs.ua.edu/~madhav/selfAssembly/
Burlingame, CA, 2008), pp. 1315. trsqpyHiDef.wmv (2011) [Online].
3 41
T. Brunschwiler, B. Michel, H. Rothuizen, U. Kloter, B. Wunderle, H. A. Azam, T. G. Leong, A. M. Zarafshar, and D. H. Gracias, PLoS One 4,
Oppermann, and H. Reichl, in 11th IEEE Conf. Thermal and e4451 (2009).
42
Thermomechanical Phenomena Electronic Systems (IEEE, Orlando, FL, S. Pandey, M. Ewing, A. Kunas, N. Nguyen, D. H. Gracias, and G.
2008), pp. 11141125. Menon, Proc. Natl. Acad. Sci. U.S.A. 108, 19885 (2011).
4 43
Y. Liu, Ph.D. dissertation (University of Arkansas, USA, 2009). D. J. Filipiak, A. Azam, T. G. Leong, and D. H. Gracias, J. Micromech.
5
D. H. Gracias, J. Tien, T. L. Breen, C. Hsu, and G. M. Whitesides, Science Microeng. 19, 1 (2009).
44
289, 1170 (2000). K. Brakke, Exp. Math. 1, 141 (1992).
6 45
H. He, J. Guan, and J. L. Lee, J. Controlled Release 110, 339 (2006). T. G. Leong, P. A. Lester, T. L. Koh, E. K. Call, and D. H. Gracias,
7
R. T. Howe, in 32nd Int. Symposium on Electron, Ion, and Photon Beams Langmuir 23, 8747 (2007).
46
(Journal of Vacuum Science and Technology, Fort Lauderdale, FL, 1988), L. J. Ladani and J. Razmi, IEEE Trans. Device Mater. Rel. 9, 348 (2009).
47
Vol. 6, p. 1809. M. S. Angyal, Y. Shacham-Diamand, J. S. Reid, and M.-A. Nicolet, Appl.
8
C. A. Mirkin, R. L. Letsinger, R. C. Mucic, and J. J. Storhoff, Nature 382, Phys. Lett. 67, 2152 (1995).
48
607 (1996). L. Jian, L. Yongping, Z. Haiyan, W. Zhongwei, and L. Li, in 16th IEEE
9
C. L. Randall, T. G. Leong, N. Bassik, and D. H. Gracias, Adv. Drug Int. Symposium on the Physical and Failure Analysis of Integrated
Deliv. Rev. 59, 1547 (2007). Circuits (IEEE, Suzhou, Jiangsu, 2009), pp. 455459.

JVST B - Microelectronics and Nanometer Structures