Intro to Programmable Logic Devices

Design Alternatives
Microprocessors
Ideal, if fast enough
Gates, MSI, PALs
Outdated, inefficient inflexible
Dedicated Standard Chip Sets
Cheap, but no product differentiation
ASICs
Only for rock-stable, high-volume designs
Programmable Logic
For flexibility and performance

Programmable Logic Device Families

Source: Dataquest
Logic

Standard
ASIC
Logic

Programmable
Logic Dev ices Gate Cell-Based Full Custom
(PLDs) Arrays ICs ICs

SPLDs
(PALs) CPLDs FPGAs

Acronyms
Common Resources
SPLD = Simple Prog. Logic Device Configurable Logic Blocks (CLB)
PAL = Prog. Array of Logic Memory Look-Up Table
CPLD = Complex PLD AND-OR planes
FPGA = Field Prog. Gate Array Simple gates
Input / Output Blocks (IOB)
Bidirectional, latches, inverters,
pullup/pulldowns
Interconnect or Routing
Local, internal feedback, and global

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 Programmable Logic Devices
74 series chips has fixed structure and function,
cannot be changed
A chip that contain relatively large amounts of
logic circuitry with a structure that is not fixed,
called programmable logic device (PLD)

Programmable
logic device as a
black box
Logic gates
Inputs and Outputs
(logic variables) programmable (logic functions)
switches

Programmable Logic Array(PLA)

Logic functions can be realized in sum-of-products
form, a PLA comprises a collection of AND gate
that feeds a set of OR gates

Implement
Sum

Implement
Product

General structure of a PLA

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 Gate-level diagram of a PLA
Programmable,
Programmable,
you can select
you can select
the input of
the input of
AND gate
OR gate

Programmable Array Logic(PAL)

AND plane is programmable, OR plane is fixed
Simpler to manufacture, cheaper

OR plane
fixed,
Programmable, f1=P1+P 2
you can select
the input of
AND gate

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 CAD tools
It is impossible to design AND/OR
plane by hand
Automatically generate configuration
of AND/OR plane for PLA and PAL
Generate a file (programming file,
fuse map, bit stream file) for
programmable logic device

Complex Programmable Logic Devices(CPLDs)

PLAs and PALs are useful for

implement small digital circuits
CPLD use to implement larger
digital circuits
A CPLD chip comprises multiple
circuit blocks, each block similar to
a PLA or a PAL

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 Structure of a complex programmable logic device

Field-Programmable Gate Arrays (FPGA)

Can implement
larger circuit
than CPLD

Basic build block

is logic blocks,
each logic
blocks can be
configure
independently

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 Programmable Logic Devices

Types of PLDs
Read Only Memory (ROM)
Programmable Logic Arrays (PLA)
Programmable Array Logic (PAL)

Field Programmable Gate Arrays (FPGA)

Programmable Logic Devices

Simple logic arrays

implement 2 level logic circuits (AND/OR)
based on regular array structure
several types
Read Only Memori es (ROMs and PROMs)
Programmable Logi c Array (PLA)
Programmable Array Logi c (PAL)
Field Programmable Gate Arrays (FPGA)
many copies of common building block
each block can be configured for different logic functions and
typically includes a flip flop
programmable interconnect
often includes SRAM blocks
largest FPGAs have about 500K gates plus 500 Kb of SRAM

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 Read-Only Memory (ROM)
A decoder generates 2n mi nterms for the n i nput vari ables.
By i nserti ng OR gates to sum the mi nterns of Boolean functi ons, w e can
generate any desi red combi nati onal ci rcui t.
A ROM i s a devi ce that i ncludes both the decoder and the OR gates w i thi n a
si ngle IC chi p.
A storage of fi xed bi nary i nformati on
ROM chi ps come w i th speci al i nternal li nks that can be fused or broken
(programmi ng)

n inputs
consi sts of n i nput li nes and m output li nes
Each i nput bi t combi nati on i s called an address
Each output combi nati on i s called a w ord
The number of bi ts per w ord i s equal to m 2n x m
The number of possi ble di sti nct addresses i s 2 n ROM
An output w ord i s selected by an uni que address

m outputs

Implementation of Read Only Memory (ROM)

0
ROM can be implemented using
orthogonal arrangement of wires. 1
optional connection at each 2
intersection
decoder puts logic 1 on exactly 3
decoder
inputs

one of the horizontal wires - this 4

can be detected at output if
connection present 5
Some PROMs are configured by 6
breaking connections.
7
high voltage placed across one
input and one output at a time
high current flow causes fuse at
intersection to blow
Other PROMs can be erased and
reprogrammed (EPROMs). stored functions
(0,1,3,4,6), (0,1,3,5,7),
(2,3,6,7), (0,3,4,6)

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 Read-Only Memory (ROM)
Example: 4x4 ROM with AND-OR gates
Truth table
A0 A1 F0 F1 F2 F3
0 0 1 0 1 1
00
A0
01 0 1 0 1 1 0
2x4 1 0 1 1 0 1
A1 decoder 10
11 1 1 1 1 1 0

AND

OR

F0 F1 F2 F3

Read-Only Memory (ROM)

Example: 32x4 ROM

0
A0
1
A1
5x32 2
A2
decoder
A3
A4
31

F0 F1 F2 F3

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 Programmable Logic Array (PLA)

PLA Programming Notation

Programmable Logic Array (PLA)

configurable x0x2x3x4x5
connection
x0x1x2x3x4x5

x0x2x4x5

x0x1x2x5
configurable
connection
x0x4x5

x1x2x3x4

x0 x1 x2 x3 x4 x5
z0 z1 z2 z3 = x0 x1 x2 x3 x4 x5 + x0 x1 x2 x5
PLAs have confi gurable AND-plane & OR-plane.
AND-plane -for Input OR-plane -for Output
Used to i mplement 2-level s-o-p expressi ons

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 Programmable Logic Array (PLA)

The Programmable Logic Array (PLA) shown here is a more general structure than the
PAL. It is comprised of an AND plane and an OR plane. The size of the AND array is
equal to the number of inputs, while the size of the OR array is equal to the number of
terms times the number of outputs. In a PLA connections are programmable in BOTH
the AND array and the OR array.

Programmable Logic Array (PLA)

Inputs

Dense array of Dense array of

AND gates Product OR gates
terms

Outputs

Programmable Array Block Di agram for Sum of Products Form

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 Programmable Devices

F1 = A B C

F2 = A + B + C

F3 = A B C

F4 = A + B + C

F5 = A xor B xor C

F6 = A xnor B xnor C

Programmable Array Logic (PAL)

x0x2x3x4x5

x0x1x2x3x4x5

x0x2x4x5

configurable x0x1x2x5
connection
x0x4x5

x1x2x3x4

x0 x1 x2 x3 x4 x5
z0 z1 z2 = x0x2x3x4x5 + x0x1x2x3x4x5
PAL i s si mi lar to PLA but fi xed OR-plane.
Si mpler to program and cheaper i mplementati on.
Li mi ted number of terms i n each output.

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 Programmable Array Logic (PAL)

PAL programmi ng notati on

Programmable Array Logic (PAL)

The PAL show n

here consi sts of
a fi xed number
of multi ple-i nput
AND gates
combi ned
through
OR terms.
Connecti ons to
each AND are
programmable,
so there i s
consi derable
flexi bi li ty i n the
range of logi c
functi ons that
can be
i mplemented.
The only
li mi tati on i s the
fi xed number of
mi nterms.

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 Programmable Array Logic (PAL)

Design Example: BCD to Gray Code Converter

K-maps
A A
AB AB
Truth Table CD 00 01 11 10 CD 00 01 11 10
A B C D W X Y Z 00 0 0 X 1 00 0 1 X 0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1 01 0 1 X 1 01 0 1 X 0
0 0 1 0 0 0 1 1 D D
0 0 1 1 0 0 1 0 11 0 1 X X 11 0 0 X X
0 1 0 0 0 1 1 0 C C
0 1 0 1 1 1 1 0 10 0 1 X X 10 0 0 X X
0 1 1 0 1 0 1 0
0 1 1 1 1 0 1 1 B B
1 0 0 0 1 0 0 1 K-map for W K-map for X
1 0 0 1 1 0 0 0
1 0 1 0 X X X X AB
A
AB
A
1 0 1 1 X X X X 00 01 11 10 00 01 11 10
CD CD
1 1 0 0 X X X X
00 0 1 X 0 00 0 0 X 1
1 1 0 1 X X X X
1 1 1 0 X X X X
1 1 1 1 X X X X 01 0 1 X 0 01 1 0 X 0
D D

Minimized Functions: C
11 1 1 X X
C
11 0 1 X X

W =A + BD+ BC 10 1 1 X X 10 1 0 X X
X = B C'
Y=B+C B B
K-map for Y K-map for Z
Z = A'B'C'D + B C D + A D' + B' C D'

Programmable Array Logic (PAL)

Design Example: BCD to Gray

Code Converter

Programmed PAL

4 product terms per each OR gate

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 Comparison of PROMs, PLAs & PALs

Can view PROMs and PALs as restricted forms of PLA.

PROMs are logically equivalent to PLA with AND-plane that
generates all minterms and configurable OR-plane
PAL is logically equivalent to PLA with fixed OR-plane in
which each output is the OR of a subset of the ANDs

Different implementations means different capabilities.

means one needs to match device capabilities to the
characteristics of logic equations being generated
consider number inputs & outputs, total number of different
terms (PLAs), number of different terms per output (PALs)
performance characteristics and cost also differ

PROMs most flexible but, if application doesnt require full

flexibility, PALs and PLAs may be preferable.
most parts also include flip flops, allowing sequential circuits

Field Programmable Gate Arrays

FPGAs can be used to construct more complex circuits.

Chip contains a large number (tens of thousands) of configurable

logic building blocks.
typically each block includes a 4 input function generator, a flip
flop and some glue logic
CAD tools map high level circuit to basic blocks, configuring
function generators & other configurable elements as needed

Programmable interconnect used to wire logic blocks.

wire segments connected to logic blocks and to other wire
segments by configurable switches
CAD tools determine switch configuration needed to provide
right connectivity

CAD tools perform mapping, placement , routing.

routing information used in timing analysis & simulation

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 CPLD (Complex Programmable Logic
Device) consists of multiple PLA
blocks that are interconnected to
realize larger digital systems

FPGA (Field Programmable Gate

Array) has narrower logic choices and
more memory elements. LUT (Lookup
Table) may replace actual logic gates

CPLDs and FPGAs

CPLD FPGA
Complex Programmable Logic Device Field-Programmable Gate Array

Architecture PAL/22V10-like Gate array-like

More Combinational More Registers + RAM
Density Low-to-medium Medium-to-high
0.5-10K logic gates 1K to 1M system gates
Performance Predictable timing Application dependent
Up to 250 MHz today Up to 150MHz today
Interconnect Crossbar Switch Incremental

Not shown: Simple PLD (SPLD) Architecture

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 PLD Industry Growth

Design Flow
Design Entry in schematic, ABEL, VHDL,
and/or Verilog. Vendors include Synopsys,
1 Aldec (Xilinx Foundation), Mentor,
Cadence, Viewlogic, and 35 others.

Implementation includes Placement &

Routing and bitstream generation using
2 Xilinxs M1 Technology. Also, analyze
timing, view layout, and more.
M1 Technology

Download directly to the Xilinx

hardware device(s) with 3
unlimited reconfigurations* !!

XC4000 XC4000 XC4000

*XC9500 has 20,000 write/erase cycles

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 Downloading the Design

Where Programmable Logic Fits into the Industry

Key components as:

Processor
Memory
Logic

No high development cost barriers

Recovered time for authoring and innovating
SW improvements reduce design iterations
No lengthy prototyping cycle
Ability to remotely upgrade any networked
system
Ultimate flexibility to manage rapid change

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 Can be used in various engineering labs
Digital Design
Intro/Advanced Digital Design
Computer Architecture
Networking and Communications
Control Systems
Projects and Labs can focus on concept,
not wire wrapping
Complete Software Package for Design,
Synthesis, Implementation and download
Immediate results in hardware

Xilinx FPGA/CPLD families

New leading-edge device families

ISE advantages can be leveraged across

various Engineering courses
Across all device families and design sizes

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 Xilinx Design Tools
v4.2i ISE Software
Complete Software Package Unix & PC Platforms
Linux support using WINE!
Design Entry (Schematic, VHDL,
Verilog)
Synthesis (XST)
Implementation (Translate, Map,
Place & Route)
Simulation (ModelsimXE-II)
iMPACT Programmer (Download
Bistream)
CORE Generator
Parameterizable Cores
StateCAD/State Bencher
State Machine Design
HDL Bencher
Test Bench Generation

Altera Devices
Programmable Logic Families
High & Medium Density FPGAs
Strati x II, Strati x, APEX II,
APEX 20K, & FLEX 10K
Low-Cost FPGAs
Cyclone & ACEX 1K
FPGAs with Clock Data Recovery
Strati x GX & Mercury
CPLDs
MAX 7000 & MAX 3000
Embedded Processor Solutions
Ni os, Excali bur T
Configuration Devices
EPC

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 Altera Design Software
Software & Development Tools:
Quartus II
Stratix II, Stratix, Stratix GX, Cyclone,
APEX II, APEX 20K/E/C, Excalibur, &
Mercury Devices
FLEX 10K/A/E, ACEX 1K, FLEX 6000,
MAX 7000S/AE/B, MAX 3000A Devices

Quartus II Web Edition

Free Version
Not All Features & Devices Included

MAX+PLUS II
All FLEX, ACEX, & MAX Devices

FPGAs Are Good Enough

Adequate capacity, performance, price

200,000 gates, 85 MHz in 1998
1,000,000 gates, 200 MHz in 1999
Standard product advantages
steep learning curve, cost decline
performance gain, speed binning
IC manufacturing is best at mass-production
custom devices have an inherent disadvantage

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 FPGAs are Good Enough Better

Deep submicron ASIC design is difficult

second-order effects burden the traditional logic
abstraction
system designer needs help from EE
Verification is very time consuming
Hardware/software integration is delayed
until a working chip is delivered.

FPGAs Are Better

User can focus on logic, not circuits
Manufacturers solves all circuit problems
clock delay and skew
interconnect delay
crosstalk
I/O standards
FPGAs are 100% tested by generic test
methods
Easy verification, incremental design
Early hardware/software integration

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 FPGAs Are Better Vastly Superior
Avoid the ASIC re-spin cost
design error or market change
Avoid the ASIC inventory risk
over- or under-inventory
obsolescence
Reprogrammability
last-minute design modifications
last-step system customization
field hardware upgrades
reconfiguration per application
reconfiguration per task
ASICs will never offer these features

CPLDs Complement FPGAs

CPLD strengths
Wide address decoding
Synchronous state machines
Short combinatorial pin-to-pin delays
Ideal for glue logic
Low-cost
Single-chip
Non-volatile
In-System Programmable
Quick and easy to use

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 The Compelling Conclusion:
Programmable is the Way to Go!
FPGAs provide performance and flexibility
The performance of custom-hardware
The ease of design and inherent flexibility of a
microprocessor solution
FPGAs avoid the risks of ASICs
The design risk
The time-to-market risk
The inventory risk
CPLDs provide a fast, low-cost alternative
Good for simple designs

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