3.

1 nV/Hz, 1 mA, 180 MHz,

Rail-to-Rail Input/Output Amplifiers
Data Sheet ADA4807-1/ADA4807-2/ADA4807-4
FEATURES PIN CONNECTION DIAGRAMS
Low input noise
VOUT 1 6 +VS
3.1 nV/Hz at f = 100 kHz with 29 Hz 1/f corner
0.7 pA/Hz at f = 100 kHz with 2 kHz 1/f corner VS 2 5 DISABLE
High speed performance with dc precision

12611-001
+IN 3 4 IN
180 MHz, 3 dB bandwidth (G = +1, VOUT = 20 mV p-p)
225 V/s slew rate for 5 V step (rise) Figure 1. 6-Lead SC70 and 6-Lead SOT-23 Pin Configuration (ADA4807-1)
47 ns settling time to 0.1% for 4 V step
VOUT1 1 8 +VS
125 V and 3.7 V/C maximum input offset voltage and drift
IN1 2 7 VOUT2
100 nA and 250 pA/C maximum input offset current and drift +IN1 3 6 IN2

12611-058
Low distortion (HD2/HD3), VS = 5 V, VOUT = 2 V p-p VS 4 5 +IN2
141 dBc/144 dBc at 1 kHz
Figure 2. 8-Lead MSOP Pin Configuration (ADA4807-2)
112 dBc/115 dBc at 100 kHz
95 dBc/79 dBc at 1 MHz VOUT1 1 10 +VS
Low power operation IN1 2 9 VOUT2
+IN1 3 8 IN2
1.0 mA quiescent supply current per amplifier at 5 V VS 4 7 +IN2

12611-059
Dynamic power scaling DISABLE1 5 6 DISABLE2

Fully specified at +3 V, +5 V, and 5 V supplies Figure 3. 10-Lead LFCSP Pin Configuration (ADA4807-2)
Rail-to-rail inputs and outputs
VOUT1 1 14 VOUT4
APPLICATIONS
IN1 2 13 IN4
High resolution analog-to-digital converter (ADC) drivers
+IN1 3 12 +IN4
Portable and battery-powered instruments and systems
+VS 4 ADA4807-4 11 VS
High component density data acquisition systems
+IN2 5 10 +IN3
Audio signal conditioning
IN2 6 9 IN3
Active filters

12611-104
VOUT2 7 8 VOUT3

Figure 4. 14-Lead TSSOP Pin Configuration (ADA4807-4)

GENERAL DESCRIPTION
The ADA4807-1 (single), ADA4807-2 (dual), and ADA4807-4 These amplifiers are fully specified at +3 V, +5 V, and 5 V supplies
(quad) are low noise, rail-to-rail input and output, voltage and can operate over the industrial 40C to +125C
feedback amplifiers. These amplifiers combine low power, low temperature range.
noise, high speed, and dc precision to provide an attractive The ADA4807-1 is available in 6-lead SOT-23 and space-saving
solution for a wide range of applications from high resolution 6-lead SC70 packages. The ADA4807-2 is available in an 8-lead
data acquisition instrumentation to high performance battery- MSOP and a compact, 3 mm 3 mm, 10-lead LFCSP. The
powered and high component density systems where power ADA4807-4 is available in a 14-lead TSSOP package.
consumption is of key importance.
With only 1.0 mA of supply current per amplifier, the ADA4807-1/ Table 1. Other Rail-to-Rail Amplifiers
ADA4807-2/ADA4807-4 feature the lowest input voltage noise Slew Voltage Max.
Bandwidth Rate Noise VOS
among high speed, rail-to-rail input/output amplifiers in the
Device (MHz) (V/s) (nV/Hz) (mV)
industry and offer a wide bandwidth, high slew rate, fast settling
AD8031/AD8032 80 35 15 1.5
time, and excellent distortion performance. Additionally, these
AD8027/AD8028 190 90 4.3 0.8
amplifiers offer very low input offset voltage and drift performance,
AD8029/AD8030/ 125 62 16.5 5
making them ideal for driving multiplexed and high throughput AD8040
precision 16-/18-bit successive approximation registers (SARs)
and 24-bit - ADCs.

Rev. B Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 20142015 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
ADA4807-1/ADA4807-2/ADA4807-4
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Pin Connection Diagrams ............................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
5 V Supply ................................................................................... 3
5 V Supply...................................................................................... 5
3 V Supply...................................................................................... 7
Absolute Maximum Ratings............................................................ 9
Maximum Power Dissipation ..................................................... 9
Thermal Resistance ...................................................................... 9
ESD Caution .................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 13
Frequency Response................................................................... 13
Frequency and Supply Current ................................................. 15
DC and Input Common-Mode Performance ......................... 16
REVISION HISTORY
9/15Rev. A to Rev. B
Added ADA4807-4 ............................................................. Universal
Changes to Features Section, General Description Section, and
Table 1 .......................................................................................................... 1
Added Figure 4, Renumbered Sequentially .................................. 1
Changes to Table 2 ............................................................................ 3
Changes to Table 3 ............................................................................ 5
Changes to Table 4 ............................................................................ 7
Deleted Figure 6, Renumbered Sequentially............................... 10
Changes to Figure 6 ........................................................................ 10
Added Figure 9 and Table 9, Renumbered Sequentially ........... 12
Changes to Figure 20 ...................................................................... 14
Added Figure 21.............................................................................. 14
Added Figure 31 and Figure 32..................................................... 16
Added Figure 35.............................................................................. 17
Changes to Figure 39 ...................................................................... 18
Added Figure 42.............................................................................. 19
Deleted Figure 50, Figure 51, Figure 53, and Figure 54 ............. 19
Added Figure 46.............................................................................. 20
Added Figure 49 and Figure 51..................................................... 21
Added Figure 59 and Figure 61..................................................... 23
Changes to DISABLE Circuitry Section ...................................... 25
Added Low Noise FET Operational Amplifier Section............. 26
Added Figure 70, Figure 71, Figure 72, and Power Mode ADC
Driver Section ................................................................................. 27
Added ADC Driving Section and Figure 73 through Figure 77..... 28
Added ADC Driving with Dynamic Power Scaling Section,
Figure 78, Figure 79, and Figure 80 .............................................. 29
Rev. B | Page 2 of 33
Data Sheet
Slew, Transient, Settling Time, and Crosstalk............................. 18
Distortion and Noise.................................................................. 20
Output Characteristics............................................................... 22
Overdrive Recovery and Turn On/Turn Off Times .............. 23
Theory of Operation ...................................................................... 24
Disable Circuitry ........................................................................ 25
Input Protection ......................................................................... 25
Noise Considerations ................................................................. 25
Applications Information .............................................................. 26
Capacitive Load Drive ............................................................... 26
Low Noise FET Operational Amplifier ................................... 26
Power Mode ADC Driver ......................................................... 27
ADC Driving............................................................................... 28
ADC Driving with Dynamic Power Scaling ........................... 29
Layout, Grounding, and Bypassing .......................................... 30
Outline Dimensions ....................................................................... 31
Ordering Guide .......................................................................... 33
Added Figure 58 ............................................................................. 33
Changes to Ordering Guide .......................................................... 33
4/15Rev. 0 to Rev. A
Added ADA4807-2 ............................................................. Universal
Changes to Features Section, General Description
Section, and Pin Connection Diagrams Heading .........................1
Added Figure 2 and Figure 3; Renumbered Sequentially ............1
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................5
Changes to Table 3.............................................................................7
Changes to Table 6 and Figure 4 ......................................................9
Added Figure 7, Figure 8, and Table 8; Renumbered Sequentially ....11
Reorganized Layout, Typical Performance Characteristics
Section.............................................................................................. 12
Added Figure 36 ............................................................................. 16
Changes to Figure 37 Caption, Figure 38 Caption, Figure 39
Caption, and Figure 40 Caption ................................................... 17
Changes to Figure 44 and Figure 47............................................. 18
Change to Theory of Operation Section ..................................... 20
Changes to DISABLE Circuitry Section, Table 9, and Noise
Considerations Section .................................................................. 21
Added Figure 65 and Figure 66 .................................................... 23
Changes to Ordering Guide .......................................................... 25
12/14Revision 0: Initial Version
Data Sheet ADA4807-1/ADA4807-2/ADA4807-4

SPECIFICATIONS
5 V SUPPLY
TA = 25C, VS = 5 V, RLOAD = 1 k to midsupply, RF = 0 , G = +1, VS VICM +VS 1.5 V, unless otherwise noted.

Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
3 dB Bandwidth G = +1, VOUT = 20 mV p-p 180 MHz
G = +1, VOUT = 2 V p-p 28 MHz
Slew Rate G = +1, VOUT = 5 V step, 20% to 80%, rise/fall 225/250 V/s
Settling Time to 0.1% G = +1, VOUT = 4 V step 47 ns
DISTORTION/NOISE PERFORMANCE
Second Harmonic (HD2) fC = 1 kHz, VOUT = 2 V p-p 141 dBc
fC = 100 kHz, VOUT = 2 V p-p 112 dBc
fC = 1 MHz, VOUT = 2 V p-p, ADA4807-1 95 dBc
fC = 1 MHz, VOUT = 2 V p-p, ADA4807-2, 84 dBc
ADA4807-4
Third Harmonic (HD3) fC = 1 kHz, VOUT = 2 V p-p 144 dBc
fC = 100 kHz, VOUT = 2 V p-p 115 dBc
fC = 1 MHz, VOUT = 2 V p-p 79 dBc
Peak-to-Peak Noise f = 0.1 Hz to 10 Hz 160 nV p-p
Input Voltage Noise f = 100 kHz 3.1 nV/Hz
f = 1 kHz 3.3 nV/Hz
f = 10 Hz 5.8 nV/Hz
Input Voltage Noise 1/f Corner 29 Hz
Input Current Noise f = 100 kHz 0.7 pA/Hz
f = 10 Hz 10 pA/Hz
Input Current Noise 1/f Corner 2 kHz
DC PERFORMANCE
Input Offset Voltage
VS VICM +VS 1.5 V ADA4807-1, ADA4807-2 125 20 +125 V
ADA4807-4 175 20 +175 V
+VS 1.5 V VICM +VS ADA4807-1, ADA4807-2 750 140 +750 V
ADA4807-4 850 140 +850 V
Input Offset Voltage Drift VS VICM +VS 1.2 V, TMIN to TMAX 0.7 3.7 V/C
Input Bias Current VS VICM +VS 1.5 V 1.2 1.6 A
+VS 1.5 V VICM +VS 530 1000 nA
Input Bias Current Drift VS VICM +VS 1.2 V, TMIN to TMAX 2.5 3.6 nA/C
Input Offset Current VS VICM +VS 1.5 V 8 100 nA
+VS 1.5 V VICM +VS 25 150 nA
Input Offset Current Drift VS VICM +VS 1.2 V, TMIN to TMAX 30 250 pA/C
Open-Loop Gain 120 130 dB
INPUT CHARACTERISTICS
Common-Mode Input Resistance 45 M
Differential Input Resistance 35 k
Common-Mode Input Capacitance 1 pF
Differential Input Capacitance 1 pF
Input Common-Mode Voltage Range VS 0.2 +VS + 0.2 V
Common-Mode Rejection Ratio (CMRR) VICM = 3 V to +2 V 96 110 dB

Rev. B | Page 3 of 33
ADA4807-1/ADA4807-2/ADA4807-4 Data Sheet
Parameter Test Conditions/Comments Min Typ Max Unit
DISABLE CHARACTERISTICS1
DISABLE Input Voltage2
Low Disabled <1.3 V
High Enabled >1.7 V
DISABLE Input Current
Low Disabled 470 nA
High Enabled 3 nA
DISABLE On Time DISABLE input midswing point to >90% 1.3 1.8 s
of final VOUT, VPD = +VS
DISABLE Off Time DISABLE input midswing point to <10% 270 340 ns
of enabled quiescent current, VPD = VS
OUTPUT CHARACTERISTICS
Saturated Output Voltage Swing RLOAD = 1 k
High +VS 0.08 +VS 0.04 V
Low VS + 0.1 VS + 0.07 V
Linear Output Current3 Sourcing, G = +1, VIN = +VS, RLOAD = varied 50 mA
Sinking, G = +1, VIN = VS, RLOAD = varied 60 mA
Short-Circuit Current Sourcing, G = +1, VIN =+VS, RLOAD= 0 to 80 mA
10
Sinking, G= +1, VIN = VS, RLOAD = 0 to 10 80 mA
Capacitive Load Drive CLOAD = 15 pF, VOUT = 20 mV p-p 17 % overshoot
POWER SUPPLY
Operating Range 2.7 11 V
Quiescent Current per Amplifier Enabled, no load, TA = 25C 1.0 1.1 mA
Disabled, TA = 25C 2.4 4.0 A
Power Supply Rejection Ratio (PSRR)
Positive +VS = 3 V to 5 V, VS = 5 V 98 107 dB
Negative +VS = 5 V, VS = 3 V to 5 V 98 120 dB
1
The disable pin is DISABLE on the ADA4807-1 and DISABLE1 or DISABLE2 for the ADA4807-2 LFCSP package, hereafter referred to as DISABLE for the ADA4807-1/ADA4807-2.
2
See the Disable Circuitry section.
3
See Figure 53 and Figure 56.

Rev. B | Page 4 of 33
Data Sheet ADA4807-1/ADA4807-2/ADA4807-4
5 V SUPPLY
TA = 25C, VS = 5 V, RLOAD = 1 k to midsupply, RF = 0 , G = +1, 0 V VICM +VS 1.5 V, unless otherwise noted.
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
3 dB Bandwidth G = +1, VOUT = 20 mV p-p 170 MHz
G = +1, VOUT = 2 V p-p 28 MHz
Slew Rate G = +1, VOUT = 2 V step, 20% to 80%, rise/fall 145/160 V/s
Settling Time to 0.1% G = +1, VOUT = 2 V step 40 ns
DISTORTION/NOISE PERFORMANCE
Second Harmonic (HD2) fC = 1 kHz, VOUT = 2 V p-p 141 dBc
fC = 100 kHz, VOUT = 2 V p-p 111 dBc
fC = 1 MHz, VOUT = 2 V p-p, ADA4807-1 93 dBc
fC = 1 MHz, VOUT = 2 V p-p, ADA4807-2, 83 dBc
ADA4807-4
Third Harmonic (HD3) fC = 1 kHz, VOUT = 2 V p-p 153 dBc
fC = 100 kHz, VOUT = 2 V p-p 115 dBc
fC = 1 MHz, VOUT = 2 V p-p 78 dBc
Peak-to-Peak Noise f = 0.1 Hz to 10 Hz 160 nV p-p
Input Voltage Noise f = 100 kHz 3.1 nV/Hz
f = 1 kHz 3.3 nV/Hz
f = 10 Hz 5.8 nV/Hz
Input Voltage Noise 1/f Corner 29 Hz
Input Current Noise f = 100 kHz 0.7 pA/Hz
f = 10 Hz 10 pA/Hz
Input Current Noise 1/f Corner 2 kHz
DC PERFORMANCE
Input Offset Voltage
0 V VICM +VS 1.5 V ADA4807-1, ADA4807-2 125 20 +125 V
ADA4807-4 175 20 +175 V
+VS 1.5 V VICM +VS ADA4807-1, ADA4807-2 720 110 +720 V
ADA4807-4 850 110 +850 V
Input Offset Voltage Drift 0 V VICM +VS 1.2 V, TMIN to TMAX 0.7 3.7 V/C
Input Bias Current 0 V VICM +VS 1.5 V 1.2 2.0 A
+VS 1.5 V VICM +VS 500 1000 nA
Input Bias Current Drift 0 V VICM +VS 1.2 V, TMIN to TMAX 2.6 3.8 nA/C
Input Offset Current 0 V VICM +VS 1.5 V 8 100 nA
+VS 1.5 V VICM +VS 25 150 nA
Input Offset Current Drift 0 V VICM +VS 1.2 V, TMIN to TMAX 30 250 pA/C
Open-Loop Gain 113 130 dB
INPUT CHARACTERISTICS
Common-Mode Input Resistance 45 M
Differential Input Resistance 35 k
Common-Mode Input Capacitance 1 pF
Differential Input Capacitance 1 pF
Input Common-Mode Voltage Range VS 0.2 +VS + 0.2 V
CMRR VICM = 1 V to 3 V 96 110 dB

Rev. B | Page 5 of 33
ADA4807-1/ADA4807-2/ADA4807-4 Data Sheet
Parameter Test Conditions/Comments Min Typ Max Unit
DISABLE CHARACTERISTICS1
DISABLE Input Voltage2
Low Disabled <1.3 V
High Enabled >1.8 V
DISABLE Input Current
Low Disabled 360 nA
High Enabled 1.3 nA
DISABLE On Time DISABLE input midswing point to >90% 450 700 ns
of final VOUT, VPD = +VS
DISABLE Off Time DISABLE input midswing point to <10% 270 450 ns
of enabled quiescent current, VPD = VS
OUTPUT CHARACTERISTICS
Saturated Output Voltage Swing RLOAD = 1 k
High +VS 0.05 +VS 0.03 V
Low VS + 0.05 VS + 0.04 V
Linear Output Current3 Sourcing, G = +1, VIN = +VS, RLOAD = varied 50 mA
Sinking, G = +1, VIN = VS, RLOAD = varied 60 mA
Short-Circuit Current Sourcing, G = +1, VIN = +VS, RLOAD = 0 80 mA
to 10
Sinking, G = +1, VIN = VS, RLOAD = 0 to 80 mA
10
Capacitive Load Drive CLOAD = 15 pF, VOUT = 20 mV p-p 24 % overshoot
POWER SUPPLY
Operating Range 2.7 11 V
Quiescent Current per Amplifier Enabled, no load, TA = 25C 950 1000 A
Disabled, TA = 25C 1.3 2.0 A
PSRR
Positive +VS = 1.5 V to 3.5 V, VS = 2.5 V 98 115 dB
Negative +VS = 2.5 V, VS = 1.5 V to 3.5 V 98 130 dB
1
The disable pin is DISABLE on the ADA4807-1 and DISABLE1 or DISABLE2 for the ADA4807-2 LFCSP package, hereafter referred to as DISABLE for the ADA4807-1/ADA4807-2.
2
See the Disable Circuitry section.
3
See Figure 53 and Figure 56.

Rev. B | Page 6 of 33
Data Sheet ADA4807-1/ADA4807-2/ADA4807-4
3 V SUPPLY
TA = 25C, VS = 3 V, RLOAD = 1 k to midsupply, RF = 0 , G = +1, 0 V VICM +VS 1.5 V, unless otherwise noted.

Table 4.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
3 dB Small Signal Bandwidth G = +1, VOUT = 20 mV p-p 165 MHz
G = +1, VOUT = 2 V p-p 28 MHz
Slew Rate G = +1, VOUT = 2 V step, 20% to 80%, rise/fall 118/237 V/s
Settling Time to 0.1% G = +1, VOUT = 2 V step 40 ns
DISTORTION/NOISE PERFORMANCE
Second Harmonic (HD2) fC = 1 kHz, VOUT = 2 V p-p 98 dBc
fC = 100 kHz, VOUT = 2 V p-p 85 dBc
fC = 1 MHz, VOUT = 2 V p-p 65 dBc
Third Harmonic (HD3) fC = 1 kHz, VOUT = 2 V p-p 94 dBc
fC = 100 kHz, VOUT = 2 V p-p 91 dBc
fC = 1 MHz, VOUT = 2 V p-p 68 dBc
Peak-to-Peak Noise f = 0.1 Hz to 10 Hz 160 nV p-p
Input Voltage Noise f = 100 kHz 3.1 nV/Hz
f = 10 kHz 3.3 nV/Hz
f = 10 Hz 5.8 nV/Hz
Input Voltage Noise 1/f Corner 29 Hz
Input Current Noise f = 100 kHz 0.7 pA/Hz
f = 10 Hz 10 pA/Hz
Input Current Noise 1/f Corner 2 kHz
DC PERFORMANCE
Input Offset Voltage
0 V VICM +VS 1.5 V ADA4807-1, ADA4807-2 125 20 +125 V
ADA4807-4 175 20 +175 V
+VS 1.5 V VICM +VS ADA4807-1, ADA4807-2 720 125 +720 V
ADA4807-4 850 125 +850 V
Input Offset Voltage Drift 0 V VICM +VS 1.2 V, TMIN to TMAX 0.7 3.8 V/C
Input Bias Current 0 V VICM +VS 1.5 V 1.2 2.0 A
+VS 1.5 V VICM +VS 500 1000 nA
Input Bias Current Drift 0 V VICM +VS 1.2 V, TMIN to TMAX 2.7 3.8 nA/C
Input Offset Current 0 V VICM +VS 1.5 V 8 130 nA
+VS 1.5 V VICM +VS 25 150 nA
Input Offset Current Drift 0 V VICM +VS 1.2 V, TMIN to TMAX 40 230 pA/C
Open-Loop Gain 104 113 dB
INPUT CHARACTERISTICS
Common-Mode Input Resistance 45 M
Differential Input Resistance 35 k
Common-Mode Input Capacitance 1 pF
Differential Input Capacitance 1 pF
Input Common-Mode Voltage Range VS 0.2 +VS + 0.2 V
CMRR VICM = 0.3 V to 1.3 V 92 110 dB

Rev. B | Page 7 of 33
ADA4807-1/ADA4807-2/ADA4807-4 Data Sheet
Parameter Test Conditions/Comments Min Typ Max Unit
DISABLE CHARACTERISTICS1
DISABLE Input Voltage2
Low Disabled <1.1 V
High Enabled >1.5 V
DISABLE Input Current
Low Disabled 325 nA
High Enabled 500 nA

DISABLE On Time DISABLE input midswing point to >90% 500 700 ns

of final VOUT, VPD = +VS
DISABLE Off Time DISABLE input midswing point to <10% 270 460 ns
of enabled quiescent current, VPD = VS
OUTPUT CHARACTERISTICS
Saturated Output Voltage Swing RLOAD = 1 k
High +VS 0.04 +VS 0.02 V
Low VS + 0.04 VS + 0.03 V
Linear Output Current3 Sourcing, G = +1, VIN = +VS, RLOAD = varied 50 mA
Sinking, G = +1, VIN = VS, RLOAD = varied 60 mA
Short-Circuit Current Sourcing, G = +1, VIN = +VS, RLOAD = 0 to 65 mA
10
Sinking, G = +1, VIN = VS, RLOAD = 0 to 70 mA
10
Capacitive Load Drive CLOAD = 15 pF, VOUT = 20 mV p-p 30 % overshoot
POWER SUPPLY
Operating Range 2.7 11 V
Quiescent Current per Amplifier Enabled, no load, TA = 25C 915 1000 A
Disabled, TA = 25C 1.0 2.0 A
PSRR
Positive +VS = 1.5 V to 3.5 V, VS = 1.5 V 97 113 dB
Negative +VS = 1.5 V, VS = 1.5 V to 3.5 V 97 130 dB
1
The disable pin is DISABLE on the ADA4807-1 and DISABLE1 or DISABLE2 for the ADA4807-2 LFCSP package, hereafter referred to as DISABLE for the ADA4807-1/ADA4807-2.
2
See the Disable Circuitry section.
3
See Figure 53 and Figure 56.

Rev. B | Page 8 of 33
Data Sheet ADA4807-1/ADA4807-2/ADA4807-4

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE
Table 5.
Parameter Rating JA is specified for the worst case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Supply Voltage 11 V
Internal Power Dissipation See Figure 5 Table 6. Thermal Resistance
Input Voltage (Common Mode) VS 0.2 V Package Type JA Unit
Differential Input Voltage 1.4 V 6-Lead SC70, 4-Layer Board 209 C/W
Output Short-Circuit Duration See power
6-Lead SOT-23, 4-Layer Board 223 C/W
derating curves in
Figure 5 8-Lead MSOP 123 C/W
Storage Temperature Range (All Packages) 65C to +125C 10-Lead LFCSP 51 C/W
Lead Temperature (Soldering 10 sec) 300C 14-Lead TSSOP 130 C/W

Stresses at or above those listed under Absolute Maximum 4.0

Ratings may cause permanent damage to the product. This is a
3.5
stress rating only; functional operation of the product at these

MAXIMUM POWER DISSIPATION (W)

or any other conditions above those indicated in the operational 3.0

section of this specification is not implied. Operation beyond

2.5
the maximum operating conditions for extended periods may LFCSP
affect product reliability. 2.0

MAXIMUM POWER DISSIPATION 1.5

The maximum power that can be safely dissipated by the 1.0 SOT-23 TSSOP MSOP
ADA4807-1/ADA4807-2/ADA4807-4 is limited by the associated SC70
rise in junction temperature. The maximum safe junction 0.5

temperature for plastic encapsulated devices is determined by 0

12611-003
40 25 10 5 20 35 50 65 80 95 110 125
the glass transition temperature of the plastic, approximately
AMBIENT TEMPERATURE (C)
150C. Exceeding this limit temporarily can cause a shift in
Figure 5. Maximum Power Dissipation vs. Ambient Temperature for a
parametric performance due to a change in the stresses exerted 4-Layer Board
on the die by the package. Exceeding a junction temperature of
175C for an extended period can result in device failure. ESD CAUTION
Although the ADA4807-1/ADA4807-2/ADA4807-4 are
internally short-circuit protected, this may not be sufficient to
guarantee that the maximum junction temperature (150C) is
not exceeded under all conditions. To ensure proper operation,
it is necessary to observe the power derating curves shown in
Figure 5.

Rev. B | Page 9 of 33
ADA4807-1/ADA4807-2/ADA4807-4 Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

VOUT 1 6 +VS

VS 2 5 DISABLE

12611-004
+IN 3 4 IN

Figure 6. ADA4807-1 Pin Configuration

Table 7. ADA4807-1 Pin Function Descriptions

Pin No. Mnemonic Description
1 VOUT Output
2 VS Negative Supply
3 +IN Noninverting Input
4 IN Inverting Input
5 DISABLE Active Low Power-Down
6 +VS Positive Supply

Rev. B | Page 10 of 33
Data Sheet ADA4807-1/ADA4807-2/ADA4807-4

VOUT1 1 10 +VS
IN1 2 9 VOUT2
3 8 IN2 VOUT1 1 8 +VS
+IN1
VS 4 7 +IN2 IN1 2 7 VOUT2
DISABLE1 5 6 DISABLE2 +IN1 3 6 IN2

12611-061
NOTES VS 4 5 +IN2
1. THE EXPOSED PAD CAN BE CONNECTED TO

12611-060
GROUND OR POWER PLANES, OR IT CAN
BE LEFT FLOATING.

Figure 7. ADA4807-2 10-Lead LFCSP Pin Configuration Figure 8. ADA4807-2 8-Lead MSOP Pin Configuration

Table 8. ADA4807-2 Pin Function Descriptions

Pin No.
10-Lead LFCSP 8-Lead MSOP Mnemonic Description
1 1 VOUT1 Output 1.
2 2 IN1 Inverting Input 1.
3 3 +IN1 Noninverting Input 1.
4 4 VS Negative Supply.
5 Not applicable DISABLE1 Active Low Power-Down 1.
6 Not applicable DISABLE2 Active Low Power-Down 2.
7 5 +IN2 Noninverting Input 2.
8 6 IN2 Inverting Input 2.
9 7 VOUT2 Output 2.
10 8 +VS Positive Supply.
Not applicable EPAD Exposed Pad. For the 10-Lead LFCSP, the exposed pad can be connected to ground
or power planes, or it can be left floating.

Rev. B | Page 11 of 33
ADA4807-1/ADA4807-2/ADA4807-4 Data Sheet

VOUT1 1 14 VOUT4
IN1 2 13 IN4
+IN1 3 12 +IN4

+VS 4 ADA4807-4 11 VS
+IN2 5 10 +IN3

IN2 6 9 IN3

12611-110
VOUT2 7 8 VOUT3

Figure 9. ADA4807-4 Pin Configuration

Table 9. ADA4807-4 Pin Function Descriptions

Pin No. Mnemonic Description
1 VOUT1 Output 1
2 IN1 Inverting Input 1
3 +IN1 Noninverting Input 1
4 +VS Positive Supply
5 +IN2 Noninverting Input 2
6 IN2 Inverting Input 2
7 VOUT2 Output 2
8 VOUT3 Output 3
9 IN3 Inverting Input 3
10 +IN3 Noninverting Input 3
11 VS Negative Supply
12 +IN4 Noninverting Input 4
13 IN4 Inverting Input 4
14 VOUT4 Output 4

Rev. B | Page 12 of 33
Data Sheet ADA4807-1/ADA4807-2/ADA4807-4

TYPICAL PERFORMANCE CHARACTERISTICS

FREQUENCY RESPONSE
27 6
VS = 2.5V VS RANGE = 2.5V TO 5V
24 RLOAD = 1k G = +1 200mV p-p
G = +10 3 R
21 VOUT = 20mV p-p LOAD = 1k
18
0
15 G = +5 20mV p-p
CLOSED-LOOP GAIN (dB)

CLOSED-LOOP GAIN (dB)

12 3
9 G = +2
6 6
3
9 2V p-p
0 G = +1
3 12
G = 1
6
9 15
12
18
15
18 21
21
24 24

12611-006

12611-009
0.1 1 10 100 1000 0.1 1 10 100 1000
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 10. Small Signal Frequency Response for Various Gains, Figure 13. Frequency Response for Various Output Amplitudes, G = +1
RF = 499
6 6
VOUT = 20mV p-p VOUT = 2V p-p 1.5V
G = +1 3 G = +1
3 RLOAD = 1k RLOAD = 1k
0
0
3
CLOSED-LOOP GAIN (dB)
CLOSED-LOOP GAIN (dB)

5.0V
3 6
9
6
12
9
15

12 18
1.5V 5.0V
21
15
24 2.5V
18
27
2.5V
21 30

12611-010
12611-007

0.1 1 10 100 1000 0.1 1 10 100 1000

FREQUENCY (MHz) FREQUENCY (MHz)

Figure 11. Small Signal Frequency Response for Various Supplies Figure 14. Large Signal Frequency Response for Various Supplies

6 6
40C
+25C 3
3 +85C
+125C 0
0
3
CLOSED-LOOP GAIN (dB)

CLOSED-LOOP GAIN (dB)

3
6
6 9

9 12
40C
15 +125C
12
18
15 +25C
21
18
VS RANGE = 1.5V TO 5V 24 VS RANGE = 2.5V TO 5V
G = +1 G = +1
21 VOUT = 20mV p-p 27 VOUT = 2V p-p
RLOAD = 1k RLOAD = 1k
24 30
12611-008

12611-011

0.1 1 10 100 1000 0.1 1 10 100 1000

FREQUENCY (MHz) FREQUENCY (MHz)

Figure 12. Small Signal Frequency Response for Various Temperatures Figure 15. Large Signal Frequency Response for Various Temperatures

Rev. B | Page 13 of 33
ADA4807-1/ADA4807-2/ADA4807-4 Data Sheet
6 6
VS = 2.5V VS RANGE = 2.5V TO 5V
3 VOUT = 20mV p-p 3 VOUT = 2V p-p
G = +1 G = +1
0
0 1k
3

CLOSED-LOOP GAIN (dB)

CLOSED-LOOP GAIN (dB)

3
6
1k
6 9

9 12
100 100
12 15
18
15
21
18
24
21 27

24 30

12611-015
12611-012
0.1 1 10 100 1000 0.1 1 10 100 1000
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 16. Small Signal Frequency Response for Various Resistive Loads Figure 19. Large Signal Frequency Response for Various Resistive Loads

12 0.6
VS = 2.5V G = +1
9 G = +1 0.5 RLOAD = 1k

6 VOUT = 20mV p-p 0.4

RLOAD = 1k
3 0.3 VS RANGE = 1.5V TO 5V
CLOSED-LOOP GAIN (dB)
CLOSED-LOOP GAIN (dB)

VOUT = 20mV p-p

0 0.2

3 0.1
0pF
6 0

9 0.1
5pF
12 0.2

15 0.3 VS RANGE = 2.5V TO 5V

10pF VOUT = 2V p-p
18 0.4
15pF
21 0.5

24 0.6

12611-221
12611-050

0.1 1 10 100 1000 0.1 1 10 100

FREQUENCY (MHz) FREQUENCY (MHz)

Figure 17. Small Signal Frequency Response for Various Capacitive Loads Figure 20. 0.1 dB Flatness Frequency Response for Various Output Amplitudes

6 6
VS = 2.5V G=2 Vs = 2.5V, 5V
G = +1 3 RF = 499 VOUT = 200mV p-p
3 VOUT = 20mV p-p RLOAD = 1k
RLOAD = 1k VCM = 0V
0 Vs = 2.5V, 5V
0 VOUT = 20mV p-p
CLOSED-LOOP GAIN (dB)

NORMALIZED GAIN (dB)

3
3
6
6 VCM = +VS 0.5V
9
9
12
12
15 Vs = 2.5V, 5V
15 VOUT = 2V p-p
18

18 21 Vs = 5V
VOUT = 4V p-p
21 24
12611-013

12611-121

0.1 1 10 100 1000 0.1 1 10 100 1000

FREQUENCY (MHz) FREQUENCY (MHz)

Figure 18. Small Signal Frequency Response for Figure 21. Frequency Response for Various Output Amplitudes, G = +2
Various Input Common-Mode Voltages (VCM)

Rev. B | Page 14 of 33
Data Sheet ADA4807-1/ADA4807-2/ADA4807-4
FREQUENCY AND SUPPLY CURRENT
20 40
VS = 2.5V ON VS = 2.5V
G = +1 DISABLE = +VS VCM = 0dBm
0 50

60
20
OFF ISOLATION (dB)

70
40

CMRR (dB)
80
60
90
OFF
80 DISABLE = VS
100
100
110

120
120

140 130

12611-017

12611-020
0.01 0.1 1 10 100 1000 0.001 0.01 0.1 1 10 100
FREQUENCY (MHz) FREQUENCY (MHz)
Figure 22. Off Isolation vs. Frequency Figure 25. CMRR vs. Frequency

120 160 30
VS = 2.5V VS = 5V
VS = 16dBm
100 140 40

80 120 50
PSRR
OPEN-LOOP GAIN (dB)

PHASE (Degrees)

60
60 100 PSRR (dB)

70
40 80 +PSRR
80
20 60
90
0 40
100

20 20
110

40 0 120
12611-018

12611-226
0.001 0.01 0.1 1 10 100 1000 0.001 0.01 0.1 1 10 100
FREQUENCY (MHz) FREQUENCY (MHz)
Figure 23. Open-Loop Gain and Phase vs. Frequency Figure 26. PSRR vs. Frequency

1.6 2.5
DISABLE = VS
1.4 2.0
QUIESCENT SUPPLY CURRENT (mA)

+IS
DISABLE SUPPLY CURRENT (A)

1.2 VS = 5.0V 1.5

1.0
1.0

0.5
0.8 VS = 1.5V
VS = 2.5V 0
0.6
0.5
0.4
1.0
IS
0.2
1.5

0 2.0
12611-019

40 25 10 5 20 35 50 65 80 95 110 125
12611-022

0 1 2 3 4 5 6
TEMPERATURE (C) POWER SUPPLY, VS (V)

Figure 24. Quiescent Supply Current vs. Temperature Figure 27. DISABLE Supply Current vs. Power Supply, VS

Rev. B | Page 15 of 33
ADA4807-1/ADA4807-2/ADA4807-4 Data Sheet
DC AND INPUT COMMON-MODE PERFORMANCE
400 60
NPN PNP VS = 2.5V
VS = 5V VS = 5V 40C TO +125C
350 VCM = +VS 0.5V VCM = 0V COUNT = 361 AMPLIFIERS
450 UNITS 450 UNITS 50 x = 0.7V/C
x = 32.7V x = 1.5V = 0.5V/C
300 = 109.4V = 17.9V

NUMBER OF AMPLIFIERS
NUMBERING UNITS

40
250

200 30

150
20

100
10
50

0 0

12611-122

12611-031
2.8 2.2 1.6 1.0 0.4 0.2 0.8 1.4 2.0 2.6 3.2 3.8
600 400 200 0 200 400 600
INPUT REFERRED OFFSET VOLTAGE (V) INPUT OFFSET VOLTAGE DRIFT (V/C)

Figure 28. Input Referred Offset Voltage Distribution for the ADA4807-1 and Figure 31. Input Referred Offset Voltage Drift Distribution, VCM = 0 V
ADA4807-2

90
NPN PNP VS = 2.5V
300 VS = 5V VS = 5V 40C TO +125C
VCM = +VS 0.5V VCM = 0V 80 COUNT = 283 AMPLIFIERS
450 UNITS 450 UNITS x = 30pA/C
250 x = 1.18nA x = 1.58nA 70 = 35pA/C
= 22.59nA = 6.62nA NUMBER OF AMPLIFIERS
NUMBERING UNITS

60
200
50

150 40

30
100
20
50
10

0 0
12611-123

12611-032
150 100 50 0 50 100 150 200 140 80 20 40 100 160 220 280
INPUT OFFSET CURRENT (nA) INPUT OFFSET CURRENT DRIFT (pA/C)

Figure 29. Input Offset Current Distribution Figure 32. Input Offset Current Drift Distribution, VCM = 0 V

1.0 40
VS = 5.0V VS = 5.0V
10 UNITS 10 UNITS
30
0.5
INPUT OFFSET CURRENT (nA)

20
INPUT BIAS CURRENT (A)

0
10

0.5 0

10
1.0
20

1.5
30

2.0 40
12611-126

5.2 3.9 2.6 1.3 0 1.3 2.6 3.9 5.2

12611-124

5.2 3.9 2.6 1.3 0 1.3 2.6 3.9 5.2

INPUT COMMON-MODE VOLTAGE (V) INPUT COMMON-MODE VOLTAGE (V)

Figure 30. Input Bias Current vs. Input Common-Mode Voltage Figure 33. Input Offset Current vs. Input Common-Mode Voltage

Rev. B | Page 16 of 33
Data Sheet ADA4807-1/ADA4807-2/ADA4807-4
300 10 25
VS = 5V OIL BATH TEMPERATURE

CHANGING IN INPUT OFFSET VOLTAGE (V)

10 UNITS 9 24
INPUT REFERRED OFFSET VOLTAGE (V)

200 8 23
7 22
6 21

TEMPERATURE (C)
100
5 20
4 19
0 3 18
2 17
1 16
100
0 15
1 14
200
2 13
3 VS = 2.5V 12
8 UNITS, SOLDERED TO PCB
300 4 11

12611-234
12611-125
5.2 3.9 2.6 1.3 0 1.3 2.6 3.9 5.2 0 100 200 300 400 500 600
INPUT COMMON-MODE VOLTAGE (V) TIME (Hours)

Figure 34. Input Referred Offset Voltage vs. Input Common-Mode Voltage Figure 35. Long-Term Input Offset Voltage (VOS) Drift

Rev. B | Page 17 of 33
ADA4807-1/ADA4807-2/ADA4807-4 Data Sheet
SLEW, TRANSIENT, SETTLING TIME, AND CROSSTALK
280 1.5
G = +1 G = +1
RLOAD = 1k VS = 5V RLOAD = 1k
260 FALLING EDGE
VOUT = 5V p-p
1.0
240
2.5V

OUTPUT VOLTAGE (V)

RISING EDGE
SLEW RATE (V/s)

220 0.5

200
0
180 FALLING EDGE
VS = 2.5V
VOUT = 2V p-p
160 0.5 1.5V
RISING EDGE 5V
140
1.0
120

100 1.5

12611-025
12611-023
40 25 10 5 20 35 50 65 80 95 110 125 0 100 200 300 400 500 600 700 800 900
TEMPERATURE (C) TIME (ns)

Figure 36. Slew Rate vs. Temperature Figure 38. Large Signal Transient Response for Various Supplies

15 0.5

0.4

OUTPUTVOLTAGE(%ofFinalValue)
10
0.3
VS =2.5V
OUTPUT VOLTAGE (mV)

0.2 OUTPUTSTEP=2V p-p

5
0.1

0 0

0.1
5
0.2 VS =5V
OUTPUTSTEP=5V p-p
0.3
10
G = +1
RLOAD = 1k 0.4
VS RANGE = 1.5V TO 5V
15 0.5

12611-238
12611-024

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 20 40 60 80 90

TIME (s) TIME (ns)

Figure 37. Small Signal Transient Response for Various Supplies Figure 39. Settling Time to 0.1%

Rev. B | Page 18 of 33
Data Sheet ADA4807-1/ADA4807-2/ADA4807-4
15 0
VS = 2.5V VS = 2.5V
G = +1 VOUT2, VOUT3, VOUT4 = 1V p-p
20 G = +1
10 RLOAD = 1k
OUTPUT VOLTAGE (mV)

40
5

CROSSTALK (dB)
0pF
5pF 60
0 10pF VOUT1
15pF
80

5
100

10
120

15 140

12611-027

12611-241
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 100 1k 10k 100k 1M 10M 100M 1G
TIME (s) FREQUENCY (Hz)

Figure 40. Small Signal Transient Response for Various Capacitive Loads Figure 42. ADA4807-4 All Hostile Crosstalk

0
VS = 2.5V
VOUT = 2V p-p
20 DISABLE = 2.5V

40
CROSSTALK (dB)

60

80

100 DRIVING AMP 1

120

140 DRIVING AMP 2

160
12611-036

0.0001 0.001 0.01 0.1 1 10 100 1000

FREQUENCY (MHz)

Figure 41. ADA4807-2 Crosstalk vs. Frequency

Rev. B | Page 19 of 33
ADA4807-1/ADA4807-2/ADA4807-4 Data Sheet
DISTORTION AND NOISE
20 0
G = +1 VS = 1.5V G = +1
RLOAD = 1k 10 VS = 2.5V RLOAD = 1k
40 VOUT = 2V p-p 20 VS = 5V VOUT = 2V p-p
VS = 1.5V, HD2 30 HD2
HARMONIC DISTORTION (dBc)

HARMONIC DISTORTION (dBc)

40 HD3
60
VS = 1.5V, HD3 50
80 60
70
100 80
VS = 5V, HD2 90
120 VS = 5V, HD3 100
110
140 120
130
160 140
VS = 2.5V, HD2 150
VS = 2.5V, HD3
180 160

12611-127
1 10 100 1000 10000 170

12611-145
0.001 0.01 0.1 1 10
FREQUENCY (kHz)
FREQUENCY (MHz)
Figure 43. ADA4807-1 Harmonic Distortion vs. Frequency for Various Supplies
Figure 46. ADA4807-2/ADA4807-4 Harmonic Distortion vs. Frequency for
Various Supplies
0
VS = 2.5V 20
VOUT = 2V p-p G = +1
20 RLOAD = 1k VOUT = 2V p-p
40 VS = 2.5V
HARMONIC DISTORTION (dBc)

40 HARMONIC DISTORTION (dBc)

60 RLOAD = 100
60
G = +5, HD2 HD2
80 80
RLOAD = 1k
G = +2, HD2 HD2
100 100
G = +1, HD2
RLOAD = 1k
120 120 HD3
G = +5, HD3
140 RLOAD = 100
140
G = +2, HD3 HD3
160
G = +1, HD3 160
180
12611-028

1 10 100 1000 10000 180

12611-030
1 10 100 1000 10000
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 44. ADA4807-1 Harmonic Distortion vs. Frequency for Various Gains Figure 47. ADA4807-1 Harmonic Distortion vs. Frequency for Various
Resistive Loads
40
VS = 2.5V 0
G=+1
50 G = +1 10 VOUT = 2V p-p
RLOAD = 1k RLOAD = 1k
TOTAL HARMONIC DISTORTION (dB)

60 20 f = 100kHz
HARMONIC DISTORTION (dBc)

30 VS = 3V VS = 5V VS = 10V
70
f = 1MHz 40
80
50
90 60 HD2
100 70 HD2 HD2
f = 100kHz HD3
80
110 HD3
90
120 100
f = 1kHz
130 110
HD3
140 120
130
150
12611-245

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 140
12611-037

0 1 2 3 4 5 6 7 8 9 10
VOUT (V p-p)
INPUT COMMON-MODE VOLTAGE (V)
Figure 45. Total Harmonic Distortion vs. Output Voltage (VOUT) Figure 48. Harmonic Distortion vs. Input Common-Mode Voltage

Rev. B | Page 20 of 33
Data Sheet ADA4807-1/ADA4807-2/ADA4807-4
6 12
VS = 2.5V VS = 5V
G = +2 G = +2
RF = 499 RF = 499
5 RLOAD = 1k 10 RLOAD = 1k
OUTPUT VOLTAGE (V p-p)

OUTPUT VOLTAGE (V p-p)

4 8

3 6

2 4
THD = 80dB THD = 80dB
THD = 90dB THD = 90dB
THD = 100dB THD = 100dB
1 2
ADA4807-1, ADA4807-1,
ADA4807-2 ADA4807-2
ADA4807-4 ADA4807-4
0 0

12611-248

12611-250
1 10 100 1000 1 10 100 1000
FREQUENCY (kHz) FREQUENCY (kHz)

Figure 49. Output Voltage vs. Frequency for VS = 2.5 V Figure 51. Output Voltage vs. Frequency for VS = 5 V

1
VS = 2.5V
G = +1
f = 1kHz
TOTAL HARMONIC DISTORTION (%)

0.1

0.01

0.001
16

0.0001
32
600

0.00001
12611-132

0.001 0.01 0.1 1

OUTPUT VOLTAGE (V rms)

Figure 50. Total Harmonic Distortion vs. Output Voltage for Various
Resistive Loads

Rev. B | Page 21 of 33
ADA4807-1/ADA4807-2/ADA4807-4 Data Sheet
OUTPUT CHARACTERISTICS
100 100 100 100
VS RANGE = 1.5V TO 5V VS RANGE = 1.5V TO 5V
PNP ACTIVE NPN ACTIVE
INPUT VOLTAGE NOISE (nV/Hz)

INPUT VOLTAGE NOISE (nV/Hz)

CURRENT NOISE (pA/Hz)

CURRENT NOISE (pA/Hz)

10 10 10 10
VOLTAGE NOISE

VOLTAGE NOISE

1 CURRENT NOISE 1 1 1
CURRENT NOISE

0.1 0.1 0.1 0.1

12611-136

12611-134
1 10 100 1k 10k 100k 1M 10M 100M 1 10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 52. Input Voltage Noise and Current Noise vs. Frequency, Figure 55. Input Voltage Noise and Current Noise vs. Frequency,
VCM = 0 V VCM = +VS 0.5 V
POSITIVE RAIL OUTPUT SATURATION VOLTAGE (V)

NEGATIVE RAIL OUTPUT SATURATION VOLTAGE (V)

1.8 1.8
VS = 2.5V VS = 2.5V
G = +1 G = +1
1.6 1.6
+125C
1.4 1.4
+85C
+25C +25C
1.2 1.2
+85C
(+VS VOUT)

+125C
(VS + VOUT)

1.0 1.0

0.8 0.8
40C
0.6 0.6

0.4 0.4
40C
0.2 0.2

0 0
12611-040

12611-043
0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100
LOAD CURRENT (mA) LOAD CURRENT (mA)

Figure 53. Positive Rail Output Saturation Voltage (+VS VOUT) vs. Figure 56. Negative Rail Output Saturation Voltage (VS + VOUT) vs.
Load Current for Various Temperatures Load Current for Various Temperatures

1000 1000
VS = 2.5V VS = 2.5V
DISABLE = +VS DISABLE = VS
DISABLED OUTPUT IMPEDANCE (k)

100
ENABLED OUTPUT IMPEDANCE ()

100

10
10

1
0.1

0.1
0.01

0.01 0.001
12611-144
12611-141

0.1 1 10 100 1000 0.1 1 10 100 1000

FREQUENCY (MHz) FREQUENCY (MHz)

Figure 54. Enabled Output Impedance vs. Frequency Figure 57. Disabled Output Impedance vs. Frequency

Rev. B | Page 22 of 33
Data Sheet ADA4807-1/ADA4807-2/ADA4807-4
OVERDRIVE RECOVERY AND TURN ON/TURN OFF TIMES
3 1.5 3
VIN VOUT VS = 2.5V VIN VS = 2.5V
G = +1 VOUT G = +2
RLOAD = 1k RLOAD = 1k
2 1.0 2

OUTPUT VOLTAGE (V)

INPUT VOLTAGE (V)
1 0.5 1
VOLTAGE (V)

0 0 0

1 0.5 1

2 1.0 2

3 1.5 3

12611-041

12611-044
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
TIME (s) TIME (s)

Figure 58. Input Overdrive Recovery Figure 60. Output Overdrive Recovery

1800 400
G = +1 G = +1
RLOAD = 1k RLOAD = 1k
1600
DISABLE = VS TO +VS DISABLE = +VS TO VS
350 VS = 1.5V
1400
TURN ON TIME (ns)

1200
VS = 5.0V TURN OFF TIME (ns) 300 VS = 5.0V
1000 VS = 2.5V
250
800

600 200
VS = 2.5V

400
150
200 VS = 1.5V

0 100
12611-033

40 25 10 5 20 35 50 65 80 95 110 125

12611-034
40 25 10 5 20 35 50 65 80 95 110 125
TEMPERATURE (C) TEMPERATURE (C)
Figure 59. Turn On Time vs. Temperature and Supply
Figure 61. Turn Off Time vs. Temperature and Supply

Rev. B | Page 23 of 33
ADA4807-1/ADA4807-2/ADA4807-4 Data Sheet

THEORY OF OPERATION
The ADA4807-1/ADA4807-2/ADA4807-4 have a rail-to-rail The rail-to-rail input stage is useful in many different applications.
input stage with an input range that goes 200 mV beyond either Although the precision is reduced from input to input, many
rail. A PNP transistor input pair is active for a majority of the applications can tolerate this loss when the alternative is no
input range, while an NPN transistor input pair is active for the functionality at all. The positive rail input range is indispensable
common-mode voltages within 1.3 V of the positive rail. The for servo loops with a high-side input range
ADA4807-1/ADA4807-2/ADA4807-4 are fabricated using the The ADA4807-1/ADA4807-2/ADA4807-4 input operates 200 mV
Analog Devices, Inc., third generation, extra fast complementary beyond either rail. Internal protection circuitry prevents the output
bipolar (XFCB) process resulting in exceptionally good distortion, from phase inverting when the input range is exceeded. When
noise, slew rate, and settling characteristics for 1 mA devices. the input exceeds a diode beyond either rail, internal electrostatic
Given traditional rail-to-rail input architecture performance, the discharge (ESD) protection diodes source or sink current through
input 1/f noise is surprisingly low, and the current noise is only the input.
0.7 pA/Hz for a 3 nV/Hz voltage noise. Typical high slew rate
devices suffer from increased current noise because of input pair I1 Q42 Q51 I2
degeneration and higher input stage current. The ADA4807-1/ Q47
ADA4807-2/ADA4807-4 exceed current benchmark parameters
DIFFERENTIAL
given the performance of the XFCB process. DRIVE Q37 Q38
FROM
INPUT STAGE Q68
The multistage design of the ADA4807-1/ADA4807-2/ C9

+
Q20 R29
ADA4807-4 has excellent precision specifications, such as input Q27
Q21
drift, offset, open-loop gain, CMRR, and PSRR. Typical harmonic VOUT
Q43 Q48 C5
distortion numbers fall in the range of 130 dBc for a 10 kHz

+
fundamental (see the Distortion and Noise section). This level of
Q49
performance makes the ADA4807-1/ADA4807-2/ADA4807-4 the I4 I5
best choices when driving 18-bit precision converters.

12611-052
Q50 Q44

The ADA4807-1/ADA4807-2 are optimized for a low shutdown

current (4 A maximum), in the order of a few microamperes. In Figure 62. Differential Drive from Input Stage
power sensitive applications, this can eliminate the use of a power
FET and enable time interleaved power saving operation schemes.

+VS

R1 R2
Q9 I2
1.3V

R5 VIN Q3 Q2

Q5 Q8 Q7
VBIAS1
VIP Q13 Q17
OUTPUT STAGE,
COMMON-MODE
FEEDBACK
Q14 Q11
VBIAS2

I1 R3 R4
Q18
12611-051

5A Q4
VS

Figure 63. Simplified Schematic

Rev. B | Page 24 of 33
Data Sheet ADA4807-1/ADA4807-2/ADA4807-4
DISABLE CIRCUITRY heating. If large differential voltages must be sustained across the
input terminals, it is recommended that the current through the
When the DISABLE pin is an option, a pull-up resistor is required
input clamps be limited to less than 10 mA. Series input resistors
if the logic leakage currents exceed 300 nA. For a 10 V supply,
sized appropriately for the expected differential overvoltage
pulling the DISABLE pin to below 6.3 V turns the ADA4807-1/
provide the needed protection.
ADA4807-2 off, which reduces the supply current to 2.4 A.
+VS
Conversely, pulling the DISABLE pin voltage to above 6.6 V
enables the ADA4807-1/ADA4807-2 with a quiescent current of BIAS

1 mA. When the ADA4807-1/ADA4807-2 device is disabled, its

ESD ESD
output enters a high impedance state. Figure 64 and Table 10
+INx INx
show the DISABLE functionality over the complete supply range. ESD ESD
4.0
3.8 VS
TRIGGER VOLTAGE BELOW +VS (V)

3.6
3.4
TO THE REST OF THE AMPLIFIER
3.2 NOTES

12611-054
1. THE INx PINS ARE IN ON THE ADA4807-1,
3.0 IN1 AND IN2 ON THE ADA4807-2,
2.8 AND IN1 TO IN4 ON THE ADA4807-4.

2.6 Figure 65. Input Stage and Protection Diodes

2.4
2.2
NOISE CONSIDERATIONS
2.0 Figure 66 illustrates the primary noise contributors for the typical
1.8
VTH gain configurations. The total output noise (VN_OUT) is the root
1.6 VON = VTH +150mV
VOFF = VTH 150mV
sum square of all the noise contributions.
1.4 VN _ R F = 4kT RF
RF
12611-152

3 4 5 6 7 8 9 10
POWER SUPPLY, VS (V)
RG ven
VN _ RG = 4kT RG
Figure 64. DISABLE Trigger Voltage + vout_en
ien

Table 10. Threshold Voltages for Disabled and Enabled Modes RS

VN _ RS = 4kT RS
Mode +3 V +5 V +10 V 5 V +7 V/2 V

12611-055
iep
Enabled 1.35 V 1.6 V 6.6 V 1.6 V 3.6 V
Disabled 1.05 V 1.3 V 6.3 V 1.3 V 3.3 V Figure 66. Noise Sources in Typical Gain Configurations

The output impedance decreases as the frequency increases. When Source resistance noise, amplifier input voltage noise, and the
disabled, a forward isolation of 120 dB is achieved at 100 kHz (see voltage noise from the amplifier input current noise (IN+ RS)
Figure 22). ESD clamps protect the DISABLE pin, as shown in are all subject to the noise gain term (1 + RF/RG).
Figure 65. Voltages beyond the power supplies cause these diodes Calculate the output noise spectral density using the following
to conduct. To avoid excessive current in the ESD diodes, ensure equation:
that the voltage to the DISABLE pin is not 0.7 V greater than the 2 2
R R
positive supply or that it is not 0.7 V less than the negative supply. VN _ OUT = 4kTRF + 1 + F [ ]
4kTRs + I N + 2 RS 2 + VN 2 + F 4kTRG + I N 2 RF 2
R
If an overvoltage condition is expected, limit the input current to RG G
less than 10 mA with a series resistor. where:
INPUT PROTECTION k is Boltzmanns constant.
The ADA4807-1/ADA4807-2/ADA4807-4 are fully protected T is the absolute temperature in degrees Kelvin.
from ESD events, withstanding human body model ESD events RF and RG are the feedback network resistances, as shown in
of 3 kV and charged device model events of 1.25 kV with no Figure 66.
measured performance degradation. The precision input is RS is the source resistance, as shown in Figure 66.
protected with an ESD network between the power supplies and IN+ and IN represent the amplifier input current noise spectral
diode clamps across the input device pair, as shown in Figure 65. density in pA/Hz.
VN is the amplifier input voltage noise spectral density in nV/Hz.
For differential voltages above approximately 1.2 V at room
temperature and 0.8 V at 125C, the diode clamps begin to
conduct. Too much current can cause damage due to excessive

Rev. B | Page 25 of 33
ADA4807-1/ADA4807-2/ADA4807-4 Data Sheet

APPLICATIONS INFORMATION
CAPACITIVE LOAD DRIVE LOW NOISE FET OPERATIONAL AMPLIFIER
Figure 67 shows the schematic for driving large capacitive loads, and Low noise amplifiers for photodiode, piezoelectric, and other
Figure 68 shows the frequency response for a gain of +2. Note that instrumentation applications typically call for circuit parameters
the bandwidth decreases with larger capacitive loads (see Figure 68). such as extremely high input impedance, low 1/f noise, or sub-
Figure 69 shows the required series resistor (RSERIES) when picoamp bias currents that can be met only with a discrete
limiting the peaking to 3 dB for a range of load capacitors amplifier design.
(CLOAD) at a gain of +2. From Figure 69, no series resistors are The discrete amplifier shown in Figure 70 uses a high-speed op
necessary to maintain stability for larger capacitors. amp preceded by a differential amplifier stage. This discrete config-
RF uration is implemented with dual matched JFETs, which provide
high input impedance and some initial gain, reducing the noise
RG
VOUT RSERIES VLOAD and precision specifications of the second stage. The low current
VIN RLOAD CLOAD
12611-056
consumption of the ADA4807-1/ADA4807-2/ADA4807-4, in
RT
49.9 addition to their precision and low noise characteristics, results
in a composite design with 7 mA of total supply current,
Figure 67. Schematic for Driving Large Capacitive Loads 1.5 nV/Hz noise at 1 kHz, and 4 nV/Hz noise at 10 Hz.
6
The unbalanced output impedance of the FETs is negated by
the use of an inverting amplifier cascode. The ADA4807-1/
NORMALIZED CLOSED-LOOP GAIN (dB)

3
ADA4807-2/ADA4807-4 are ideally suited for the cascode due
15pF, 100
0
47pF, 82.5 to their rail-to-rail input structure, which results in excellent
3 470pF, 20 overload behavior of the overall discrete amplifier. Using this
1nF, 10.5 cascode structure, the CMRR is greater than 100 dB.
6 10nF, 1.69
100nF, 0.5 A high output impedance current source is also needed to
9 maintain the CMRR of the discrete amplifier. An ADR510
12
maintains a precise current over the supply voltage, and the low
VS = 5V collector capacitance of the PMP4201 results in a balanced and
RLOAD = 1k
15
G = +2 predictable slew rate behavior. This is shown in Figure 71 with a
18
VOUT = 70mV p-p
0.4 V p-p input and a 4 V p-p output with a gain of 10. Figure 72
12611-155

0.1 1 10 100 1000

shows output referred total harmonic distortion plus noise
FREQUENCY (MHz)
(THD + N) for a gain of 10.
Figure 68. Frequency Response for Driving Large Capacitive Loads,
RF = RG = 249
100

90

80

70
RSERIES ()

60

50

40

30

20

10
12611-057

0
0.001 0.01 0.1 1 10 100
CLOAD (nF)

Figure 69. Required Series Resistor (RSERIES) vs. Capacitive Load (CLOAD)
at 3 dB Peaking

Rev. B | Page 26 of 33
Data Sheet ADA4807-1/ADA4807-2/ADA4807-4
R0 C7
100 27pF
Rb VOS
VOS 100 TRIM
C0 R1 R13
TRIM 20pF 10
R12 100 +5V
100
VOUT
+
5V
ADA4807-1/
ADA4807-2/
+5V 5V ADA4807-4
R4 C9
ADA4807-1/ + 2pF
5k
V ADA4807-2/ V+
ADA4807-4
1/2 LSK489 1/2 LSK489

+5V
R2 R3
100 1k
R6
5k

qn1 qn0
1/2 PMP4201 1/2 PMP4201

R7
ADR510 200

12611-068
5V

Figure 70. Low Noise FET Operational Amplifier Schematic

POWER MODE ADC DRIVER

One of the merits of a SAR ADC, such as the AD7980, is that its
1
power scales with the sampling rate. This power scaling makes
SAR ADCs very power efficient, especially when running at a
low sampling frequency. However, the ADC driver used with
the SAR ADC traditionally consumes constant power regardless
of the sampling frequency.
2
Figure 73 illustrates a method by which the quiescent power of
the ADC driver can be reduced by 95% while still maintaining
the input signal to the ADC. Both the ADA4807-1/ADA4807-2/
ADA4807-4 and the AD8603 are rail-to-rail input and output
12611-069

(RRIO) amplifiers and can operate on a single 5 V analog supply.

CH1 200mV CH2 1V M100ns A CH1 0V
Connecting the AD8603 in parallel with a sharing resistor allows
Figure 71. Pulse Response, G = 10, 4 V p-p Output
the ADA4807-1/ADA4807-2/ADA4807-4 to be powered down,
60
reducing the total supply current for the driver from 1 mA to
65
50 A. The sampling frequency of the AD7980 can then be
70 reduced to match the power consumption of the AD8603. With
75 the ADA4807-1/ADA4807-2/ADA4807-4 powered on, the SNR
DISTORTION (%)

80
and THD are 84.1 dB and 100.3 dB for a 3 V p-p, 1 kHz input
and a 4.096 V reference. The SNR and THD degrade to 81.4 dB
85
and 77.3 dB for the same input signal in the low power mode
90
when only the AD8603 is on.
95
One issue with this method is that the reference and reference
100
buffer power do not scale with the ADC or the driver. This
105 makes this configuration most useful in multichannel systems
110 where the reference can be reused across many inputs.
12611-071

100 1k 10k 20k

FREQUENCY (Hz)
Alternately, the reference buffer can be scaled in the same
fashion as the input driver; however, the reference itself must
Figure 72. 8 V p-p Output, THD + N for G = 10, RLOAD = 600
remain on in any of the modes.

Rev. B | Page 27 of 33
ADA4807-1/ADA4807-2/ADA4807-4 Data Sheet
5V 5V

ADA4807-1/
ADA4807-2/
ADA4807-4
ADR4540 +
C3 C2
C4 10F 0.1F
0.1F

LP MODE

5V
R10
ADA4807-1/ 22 REF
ADA4807-2/ IN+
ADA4807-4 AD7980
VIN + C1
R11 2.7F IN
49.9 GND

5V

AD8603

12611-070
+

Figure 73. Dual Power Mode ADC Driver

ADC DRIVING Figure 76 shows the ADA4807-1/ADA4807-2/ADA4807-4

The ADA4807-1/ADA4807-2/ADA4807-4 can be used in ADC configured to convert a single-ended to differential signal and
driving applications. Figure 74 is a simplified schematic of the drive an 18-bit ADC. This configuration results in an ENOB of
ADA4807-1/ADA4807-2/ADA4807-4 driving an 18-bit differential 15.3. The FFT is shown in Figure 77.
ADC, the AD7982, in a fully differential signal chain. This configu-
20
ration results in an effective number of bits (ENOB) of 15.7; results
are shown in Figure 75. VIN 2.7nF
ADA4807-1/ IN+
ADA4807-1/ ADA4807-2/ ADC
ADA4807-2/ ADA4807-4 1k
IN
ADA4807-4 1k
VIN+ 20 20
REF
2 2.7nF
2.7nF
ADA4807-1/

12611-276
IN+
ADC ADA4807-2/
IN
ADA4807-4
20 Figure 76. Schematic for Driving the AD7982 Differential Converter from a
Single-Ended Input Signal, +VS = +7 V, VS = 1 V
VIN 2.7nF
0
ADA4807-1/
12611-275

fs = 200kSPS
ADA4807-2/ fIN = 1kHz
20
ADA4807-4 SNR = 94.5dB
THD = 110.3dB
Figure 74. Schematic for Driving the AD7982, +VS = +7 V, VS = 1 V 40 SFDR = 111.1dB
SINAD = 94.4dB
0 60
AMPLITUDE (dB)

fs = 200kSPS
20 fIN = 1kHz
SNR = 96.6dB 80
THD = 111.5dB
40 SFDR = 112.3dB 100
SINAD = 96.5dB
60 120
AMPLITUDE (dB)

80 140

100 160

120 180
12611-077

0 2 4 6 8 10 12 14 16 18 20
140 FREQUENCY (kHz)

160 Figure 77. FFT for Driving a Single-Ended Input Signal into a Differential
Converter
180
12611-075

0 2 4 6 8 10 12 14 16 18 20
FREQUENCY (kHz)

Figure 75. FFT for Driving a Differential Converter, 0.5 dBFS

Rev. B | Page 28 of 33
Data Sheet ADA4807-1/ADA4807-2/ADA4807-4
ADC DRIVING WITH DYNAMIC POWER SCALING
In power sensitive applications, the ADA4807-1/ADA4807-2 CONV

can be switched on prior to the ADC turning on. Figure 78

shows the timing diagram for dynamically power scaling the
1
ADA4807-1/ADA4807-2 with the AD7982 configuration shown in
Figure 79. The falling edge of the DISABLE signal must align DISABLE

with the rising edge of the CONV signal of the ADC to obtain a
clean data acquisition. Figure 79 gives the FFT for driving a fully
differential signal chain with a 1.2 s on time as shown in Figure 78. 2

With this method, the ADA4807-1/ADA4807-2 quiescent current

(per amplifier) is reduced from 2 mA to 0.25 mA. Figure 81 gives

12611-078
the FFT for dynamically power scaling a single-ended input
CH1 2V CH2 2V M1s A CH1 2.56V
signal chain into a differential ADC with a 4 s on time as
Figure 80. Dynamic Power Scaling Timing Diagram for Driving a Single-
shown in Figure 80. This configuration results in a quiescent Ended Input Signal Chain into a Differential ADC (AD7982)
current reduction of 20%. 0
fs = 200kSPS
20
fIN = 1kHz
SNR = 94.7dB
CONV THD = 107.11dB
40 SFDR = 108.8dB
SINAD = 94.4dB
60

AMPLITUDE (dB)
1
80
DISABLE
100

120

2 140

160
12611-278

180

12611-080
0 2 4 6 8 10 12 14 16 18 20
CH1 2V CH2 2V M1s A CH1 2.56V
FREQUENCY (kHz)
Figure 78. Dynamic Power Scaling Timing Diagram for Driving a Fully
Differential Signal Chain into a Differential ADC (AD7982) Figure 81. FFT for Driving a Single-Ended to Differential Converter Using
Dynamic Power Scaling, 0.5 dBFS, On Time of 4 s, for the Schematic Shown in
0 Figure 76
fs = 200kSPS
20
fIN = 1kHz
SNR = 96.7dB
THD = 110.9dB
40 SFDR = 111.8dB
SINAD = 96.6dB
60
AMPLITUDE (dB)

80

100

120

140

160

180
12611-079

0 2 4 6 8 10 12 14 16 18 20
FREQUENCY (kHz)

Figure 79. FFT for Driving a Differential Converter using Dynamic Power Scaling,
0.5 dBFS, On Time of 1.2 s, for the Schematic Shown in Figure 74

Rev. B | Page 29 of 33
ADA4807-1/ADA4807-2/ADA4807-4
LAYOUT, GROUNDING, AND BYPASSING
The ADA4807-1/ADA4807-2/ADA4807-4 are high speed
devices. Realizing their superior performance requires attention
to the details of high speed printed circuit board (PCB) design.
The first requirement is to use a multilayer PCB with solid ground
and power planes that cover as much of the board area as possible.
Bypass each power supply pin directly to a nearby ground plane,
as close to the device as possible. Use 0.1 F high frequency
ceramic chip capacitors.
Provide low frequency bulk bypassing using 10 F tantalum
capacitors from each supply to ground.
Stray transmission line capacitance in combination with
package parasitics can potentially form a resonant circuit at
Rev. B | Page 30 of 33
Data Sheet
high frequencies, resulting in excessive gain peaking or possible
oscillation. Signal routing must be short and direct to avoid such
parasitic effects. Provide symmetrical layout for complementary
signals to maximize balanced performance.
Use radio frequency transmission lines to connect the driver
and receiver to the amplifier.
Minimize stray capacitance at the input and output pins by
clearing the underlying ground and low impedance planes
near these pins.
If the driver and receiver are more than one-eighth of the
wavelength from the amplifier, minimize the signal trace
widths. This nontransmission line configuration requires
clearing of the underlying and adjacent ground and low
impedance planes near the signal lines.
Data Sheet ADA4807-1/ADA4807-2/ADA4807-4

OUTLINE DIMENSIONS
2.20
2.00
1.80

1.35 6 5 4 2.40
1.25 2.10
1.15 1 2 3 1.80

0.65 BSC
1.30 BSC

1.00 0.40
1.10
0.90 0.10
0.80
0.70

0.46
SEATING 0.22
0.10 MAX 0.30 0.36
PLANE 0.08
COPLANARITY 0.15 0.26
0.10

072809-A
COMPLIANT TO JEDEC STANDARDS MO-203-AB

Figure 82. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-6)
Dimensions shown in millimeters

3.00
2.90
2.80

6 5 4 3.00
1.70
1.60 2.80
1.50 2.60
1 2 3

PIN 1
INDICATOR
0.95 BSC
1.90
BSC
1.30
1.15
0.90
1.45 MAX 0.20 MAX
0.95 MIN 0.08 MIN
0.55
0.15 MAX 10 0.45
0.05 MIN SEATING 4 0.60
0.50 MAX PLANE BSC 0.35
0.30 MIN 0
12-16-2008-A

COMPLIANT TO JEDEC STANDARDS MO-178-AB

Figure 83. 6-Lead Small Outline Transistor Package [SOT-23]

(RJ-6)
Dimensions shown in millimeters

Rev. B | Page 31 of 33
ADA4807-1/ADA4807-2/ADA4807-4 Data Sheet
3.20
3.00
2.80

8 5 5.15
3.20 4.90
3.00 4.65
2.80 1
4

PIN 1
IDENTIFIER

0.65 BSC

0.95 15 MAX
0.85 1.10 MAX
0.75
0.80
0.15 6 0.23
0.40 0.55
0.05 0 0.09 0.40
COPLANARITY 0.25

10-07-2009-B
0.10

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 84. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)
Dimensions shown in millimeters

2.48
2.38
3.10
2.23
3.00 SQ
2.90 0.50 BSC
6 10

PIN 1 INDEX EXPOSED 1.74

AREA PAD
1.64
0.50 1.49
0.40
0.30
5 1 0.20 MIN
TOP VIEW BOTTOM VIEW PIN 1
INDICATOR
(R 0.15)
0.80 FOR PROPER CONNECTION OF
0.75 0.05 MAX THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
0.70 0.02 NOM FUNCTION DESCRIPTIONS
COPLANARITY SECTION OF THIS DATA SHEET.
SEATING 0.08
0.30
02-05-2013-C

PLANE 0.25 0.20 REF

0.20

Figure 85. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]

3 mm 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters

Rev. B | Page 32 of 33
Data Sheet ADA4807-1/ADA4807-2/ADA4807-4
5.10
5.00
4.90

14 8

4.50
4.40 6.40
BSC
4.30
1
7

PIN 1

0.65 BSC
1.05
1.00 1.20
MAX 0.20
0.80 0.09 0.75
0.15 8 0.60
SEATING 0
0.05 0.30 PLANE 0.45
COPLANARITY 0.19
0.10

061908-A
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

Figure 86. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)
Dimensions shown in millimeters

ORDERING GUIDE
Package
Model1 Temperature Range Package Description Option Branding
ADA4807-1AKSZ-R2 40C to +125C 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 H3J
ADA4807-1AKSZ-R7 40C to +125C 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 H3J
ADA4807-1ARJZ-R2 40C to +125C 6-Lead Small Outline Transistor Package [SOT-23] RJ-6 H3J
ADA4807-1ARJZ-R7 40C to +125C 6-Lead Small Outline Transistor Package [SOT-23] RJ-6 H3J
ADA4807-2ACPZ-R2 40C to +125C 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] CP-10-9 H3S
ADA4807-2ACPZ-R7 40C to +125C 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] CP-10-9 H3S
ADA4807-2ARMZ 40C to +125C 8-Lead Mini Small Outline Package [MSOP] RM-8 H3S
ADA4807-2ARMZ-R7 40C to +125C 8-Lead Mini Small Outline Package [MSOP] RM-8 H3S
ADA4807-4ARUZ 40C to +125C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14
ADA4807-4ARUZ-R7 40C to +125C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14
ADA4807-1AKSZ-EBZ Evaluation Board for 6-Lead SC70
ADA4807-1ARJZ-EBZ Evaluation Board for 6-Lead SOT-23
ADA4807-2ACPZ-EBZ Evaluation Board for 10-Lead LFCSP_WD
ADA4807-2ARMZ-EBZ Evaluation Board for 8-Lead MSOP
ADA4807-4AURZ-EBZ Evaluation Board for 14-Lead TSSOP
1
Z = RoHS Compliant Part.

20142015 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D12611-0-9/15(B)

Rev. B | Page 33 of 33