BANGLADESH UNIVERSITY OF ENGINEERING AND TECHNOLOGY

EEE 6404
VLSI Technology and Device Modelling

Report writing on VLSI Technology

Selected paper:

A MOSFET Fabrication using a Maskless Lithography System in Clean-

Localized Environment of Minimal Fab
Sommawan Khumpuang, Member, IEEE and Shiro Hara
IEEE Transactions on Semiconductor Manufacturing (Volume: 28, Issue: 3, Aug. 2015)
10.1109/TSM.2015.2429572

Date of Submission: 24/08/2016

Submitted by,
Faysal Hakim
Student ID: 0416062232
Department: EEE

Submitted to, Dr.

Apratim Roy
Associate Professor
EEE, BUET
Abstract:
We compare the conventional fabrication process with a new and improvised fabrication
mechanism including minimal fab. The masked photolithography of the conventional process is
compared with a newly proposed maskless lithography technique. After brief analysis of both the
conventional and novel methods, we discuss the advantages and prospects of the maskless
photolithography system with facts and figures taken from the selected paper.
Conventional Fabrication Process and Masked Lithography:
In a conventional fabrication process, a wafer is initially processed from EGS. The cleaned and
prepared wafer is oxidized to have oxide layer over the substrate. Upon the oxide layer, photoresist
is coated, soft baked and then mask is aligned with respect to the wafer to expose UV light. The
mask is a glass plate having metal film or patterned emulsion on one side. It takes around 1-5 sec
in automated process and 35-40 sec by a manual operator to align the mask properly. When light
is exposed through the mask, the coated photoresist is either softened or hardened depending on
the type of photoresist. Then after hard baking, masked/unmasked portion is etched out and resist
removal takes place. After that, diffusion or ion implantation takes place to alter the doping profile
and thus introducing different section of the transistor (eg. source, drain, gate, metal contact etc).
The fabricated device is further (laser) annealed to improve its quality. All the processes are carried
out in a cleanroom with a very low dust particle count.
Building up and maintenance of a cleanroom of high quality (class-1~10) is both challenging and
costly. Also, the conventional process of transistor fabrication mentioned above takes up to several
days to weeks (in some cases). Moreover, mask production, especially in electron beam
lithography (EBL) is costly and difficult. All these disadvantages in conventional transistor
fabrication using masked lithography demands a rather direct exposure system eliminating the
need of mask and cleanroom if possible.
Minimal Fab Technology:

Minimal Fab is a totally new semiconductor production system to deal with production needs of
multiple kinds in small quantities and variable kinds in variable quantities. Helping to eliminate
the need for a clean room is a localized cleaning technology with a minimal shuttle, minimal
machine and wafer transfer system (PLAD). The main benefits of minimal system instead of a
conventional process chain are: processing a single wafer only with a 12.5 mm diameter,
eliminating the need of cleanroom and portability of the system. The minimal fab is a low cost
(1/1000 of conventional process) and easy to assemble machine. In this paper, the minimal fab
system is improvised for the new proposed technique of maskless lithography.

Minimal Hybrid Process and Maskless Lithography:

Other than the maskless lithography, all other steps of MOSFET fabrication in this paper have been
conventional techniques. In maskless lithography, initially the wafer has been cleaned by piranha
clean and RCA clean. Then photoresist has been spin coated in the wafer. These processes are all
conventional processes.

After cleaning and resist coating, without applying a mask, patterns have been formed in the wafer
surface using a DLP (Digital Light Processing) exposure. The mask image has been initially loaded
in a computer which is connected to a digital micro mirror device (DMD). Then UV light is made
incident in the mirror. This exposure is reflected by DMD to project UV light in the wafer. The
light is focused on to the wafer using a condensing lens. Using a digital imaging, a computational
bitmap is projected. The above stated configuration is illustrated in figure 1.The DLP exposure is
carried out four times to form the patterns of sources, drains, gate and contacts.

Figure 1: Schematic of a maskless exposure system using DMD installed in a minimal machine
with the dimension of W30cm, L45cm, and H144cm.

After the exposure, the wafer has been placed in developer where manufacturer provided
photoresist developer develops the pattern. The patterns being formed, polysilicon and
tetraetoxysilane (TEOS) have been formed on top of gate pattern and polysilicon using CVD
(Chemical Vapor Deposition) and PE-CVD (Plasma-Enhanced Chemical Vapor Deposition)
processes respectively. Consequently, source-drain formation and rapid thermal annealing (RTA)
are carried away. Later, layers have been etched and electrodes are formed. As for final step
sintering has been performed using gas annealing. Again these are all conventional process but
carried out in minimal fab. The fabrication design is shown in figure 2.

Figure 2: The designed n-channel MOSFET structure and the gate dimension
Advantages/Disadvantages of the proposed system:
The minimal fab eliminates the necessity of a cleanroom with its high quality of cleanness.
Facts from Table 1 (in results and discussion section) proves that the minimal fab is of
cleanroom quality in between class 3-10. Considering the cost of minimal fab and a class-
3~10 cleanroom, the improvised minimal fab in the paper can be considered as a great
alternative to the cleanrooms. The number of particles inside the wafer transfer system
(PLAD) is shown in figure 3. The cleanness of the system is also supported by the
transistors defect density (2.33x1010 cm-2) which at an acceptable level.

Figure 3: Particle densities inside the PLAD. (a) In step1, the PLAD is open to the outside and no
clean air is fed. The detected particle density is in ISO class 8. (b) In step2, the PLAD is close for
the outside with feeding it downstream. No particle above 0.08 m is detected for 110sec. this is
equivalent to ISO class 3. (c) In step3, no clean air is fed and the PLAD is open again to suck the
room air. The resultant ISO class becomes to be 8 again.
The proposed system in the paper employs the use of a high resolution lens to condense
the reflected light from the mirror to acquire a minimum spot size of 0.5 m x 0.5 m and
thus improve the overall system. The light intensity of the system is also corrected to reduce
the surface profile variations. The digital resolution of the system is 0.5 m, which is
acceptable compared to the cost associated.
The minimal hybrid system can fabricate a gate with minimum length of 1 m. So, a
limitation arises in case of smaller feature length.
A deterioration in alignment accuracy has been noted by the research group as a result of
multiple bitmap imaging and side etching which affects the consistency of wafers to wafers.
The proposed system is still in development stage, so not applicable for mass production.

Conclusion:
The maskless lithography technique in minimal fab is definitely a promising technique which is
still under development. The low cost and cleanness of the system indicates its possibility in
industry. If researchers overcome the limitation of m gate length and improve the resolution as
well as the alignment accuracy, then there is a high possibility of the proposed technique in the
paper to be implemented commercially in future.