03 Isa Addrmodes PDF

Department of Electrical and Computer Engineering
University of Waterloo
ECE 222
Digital Computers
Hiren Patel
Special thanks to Prof. Bill Bishop, Prof. Gord Agnew,

and Prof. Anwar Hasan. These slides heavily borrow
theirs.
NOTE:
Students enrolled in ECE 222 are permitted to print copies of

these lecture notes for their personal use in this course.
Department of Electrical and Computer Engineering
University of Waterloo
Instruction Sets and Addressing

Modes
Readings
HVZM6
2.12.14
ECE 222 (Patel, H.): ISAs and Addressing Modes 3

Memory Addressing
Memory systems do not allow instructions to directly address

a single bit in memory
Single bits of memory are not used frequently
If one did, then youd need as many unique addresses as bits
The range of addresses is known as the address space
The number of unique addressable locations in memory

depends upon the width of the address signal:
A 24 bit address generates an address space of 224 (16 777 216)
addressable locations
A 32 bit address generates an address space of 232 (4 294 967 296)
addressable locations

Byte Addressable Memory Systems
Memory systems are typically byte addressable
Instructions may refer to a particular byte or a particular word

in memory
Each byte has a unique address
Adjacent bytes are located in addresses that differ by 1
Adjacent words are located in addresses that differ by the number of
bytes in a word
For example, the first word in memory would be located at

address 0x0000 and the second word in memory would be
located at address 0x0004 if words consist of 4 bytes
Given a 24 bit address, a byte addressable memory system

supports 16 MiB of memory
NOTE:
16 MiB of memory is exactly 16 777 216 bytes.
SI Prefixes vs. Binary Prefixes
In 2005, IEEE adopted a set of binary prefixes to replace SI

prefixes in the labelling of storage devices
The binary prefixes were introduced to address the confusion over the
size of kilobytes, megabytes, and gigabytes
Prior to the adoption of this standard, some companies and

textbooks used a 1 kB to represent 1 000 bytes while others
used 1 kB to represent 1 024 bytes
Using SI prefixes, 1 kB refers to exactly 1 000 bytes
Using binary prefixes, 1 KiB refers to exactly 1 024 bytes

Often used as KB
For us, we always mean exact number of bytes

whether we use KiB or KB

Important Binary Prefixes (IEEE 1541)
Binary Prefix Symbol Base 2 Base 10

kibi Ki 210 1 024
mebi Mi 220 1 048 576
gibi Gi 230 1 073 741 824
tebi Ti 240 1 099 511 627 776
pebi Pi 250 1 125 899 906 842 624
exbi Ei 260 1 152 921 504 606 846 976
NOTE:
The IEEE 1541 standard for binary prefixes was
officially adopted by the IEEE in 2005 but the binary
prefixes have not yet seen widespread use in the
computer industry.

Word Addressable Memory Systems
In a word addressable memory system, instructions may only

refer to a particular word in memory
Each word has a unique address
Adjacent words are located in addresses that differ by 1
Memory accesses transfer data 1 word at a time
For example, the first word in memory would be located at

address 0x0000 and the second word in memory would be
located at address 0x0001, regardless of the word size
Given a 24 bit address, a word addressable memory system

supports 64 MiB of memory if a word consists of 4 bytes
Word addressable memory systems are rarely used

Word and Byte Encoding
A common word length is 32 bits

Such a word can store a 32-bit signed integer or four 8-bit bytes (e.g.,
ASCII characters)
For 32-bit integer encoding, bit b31 is sign bit

Byte Ordering
Defines how addresses are assigned to bytes of a word
Big-endian byte ordering assigns the lower byte addresses to

the more significant bytes within a word of memory
Low addresses to left most bytes
Little-endian byte ordering assigns the lower byte addresses

to the less significant bytes within a word of memory
Low addresses to right most bytes

Big-Endian vs. Little-Endian
MSB Byte Address LSB MSB Byte Address LSB
Word 1 0 1 2 3 Word 1 3 2 1 0
Word 2 4 5 6 7 Word 2 7 6 5 4
NOTE: NOTE:
The most significant byte is The least significant byte is
assigned to address 0. assigned to address 0.
2k-4 2k-3 2k-2 2k-1 2k-1 2k-2 2k-3 2k-4
a) Big-endian assignment b) Little-endian assignment
Bits within a byte are labelled in the same way

B31, B30, , B2, B1,B0

Example of Byte Ordering
Given a 32 bit hexadecimal value of 0x0A0B0C0D stored at

memory address 0x0000, the bytes are arranged as follows
for each of the popular byte orderings:
Byte Values
Memory Address
Big-Endian Little-Endian
0x0000 0x0A 0x0D
0x0001 0x0B 0x0C
0x0002 0x0C 0x0B
0x0003 0x0D 0x0A
NOTE:
The least significant byte is 0x0D and
the most significant byte is 0x0A.

Word Alignment
Aligned addresses are those that begin at a byte address that

is a multiple of the number of bytes of a word
A 4 byte word has aligned addresses at 0, 4, 8, 12, 16,
Most processors require words of data to be aligned
0x0000 Word 0
0x0004 Word 1
0x0008 Word 2
..
.
4n Word n

Instruction Types
A computer must have instructions capable of performing four

types of operations:
Data transfers between the memory and the processor registers
Load, store
Arithmetic and logic operations on data
Add, subtract,
Program sequencing and control
Branch, jump,
I/O transfers (typically memory operations for memory mapped)
Load, store,
An instruction-set architecture (ISA) defines the set of

opcodes (machine language), and native commands
implemented by a processor
Examples: ARM ISA, x86 ISA, MIPS ISA, SPARC ISA,

RISC vs. CISC
RISC ISA characteristics

Each instruction fits in a single word
E.g. 32 bits
Load-store architecture
Memory operands are accessed only using Load and Store instructions
All operands for arithmetic and logical operations must be in processor registers
or one of the operands may be given explicitly in the instruction
CISC ISA characteristics

Variable length for an instruction
Many instructions can access memory, and multiple operands can be
locations to the memory

Register Transfer Level (RTL) Notation
Expressing semantics of instructions as data transfers:

1. Memory locations are identified by symbolic names
For example, LOC1 and LOC2 may be symbolic names for two particular
addresses in memory
2. Registers are identified by register names
For example, R0 and R1 may be names for general-purpose registers
3. The contents of memory locations are denoted by placing square brackets
around the names of the locations
For example, [LOC1] refers to the contents of memory location LOC1
4. Control signals are identified by symbolic names
For example, T1 and T2 may be symbolic names for control signals
produced by the control unit within the CPU
Convention for us: [X]

If X is a register, means contents of register
If X is a memory address, means contents of memory pointed by address X
16
ECE 222 (Patel, H.): ISAs and Addressing Modes

Register Transfer Level Statements
Assignment statements transfer and manipulate data

Right-hand side denotes a value,
Left-hand side denotes the name of a location where the value is to be
placed
Example: R1 [LOC1]
Conditional statements allow the evaluation of control signals

prior to performing assignment statements
Example: If (T1 = 1) then (R2 [R1])
17

Examples of RTL Statements
R1 [LOC1]
This assignment statement transfers the contents of memory

location LOC1 into register R1
R3 [LOC1] + [LOC2]
This assignment statement adds the contents of memory

locations LOC1 and LOC2 and stores the sum in register R3
LOC1 [R1]
Transfer contents of register R1 to the memory location

addressed by LOC1
18

Assembly Language Notation
Assembly language is a type of notation used to represent

machine instructions and programs
Assembly language instructions may specify

One or more source operands and
One or more destination operands
Example
Transfer contents from memory location LOC1 to register R1 is the
following:
Load dest, src Load R1, LOC1
Example
Store the contents of register R1 to the memory location addressed by
LOC1
Store src, dest Store R1, LOC1

Arithmetic Instruction
An example of an arithmetic instruction is the following:
Destination Source
Operand Operands
Add R2,R3,R4
R2 [R3] + [R4]
This is an example of a 3 operand instruction

R3 and R4 are the source operands
R2 is the destination operand

Addition Example: C = [A] + [B]
Paper-simulate this example
i Load R2,A
These memory locations
i+4 Load R3,B store the program
instructions.
i+8 Add R4,R2,R3
i + 12 Store R4, C R2 12
36
8
R3 12
36
8
A 12 R4 12
36
8
B 24 These memory locations
store the data values
C 10
36
222 used by the program.

Additional Example: Sum N numbers
Paper-simulate this example ?

More Instructions in the Arsenal
Subtract R2, R2,#1

R2 [R2] 1
#1 is known as an immediate value specified in the bits of the
instruction
Branch_if_[R2]>0 LOOP
If ([R2] > 0) then PC LOOP
Conditional branch
Condition: ([R2] > 0)
Branch target: LOOP
Branch_if_[R4]>[R5] LOOP
Branch_greater_than R4,R5,LOOP
Mnemonic
BGT R4,R5,LOOP

Branching Example
Consider the following assembly language program that

illustrates branching:
Load R2,N NOTE:
Clear R3 Due to space limitations,
LOOP only a portion of the entire
Determine address of program is shown. The
These memory locations next number, load the complete example is
store the instructions next number into R5, provided in Figure 2.6 of the
that loop when the and add it to R3 textbook.
branch is taken.
Subtract R2,R2,#1
Branch_if_[R2]> 0, LOOP
Store R3,SUM NOTE:

I have only illustrated NUM1
SUM and NUM2. Many more
data values might be used
N
by the program.
NUM1
NUM2

Comments on the Previous Example
LOOP, SUM, N, NUM1, and NUM2 are all examples of labels

In assembly language programs, labels are used to represent the
addresses of instructions and data values within memory
A simple loop that iterates n times is created using the

following steps:
1. A count value stored in a register is initialized to n
2. Every time the loop iterates, the count value is decremented
3. The program branches to the start of the loop if the count value is
greater than 0
The program exits the loop when the count value in register
R2 is 0

Specifying Operands
Addressing modes
Different ways for specifying the locations of instruction operands
The location of instruction operands are specified using an

effective address
The effective address is computed differently depending on

the addressing mode
Instructions may have a source effective address, a

destination effective address, or a combination of both
Most processors support a large set of addressing modes

Addressing Modes
Addressing Mode Assembler Syntax Function
Immediate #Value Operand = Value
Register Ri EA = Ri
Absolute (Direct) LOC EA = LOC
(Ri) EA = [Ri]
Register Indirect
(LOC) EA = [LOC]
Index X(Ri) EA = [Ri] + X
Base with Index (Ri,Rj) EA = [Ri] + [Rj]
PC-Relative X(PC) EA = [PC]+ X
There can be many more addressing modes

Some more to come

Immediate Addressing
Immediate addressing is used when an operand is a

constant
#Value Operand = Value
Example: Move R0, #200 moves a constant value of 200

expressed as a decimal quantity to register R0
RTL: R0 200
Example: a program to compute A = [B] + 6 could be written

in assembly language as follows:
Load R1, B Absolute addressing for B; Register addressing for R1
Add R1,R1,#6 Immediate addressing for 6; Register addressing for R1
Store R1, A Register addressing for R1; Absolute addressing for A

Register Addressing
Register addressing is used when an operand is a register

Ri EA = Ri
When general-purpose registers are used, the notation Rn is

used to represent register n
Example: Add R2, R3, R4
RTL: R2 [R3] + [R4]

Absolute (Direct) Addressing
Absolute addressing is used when the address of an

operand in memory is known
LOC EA = LOC
An example of absolute (direct) addressing is:

Load R3, LOC
RTL: R3 [LOC]

Register Indirect Addressing
Indirect addressing is used when the address of an operand

is stored in a register or a memory location
(Ri) EA = [Ri]
(LOC) EA = [LOC]
Example: Load R0, (R1) moves the contents of the memory

location pointed to by register R1 to register R0:
Note that the round brackets denote the use of indirect addressing
RTL: R0 [[R1]]
Indirect addressing is analogous to the use of pointers in a

high-level language

Register Indirect Addressing Example 1
Consider the operation of the Load R0,(R1) instruction

illustrating the use of indirect addressing:
Load R0, (R1) R0 10

20
R1 1000
1000 20
NOTE:
In this case, R1 contains the address of one of the operands to be used in the
calculation. Indirect addressing is similar to dereferencing a pointer.

Summation Example
We are now ready to write the sum N numbers with a loop!

Summation Example
Given the addressing modes introduced, it is now possible to

show the complete assembly language program for calculating
the sum of n numbers:
Load R2,N
Clear R3 Initialization code
Move R4,#NUM1
LOOP Load R5,(R4) Indirect addressing
Add R3, R3,R5
Summation loop
Add R4,R4,#4
Subtract R2,R2,#1
Branch_if_R2>0 LOOP
Store R3,SUM
SUM
New Instruction
N
Move R4,#NUM1 Data values in memory
NUM1
Semantics: R4 NUM1 NUM2

Index Addressing
Index addressing is used when the operand address is

known to be at a constant offset from a known memory
location
X(Ri) EA = [Ri] + X
Index addressing is particularly useful for arrays of data

If the starting address of the array is known and the size of the data
elements is fixed, index addressing can be used to calculate the effective
address of a particular element
For example, Load R1,20(R0) copies the data value stored at

the effective address to register R1
The effective address is calculated as the sum of the contents of index
register R0 with a constant offset of 20
RTL: R1 [[R0] + 20]

Index Addressing Example 1
Consider the operation of the following Load R1,20(R0)

instruction illustrating the use of index addressing:
Load R1, 20(R0) R0 1000

R1
1000 12
1020 36
The final value in R1 is 36

Index Addressing Example 2
Assume List of Student Records

List of scores for a course
N n
Starts at address LIST
LIST Student ID
4-word memory block = record LIST + 4 Test 1 Student
Word length is 32-bits LIST + 8 Test 2 Record 1
Each student has ID followed LIST + 12 Test 3

by 3 test scores Student ID
Student Test 1
Compute sum of test scores Record 2
Test 2
obtained on each of the Test 3
tests and store these sums
in SUM1, SUM2, and SUM2 Student
Record 3

Index Address Example 2
List of Student Records Assembly Language Program
N n Move R2,#LIST
Clear R3
LIST Student ID Clear R4
LIST + 4 Test 1 Student
Clear R5
LIST + 8 Test 2 Record 1 Load R6,N
LOOP: Load R7,4(R2)
LIST + 12 Test 3 Add R3,R3,R7
Student ID Load R7,8(R2)
Student Add R4,R4,R7
Test 1
Record 2 Load R7,12(R2)
Test 2 Add R5,R5,R7
Test 3 Add R2,R2,#16
Subtract R6,R6,#1
Student Store R3,SUM1
Record 3
Store R4,SUM2
Store R5,SUM3

Comments on the Previous Example
The program on the previous slide computes sums of test

scores on three different tests:
The sum of Test 1 scores is accumulated in R3
Index addressing is used to access the data within the

student records
The size of a student record is fixed so the address of the individual test
scores can be easily computed using the base address stored in register
R2 and a constant offset
Register R2 is updated to reflect the starting address of the current
student record as student records are processed
Notice that this is an example of a list data structure

Base with Index Addressing
Base with index addressing is used when it is more

convenient for a second register to compute the offset from a
known memory location
(Ri,Rj) EA = [Ri] + [Rj]
For example, Load R2, (R0,R1), uses base with index

addressing for the source operand to copy data from the
effective address to register R2:
The effective address is computed as the sum of an index register R0 and
a base register R1
RTL: R2 [[R0]+[R1]]

Base with Index and Offset Addressing
Base with index and offset addressing is used when there

is a need to compute an offset from a known memory location
using a constant offset and two register values:
X(Ri,Rj) EA = [Ri] + [Rj] + X
This type of addressing is useful for 3-dimensional arrays:

The first register stores the row of the record within the matrix
The second register stores the column of the record within the matrix
The constant offset indicates the specific field within the records of data
For example, Load R2,10(R0,R1) uses base with index and

offset addressing for the source operand to copy data from
the effective address to register R2:
The effective address is computed as the sum of index register R0, base
register R1, and a constant offset of 10
RTL: R2 [[R0]+[R1]+10]

PC-Relative Addressing
PC-relative addressing is very similar to index addressing:

Instead of an index register, the program counter register is used
PC-relative addressing is useful for specifying addresses

relative to the current program counter
For example, Move R0, -16(PC)

The effective address for the destination operand R0 is calculated as the
sum of the program counter and a constant offset of -16
RTL: R0 [PC] + -16
Relative addressing is most often used to specify the

destination for branch instructions

Calculating Offsets for a Branch
Assume that the LOOP label corresponds with address 1000 in

the following assembly language program:
The addresses for the instructions have
Load R2,N been shown to the right of the instructions.
Clear R3 Assumed instructions have a constant size
of 4 bytes.
Move R4,#NUM1
LOOP Load R5,(R4) 1000 When the branch instruction is executed,
Add R3, R3,R5 1004 the program counter already refers to
address 1020.
Add R4,R4,#4 1008
Subtract R2,R2,#1 1012
To branch to the start of the loop, the offset
Branch_if_[R2]>0 LOOP 1016 required will be -20.
Store R3,SUM 1020
NOTE:
SUM
The assembler calculates a relative
N address for a branch automatically when
NUM1 given a label for the start of the loop. J
NUM2

Auto Increment Addressing
Auto increment addressing is designed to simplify the task

of accessing data items in successive locations in memory
(Ri)+ EA = [Ri]; Increment Ri
Auto increment addressing is similar to register indirect

addressing using a register:
The key difference is that the register is automatically incremented
in value after the data in the register has been read
This is sometimes called post-increment addressing
For a byte addressable memory system, the size of the

increment depends on the number of bytes read
E.g. Load R2, (R3)+

RTL: R2 [[R3]] ; R3 [R3] + inc

Auto Decrement Addressing
Auto decrement addressing is similar to auto increment

addressing:
The key difference is that the register is automatically
decremented in value prior to the data in the register being read
For a byte addressable memory system, the size of the

decrement depends on the number of bytes read
This is sometimes called pre-decrement addressing
E.g. Load R2, -(R3)

RTL: R3 [R3] inc ; R2 [[R3]]

Comments on Auto Increment Addressing and
Auto Decrement Addressing
Neither of these addressing modes are essential:

Instructions using these addressing modes can always be rewritten as a
sequence of two instructions
Auto increment addressing and auto decrement addressing

are provided out of convenience:
These addressing modes are particularly useful when working with stacks
and queues
While it might not be apparent, it is important that auto increment
addressing performs a post-increment while auto decrement addressing
performs a pre-decrement

Stacks in General
A stack is a list of data elements of a particular size with

access restrictions:
Add or remove elements from only one end of the list
Stacks implement LIFO (last-in-first-out) behaviour
Analogy: Pile of trays at cafeteria

Student picks up a tray before getting food (Pop a tray)
Clean trays are put on top of the pile (Push a tray)
Perhaps another analogy: Stack of homework

Stacks in Computers
Stack resides in the main memory

The top of the stack (most recent element) is stored at the lowest
memory address
The bottom of the stack (least recent element) is stored at the highest
memory address
Special CPU register points to the top of the stack (stack

pointer)
Assume SP is the stack pointer register
Push: Data elements are pushed onto the stack

A push involves decrementing the SP and then copying data into the new
location pointed to by the SP
Pop: Data elements are popped from the stack

A pop involves copying data from the location pointed to by the SP and
then incrementing the SP
Illustration of a Stack
Low Memory Addresses

Push
SP -28 Current Top Element
17
739
Stack
43 Current Bottom Element
Pop
High Memory Addresses

Pushing onto the Stack

Subtract SP,SP,#4
Store R2,(SP)
Push
100
SP -28 Current Top Element
17
739
Stack
R2 100

Popping from the Stack

Load R2,(SP)
Add SP,SP,#4
SP 100 Current Top Element
-28
17
Stack
739

Pop
R2 100

Subroutines
A subroutine is a block of instructions that is executed

repeatedly
Subroutines have the following desirable features:

Avoid unnecessary duplication of code
Permit code reuse
Enable modularization
Subroutines do the following:

Program invokes subroutine by executing Call instruction
Subroutine executes
Subroutine returns to the main program by executing Return instruction

Calling and Returning from Subroutines
Calling is implemented using subroutine linkage method

Save return address to a specific location
May be stored on the stack
But it may be stored in a special register called the link register
A Call is a special branch instruction that invokes a

subroutine by performing the following steps:
1. Store the contents of the PC to the link register
This is to know where to return back to once the subroutine completes
2. Branch to the target address specified by the instruction
Returning from a subroutine performs the following step:

1. Branch back to the address in the link register

Example: Subroutine Linkage Method

Nesting Subroutines and the Stack
We can permit one subroutine (SUB1) to call another (SUB2),

which results in subroutine nesting
Potential problem
Link register contents after SUB1 call are overwritten after second SUB2
call
Solution
SUB1 should save the address in the link register on the stack
before second call to SUB2
Before returning from SUB1, SUB1 should restore the contents of link
register
Notice that we use the stack to save the return address

Problems will occur if either of the following are true:
1. The stack is full so the calling of a subroutine causes the stack to overflow
2. The stack is not properly maintained during program execution

Parameter Passing
A program may call a subroutine many times with different

data to obtain different results
Information exchange to/from a subroutine is called parameter passing
Three different schemes to pass parameters:

1. Parameters may be passed using registers
2. Parameters may be passed using memory locations
3. Parameters may be passed on the stack
In general, parameters are passed using registers if and only

if all of the following conditions are true:
1. A small number of parameters are required
2. The subroutine is not recursive
3. The subroutine does not call other subroutines that will use the same
registers

Example of Parameter Passing Using
Registers: Sum n numbers
Calling program
Load R2,N R2 contains n
Move R4,#NUM1 R4 points to the address of NUM1
Call LISTADD
Store R3,SUM R3 holds the result

Subroutine
LISTADD: Subtract SP,SP,#4 Push [R5] on stack. Because its
Store R5,(SP) used in LISTADD
Clear R3
LOOP: Load R5,(R4)
Add R3,R3,R5
Add R4,R4,#4 Summation in a LOOP as before
NOTE:
Subtract R2,R2,#1
Can you identify
pass by reference
and pass by value Load R5,(SP) Restore [R5] in preparation to
in this example? Add SP,SP,#4 Return
Return

Example of Parameter Passing Using
Stack: Sum n numbers
Move R2,#NUM1 LISTADD: Subtract SP,SP,#16
Subtract SP,SP,#4 Push #NUM1 Store R2,12(SP)
Store R2,(SP) Store R3,8(SP)
Load R2,N Store R4,4(SP)
Subtract SP,SP,#4 Push N Store R5,(SP)
Store R2,(SP) Load R2,16(SP)
Call LISTADD Load R4,20(SP)
Load R2,4(SP) Clear R3
Store R2,SUM Get SUM and LOOP: Load R5,(R4)
Add SP,SP,#8 restore stack Add R3,R3,R5
Add R4,R4,#4
Subtract R2,R2,#1
Store R3, 20(SP)
[R5] Level 3 Load R5,(SP)
[R4] Load R4,4(SP)
Load R3,8(SP)
[R3]
Load R2,12(SP)
[R2] Add SP,SP,#16
n Level 2 Return
NUM1
Level 1

Stack Frames
Locations at the top of the processor stack are used as a

private work space by subroutines
This is called a stack frame
A frame pointer (FP) register enables access to private work space for
current subroutine
A stack frame consists of all of the items pushed onto the

stack prior to the calling of a subroutine and during the
execution of a subroutine

Stack Frames
Prior to calling a subroutine, the following items are pushed

onto the stack in order:
1. Parameters (if applicable)
Once the subroutine executes, the following items are pushed

onto the stack in order:
1. Return address (link register content)
2. Frame pointer to indicate the start of a stack frame
3. Local variables
4. Register values for all registers that will be modified by the subroutine

Example of a Stack Frame
Stack Pointer (SP) Saved [R4]

Registers Pushed at the
Saved [R3] Start of Subroutine Call
Saved [R2]
Local Variable 3
Local Variable 2
Data Pushed / Reserved at
Local Variable 1 Time of Subroutine Call
Frame Pointer (FP) Saved [FP]
Return Address
Parameter 1
Parameters Pushed Prior
Parameter 2 to Subroutine Call
Parameter 3
NOTE:
This is a complex stack frame that illustrates the use of parameter passing,
creation of a frame pointer, allocation of local variables, and the saving of
registers R2, R3, and R4 prior to modification.

The Use of the Frame Pointer
The stack frame on the previous slide illustrates the use of a

frame pointer to provide a convenient reference point for
accessing parameters and local variables:
Any general purpose register with the exception of the stack pointer may
be used as the frame pointer
Using the frame pointer, these values are accessed as follows

(assuming all values are stored as one word):
Parameter 1 : 8(FP)
Parameter 2 : 12(FP) NOTE:
Parameter 3 : 16(FP) Regardless of the number of local
variables, the parameters will
Local Variable 1 : -4(FP) always be in the same location
Local Variable 2 : -8(FP) relative to the frame pointer.
Local Variable 3 : -12(FP)

Manipulating SP and FP for Stack Frames
Before calling subroutine Saved [R4]

Calling program saves four parameters on stack Saved [R3]
Saved [R2]
Call is executed
Local Variable 3
SP points to return address
Local Variable 2
Local Variable 1
When entering subroutine Saved [FP]
Return address (link register) saved Return Address
Parameter 1
Save FP to stack first!
Parameter 2
Subtract SP,SP,#4
Store FP,(SP) Parameter 3
Move FP,SP Parameter 4
Make space for 3 local variables
Make space and store R2, R3, and R4

Manipulating SP and FP for Stack Frames
When returning from subroutine Saved [R4]

Pop R4, R3, R2 into those registers Saved [R3]
Saved [R2]
De-allocate local variables
Local Variable 3
Save old value of FP back into FP
Local Variable 2
Restore link register Local Variable 1
Return Saved [FP]
Return Address
Parameter 1
Parameter 2
Parameter 3
Parameter 4

Example: Stack Frames with Nested
Subroutines - Main

Subroutines SUB1

Subroutines- SUB2

Additional Instructions
Logic instructions
AND, OR, and NOT operations
Using RISC-style instructions, all operands are in registers or specified as
immediate values:
Or R4, R2, R3
And R5, R6, #0xFF
16-bit immediate is zero-extended to 32 bits
Shift and rotate instructions

Shifting binary value left/right = mult/div by 2
Arithmetic shift preserves sign in MS bit
Rotate copies bits from one end to other end
Shift amount in register or given as immediate
Examples:
LShiftL R3, R3, #2 (mult by 4)
RotateL R3, R3, #2 (MS bits to LS bits)

Additional Instructions

Encoding of Machine Instructions
Assembly-language instructions express the actions to be

performed by processor circuitry
Assembler
A program that converts to machine instructions
Three-operand RISC instructions require enough bits in single

word to identify registers
16-bit immediate must be supported
Instruction must include bits for OP code
Call instruction also needs bits for address

Encoding of Machine Instructions
One possible encoding

Summary
Big vs. Little endian
Addressing modes
Subroutines
Stacks
Parameter passing
Additional instructions
Encoding of machine instructions

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Department of Electrical and Computer Engineering

Special thanks to Prof. Bill Bishop, Prof. Gord Agnew,

Students enrolled in ECE 222 are permitted to print copies of

Instruction Sets and Addressing

ECE 222 (Patel, H.): ISAs and Addressing Modes 3

Memory systems do not allow instructions to directly address

The range of addresses is known as the address space

The number of unique addressable locations in memory

ECE 222 (Patel, H.): ISAs and Addressing Modes 4

Memory systems are typically byte addressable

Instructions may refer to a particular byte or a particular word

For example, the first word in memory would be located at

Given a 24 bit address, a byte addressable memory system

In 2005, IEEE adopted a set of binary prefixes to replace SI

Prior to the adoption of this standard, some companies and

Using SI prefixes, 1 kB refers to exactly 1 000 bytes

Using binary prefixes, 1 KiB refers to exactly 1 024 bytes

For us, we always mean exact number of bytes

ECE 222 (Patel, H.): ISAs and Addressing Modes 6

Binary Prefix Symbol Base 2 Base 10

ECE 222 (Patel, H.): ISAs and Addressing Modes 7

In a word addressable memory system, instructions may only

For example, the first word in memory would be located at

Given a 24 bit address, a word addressable memory system

Word addressable memory systems are rarely used

ECE 222 (Patel, H.): ISAs and Addressing Modes 8

A common word length is 32 bits

For 32-bit integer encoding, bit b31 is sign bit

ECE 222 (Patel, H.): ISAs and Addressing Modes 9

Defines how addresses are assigned to bytes of a word

Big-endian byte ordering assigns the lower byte addresses to

Little-endian byte ordering assigns the lower byte addresses

ECE 222 (Patel, H.): ISAs and Addressing Modes 10

2k-4 2k-3 2k-2 2k-1 2k-1 2k-2 2k-3 2k-4

a) Big-endian assignment b) Little-endian assignment

Bits within a byte are labelled in the same way

ECE 222 (Patel, H.): ISAs and Addressing Modes 11

Given a 32 bit hexadecimal value of 0x0A0B0C0D stored at

ECE 222 (Patel, H.): ISAs and Addressing Modes 12

Aligned addresses are those that begin at a byte address that

Most processors require words of data to be aligned

ECE 222 (Patel, H.): ISAs and Addressing Modes 13

A computer must have instructions capable of performing four

An instruction-set architecture (ISA) defines the set of

ECE 222 (Patel, H.): ISAs and Addressing Modes 14

RISC ISA characteristics

CISC ISA characteristics

ECE 222 (Patel, H.): ISAs and Addressing Modes 15

Expressing semantics of instructions as data transfers:

Convention for us: [X]

ECE 222 (Patel, H.): ISAs and Addressing Modes

Assignment statements transfer and manipulate data

Conditional statements allow the evaluation of control signals

ECE 222 (Patel, H.): ISAs and Addressing Modes

This assignment statement transfers the contents of memory

This assignment statement adds the contents of memory

Transfer contents of register R1 to the memory location

ECE 222 (Patel, H.): ISAs and Addressing Modes

Assembly language is a type of notation used to represent

Assembly language instructions may specify

ECE 222 (Patel, H.): ISAs and Addressing Modes 19

An example of an arithmetic instruction is the following:

This is an example of a 3 operand instruction