A DC/DC Converter Suitable for HVDC Applications
with Large Step-ratios
T. Lth*, M. Merlin, T. Green
Electrical & Electronic Engineering
Imperial College
London, UK
*thomas.luth06@ic.ac.uk
Abstract This paper presents a DC/DC converter suitable for
HVDC applications requiring a high step-ratio, such as HVDC
taps. A circuit and its method of operation are introduced and
demonstrated through a full scale, 500 kV and 200 MW,
simulation model. The paper also includes an analysis of the
power losses in all major circuit components for the simulation
model.
I. INTRODUCTION TO HVDC TRANSMISSION
Across Europe Renewable Energy Sources (RES) are
becoming an ever more important component of the national
energy mix. Whilst the exact goals for RES content might
vary, most factor in an increase in capacity over the coming
years. RES however are inherently inflexible in terms of
location of generation which requires new transmission
corridors to facilitate this expansion.
High Voltage Direct Current (HVDC) transmission
technologies are seen as a key component to connect a
number of planned off-shore wind-farms as well as provide
greater transmission capacity between countries. Some
conceptual schemes envisage a transmission backbone which
stretches from the Norwegian hydro plants through central
Europe to Northern Africa [1]. Whilst this may or may not
happen in the distant future, a number of projects are pointing
the way already. One such example is the recently published
vision to build three north-south transmission corridors in
Germany using HVDC [2]. A number of connections to off-
shore wind-farms in the north-sea may become the
foundation for a multi-terminal HVDC network for northern
Europe [3].
For such multi-terminal applications, Voltage Source
Converter (VSC) technology is considered most suitable [4].
The modular multi-level converter (MMC) [5] is currently
the most commonly promoted architecture although
alternatives exist in the literature [6-7]. The popularity of the
MMC is not least due to its modular design using cells, or
sub-modules, consisting of half- or full-bridges.
The authors gratefully acknowledge the financial support provided by
the EPSRC (www.epsrc.ac.uk) under grant number EP/G066477/1.
978-1-4799-5776-7/14/$31.00 2014 IEEE
Such sub-modules can be series-connected to form a stack
of cells which provides voltage generating capabilities in the
converter. Because each cell is typically capable of providing
a relatively small voltage compared to the total maximum
stack voltage, very smooth (finely resolved) voltage
waveforms can be generated. Each stack can thus be thought
of as a controlled variable voltage source.
Most HVDC schemes build to date are point-to-point
schemes. The converter at the terminals is typically rated at
or near the full power capacity of the link. Facilitating a
partial power connection, such as an en-route load, using such
conventional, full scale converters would not make full use
of their capacity and thus financially inefficient. A partial
power connection is referred to as a HVDC tap and is
typically rated at 1-10 % of the links capacity [8] and feeds
directly into a medium or low voltage local network.
A HVDC tap could be build using a conventional AC/DC
converter followed by a three phase transformer to provide
the voltage step, as illustrated in Fig. 1. In this design a
transformer would be used to facilitate the voltage-step to
allow for a direct interconnection to the local AC grid. Thus
such as a transformer would need to be rated at 50 Hz and be
of a three-phase design. Such transformers are typically quite
voluminous. By replacing the transformer with a DC/DC
converter to accomplish the voltage-step, as illustrated in
Fig. 2, an overall reduction in volume may be achieved [9].
DC/DC converters for HVDC applications is an area of
increasing interest. A designs using a front-to-front
arrangement suitable for high power ratings and low step-
ratios can be found in [10]. Alternatives with larger step-
ratios are discussed in [11-12] and some thoughts on DC
converters using sub-modules can be found in [13]. This
paper presents a DC/DC converter topology suitable for such
an application.
5331
 HVDC Link transformer is connected between this midpoint and a neutral
connection created by two DC terminal capacitor. A passive
AC Link rectifier interfaces the AC output from the transformer with
the HV2 DC link. The converter presented is illustrated for a
symmetric monopole arrangement.
As this is intended as a single-phase design a square-wave
DC/AC transformer shape is chosen for the AC connection. Theoretically this
converter
allows for an uninterrupted DC current flow in the HV2 DC
Figure 1. HVDC tap design using high voltage rated AC/DC converter. side with minimal DC filtering requirements. Conventionally
in high power transmission systems, sinusoidal waveforms
HVDC Link prevail. Square-waves however have a more advantageous
RMS to peak value ratio. Furthermore to achieve similarly
AC Link small DC filter requirements using sinusoids a multi-phase
arrangement would be required. It can also be argued that due
to the insulation distances involved when building converter
halls, fewer phases will allow a more compact design.
DC/DC DC/AC
converter converter A. Working mechanism
The primary current is formed from the two arm currents
Figure 2. HVDC tap design using DC/DC converter and low voltage
DC/AC converter. as per equation (1). The arm currents in turn consist of the
AC component due to the primary current and a DC current
II. INTRODUCTION TO PROPOSED DC/DC CONVERTER resulting from the power exchange with the HV1 DC link.
The converter proposed is of a single phase design, as The primary current is split equally between both arms and
illustrated in Fig. 3: two stacks of cells are connected across flows through the HV1 DC side capacitors.
the HV1 terminals (higher voltage DC link) and generate an
AC voltage at their midpoint. The primary winding of a
HV1 Filter I
d1

Cell

Stack of Cell
Vd1
cells
2
Half Bridge
Cell
Rectifier Id2 HV2 Filter
It
Vp
Lt
Is Vd2
Lb Ip Vs
Ib
Cell
Cell Id2
Cell
Vd1
2
Cell

Id1
Figure 3. Circuit diagram of proposed DC/DC converter.

5332

  =
 


:
  =
 sqw  
(1) transition takes a non-zero amount of time. To facilitate a


quick transition of the AC component of the arm currents the
stacks voltage capability can be increased. This increase can
 constant, &'( , which increase the voltage capability of the
1  0  <
be expressed as per equation (3) in terms of a control margin
 2
: sqw  =
0 
1   < 
stack as defined by (2).

2 Voltage &
current
The stacks of cells have to generate the square-wave measurements
voltage across the primary. If this voltage is smaller in
magnitude than the terminal voltage of the HV1 link, then the Current
stacks are said to be under-modulating, or in other words have references
to generate a DC voltage as well. The equations describing
the primary voltage as well as the voltage capability required

!"
of the stacks are summarised in (2).

  = +  
Current current

2
(2) controller

!"
measurements

$  =  

2

:   = % sqw  

Low-level
controller

The rectifier as presented here is made up of passive cell

components only. This limits the power flow to a transfer switching
signals
from the HV1 to the HV2 DC connection. The converter
could be made to allow for bi-directional power transfer by

!"
adding anti-parallel active devices to the rectifier. Figure 4. Controller structure overview.

B. Control structure
The arm inductors along with the leakage inductance of
the transformer create an inductive network, the terminals of
which are connected to the stacks and the neutral connection
created by the HV1 DC capacitors. The cell stacks can be
thought of as controlled voltage sources which can apply any
voltage levels at the terminals of the inductive network to
control the currents flowing through it.
An overview of the controllers structure is provided in
Fig. 4: it can be split into three separate components. First,
the reference building. Here time-domain references for the
arm currents are created taking into account any power set-
points to be tracked. Second, the current controller. Here the
current references are tracked. A proportional MIMO
controller is used to create the required stack voltages to track
the arm current references. Finally the low-level controller
% ,$
= + *  1 + &'( 
2
(3)
Whilst this will increase the number of cells and therefore
the losses incurred in the stacks, a certain amount of control
margin will always be required: The stacks perform two
functions: first, they generate the voltages across the primary.
Second, they apply voltages across the inductive network
control the currents. To do the second, voltage capability
additional to that required for the first is required.
A typical waveform of the voltage generated by the top
stack along with its arm current can be seen in Fig. 5. Here
the voltage peaks and troughs generated to achieve a current
transition can be seen. The ramp-rate of the arm current is
proportional to the voltage available for the current
transitions. To ensure the rise and fall times of the current are

1
the same, the control margin can be found as per equation (4).
discretises the required stack voltages into an integer number
&'( = 1
1 %
of cell voltages to be switched into the conduction path. The (4)

final output are the switching commands to each individual
cell transistor.
C. Voltage capability in stacks for control purposes
An ideal square-wave transitions between its extreme
values instantaneously. Practically this is of course
impossible: the inductances in the circuit combined with the
limited voltage capability of the stacks mean that each
+
2 !"
Ensuring that the current transitions quickly reduces the
harmonic content of the DC currents in both Dc connections.
This allows for smaller filter components which implies a
smaller filter volume and lower losses.

5333
D. Filter design
The DC filters consist of the DC side capacitor and the
parallel inductor and resistor impedance connecting to the
DC terminal. The transfer function for the filter is shown in
equation (5).
to be used. This allows the filter inductance to be smaller, i.e.,
more compact and less lossy. A rising frequency also allows
the use of smaller cell capacitors, which in a 50 Hz modular
converter application tend to take up about 2/3rd of the total
volume of the cell [10].

1500
a) Arm Current The transformer also will decrease in volume as the
frequency is increased. This is primarily caused by a
1000
reduction in the peak flux density achieved during a cycle, as
Current [A]

500 the length of the cycle decreases. This allows the cores cross
0 sectional area to be shrunk. At the same time however the
500 transformers hysteresis and eddy current losses will rise with
b) Stack Voltage frequency. Thus the losses per unit volume quickly increase
600
causing a rise in operating temperature. At some point the
Voltage [kV]

400
200
volume of the additional cooling equipment required to
Voltages to ramp current maintain a tolerable operating temperature inside the
0
transformer, will nullify any volume savings due to a
200 decreased core size.
0.3925 0.393 0.3935 0.394 0.3945
Time [s]
A rising AC higher frequency also requires the cells to
Figure 5. Typical stack voltage and arm current.

-.
switch more often per unit time, to generate the AC voltages

,
+1
/.
and ramp the currents. Each switching event is also a power
(5)
+, =
loss event and therefore a trade-off for the AC frequency
-.
, 0 -. 1. + , / + 1
exists where additional switching losses incurred due to a
higher frequency no longer justify the reduction in volume
. achieved to passive components.
The filter was designed by first sizing the DC capacitor
Voltage [kv] Voltage [kv] Voltage [kv]

200
such that its voltage ripple, due to the circulating AC Vp
component of the arm current on the HV1 side for instance, 0

is kept within tolerable limits. Following this design rule, the 200

corner frequency of the filter sets the inductance, given the

50 V
capacitance. Lastly the filters quality factor dictates the 0
s

parallel resistance. As the quality factor dictates the current 50

near 1. For a quality factor of 12 a corner frequency (4 )

overshoot during a power ramp, this should be kept below or
600

between 56 4 56 has been found to be appropriate.

. .
400 V st

" 7
200 V sb
0
E. Circuit Simulation 0.39 0.392 0.394 0.396 0.398 0.4
Time [s]
The systems operability was confirmed through
Figure 6. Transformer and stack voltages for test system.
simulation in Simulink. The use of the Artemis block library
allowed the simulation of a full scale converter with a HV1 2000
Current [A]

link voltage of 500 kV stepped down to 50 kV on the HV2 I

p
0
side. An overview of the system and simulation parameters is
provided in Table I. 2000
5000
Current [A]

Each cell is operated at a nominal voltage of 1.8 kV I

s
resulting in 280 cells per stack. A typical HVDC underground 0
cable is designed for a current rating of up to 3 kA and 300 kV 5000
[14]. The converters power rating of 200 MW and terminal
Current [A]

1000 It
voltage rating of 250 kV therefore results in a DC current of
400 A, or about 13 % of the links rated power level. This I
0 b

therefore models a typical power level for a HVDC tap.

0.39 0.392 0.394 0.396 0.398 0.4
Time [s]
The AC link is internal to the converter. In this test system
it is operated at a frequency of 500 Hz. Higher frequencies Figure 7. Transformer and arm currents for test system.
shift the harmonic content of the DC current up in the
frequency spectrum, allowing for a higher corner frequency

5334
 TABLE I. CIRCUIT PARAMETERS USED IN SIMULATION.

!"
Parameter Description Value used in simulation

!0
HV1 link voltage 500 kV

8
HV2 link voltage 50 kV

- & -
Power to be transmitted from HV1 to HV2 200 MW

%
Arm inductors 1 mH

%
Peak primary voltage 150 kV

:;
Peak secondary voltage 50 kV

&'(
Frequency of square wave 500 Hz

'<==
Control Margin 25 %

1'<==
Nominal cell voltage 1.8 kV

>'<==
Cell capacitance 2 mF

?@AB@4
Number of cells per arm 280

-.B=<?_DE"
Number or cell rotations per AC cycle 8.2 rot./cycle

/.B=<?_DE"
HV1 filter inductance 8 mH

-.B=<?_DE0
HV1 filter resistance 5

/.B=<?_DE0
HV2 filter inductance 2 mH
HV2 filter resistance 5

The voltage waveforms resulting from the simulation of the By increasing the rotation frequency the voltage deviation
test system can be seen in Fig. 6. The secondary voltage is can be reduced allowing for smaller capacitors. Simultaneously
comparatively smooth, as the diodes clamp the HV2 capacitors the number of lossy switching events increases thereby
voltage across the secondary winding depending on the increasing the system losses.
transformer current direction. Unlike on the HV1 side only 1900
some harmonic content of the DC current will flow through the V Mean
c
DC capacitor, thereby significantly reducing its voltage ripple. V c Maximum
1850 V Minimum
The voltage across the cell stacks can be seen in the bottom c

graph of Fig. 6. They can be noted to contain voltage spikes at

Voltage [V]

the square wave transitions. These are due to the time taken to
1800
ramp the arm currents up and down.
The currents flowing through the arms as well as the
primary and secondary windings of the transformer can be seen 1750
in Fig. 7. The arm and primary currents contain a combination
of triangular and square-wave shapes. This is due to the
1700
magnetisation of the core which is controlled from the primary 0.25 0.252 0.254 0.256 0.258 0.26
side to reduce undesired harmonic content on the secondary Time [s]
side. Furthermore the arm currents can be seen to contain a DC Figure 8. Mean, maximum and minimum cell voltages for top stack during
current offset. This is due to the DC current exchanging energy full power transfer operation.
between the HV1 link and the cell stacks.
III. CONVERTER PERFORMANCE
The mean as well as maximum and minimum cell voltages
of the top stack are shown in Fig. 8. It illustrates the voltage One of the most important performance measures for any
deviation experienced by the cells due to the arm currents. The high power converter is its power efficiency. To evaluate the
maximum and minimum voltages of any one cell at any given feasibility of this DC/DC converter, the losses of the system
time can be brought closer to the mean cell voltage by were estimated, using the simulation results and device specific
increasing the cell rotation frequency. The rotation frequency power loss curves. Since this type of equipment is expected to
denotes how often cell duties are switched around, without remain in service for 20 years or more, the power losses it
varying the total voltage generated by the stack. incurs are a very significant component of the lifetime cost of
ownership. The losses of the main components of the circuit

5335
have been analysed, namely: the DC filters, cell stacks, arm B. Transformer Losses
inductances, transformer and rectifier. The transformer losses were modelled separately from the
A. Semiconductor Losses time-domain simulation in Matlab. The method used for
calculating the core losses was the modified Steinmetz equation
For the cell stacks, the semiconductor losses are assumed to
[15]. The model assumes a transformer with a central round
be dominant. These were calculated using device specific
core leg. The primary and secondary windings are fitted around
conduction voltage drop and switching loss data expressed as
this on top of one another, with appropriate insulation distances
functions of current. The current measurement from the time
between them. The magnetic circuit is completed through two
domain Simulink model was used to calculate the losses of each
half legs on opposite sides of the windings. The core is assumed
individual switch and anti-parallel diode. This method assumes
to be constructed from AK Steel Lite Carlite M-2 electrical
that the losses do not have a significant impact on the current
steel with a lamination thickness of 0.18 mm and a peak
and voltage waveforms in the simulation. The device used in
operational flux-density of 1.62 T. The windings use round
the cells for this set of results was the Mitsubishi HVIGBT
copper Litz wire. The number of strands per bundle were
module CM1200HA-66H.
calculated to result in the minimal AC resistance of the winding
The losses in the rectifier were similarly calculated using as per [16].
data for the Mitsubishi soft recovery diode FD3000AU-120DA.
The model aims to provide a simplified method for
Each arm in the rectifier has to be able to withstand the HV2
analysing transformer losses for varying frequency square-
link voltage. Thus 13 diodes were modelled in series for each
wave applications. One of the biggest limitations of the model
arm of the rectifier.
however is the lack of a thermal analysis. As such temperature
The results for the cell stacks as well as the rectifier are is not taken into account when estimating the material specific
presented in Table II. The switching losses in the cell stacks can losses nor is cooling equipment included in the volume of the
be seen to be of similar magnitude to their conduction losses. transformer. Furthermore an even flux density across the core
In a typical DC/AC modular converter such as the MMC, this is assumed. Parasitic capacitance effects in the windings are not
is not the case, as such converters are operated to generate a modelled, but warrant further work to investigate the effects of
50 Hz AC voltage waveform only. The significantly higher the applied square waveforms.
semiconductor losses seen here are a direct result of the
The dimensions of the transformer have been summarised
relatively high AC frequency (500 Hz).
in Table III and the losses in Table IV. The operation at 500 Hz
The switching losses are broken down into two categories: allows for a relatively compact transformer.
first, the switching events associated with generating the
voltages (to both track the current as well as generate the TABLE III. TRANSFORMER PARAMETERS.
primary voltage). Second, the switching events which occur Transformer parameter Value
due to the cell rotation controller. In the latter events the total Primary turns 60
stack voltage generated remains unchanged as one cell is
simply swapped for another. It can be noted that these losses Secondary turns 20
are substantial and are of a similar magnitude to the losses Magnetising inductance 1.19 H
incurred to generate the voltages. Cross sectional area of core leg 0.77 m2
The rectifiers losses are significantly lower, mainly due to Outer height of transformer 1.7 m
two reasons: first, the devices forward conduction loss is much Outer width of transformer 3.1 m
lower compared that of the IGBTs. Furthermore although the Outer depth of transformer 0.8 m
rectifier experiences a much larger current magnitude there are
Transformer Volume 4.2 m3
substantially fewer devices in the conduction path than in the
stacks. Core volume 2.86 m3
Copper volume 0.03 m3
TABLE II. SEMICONDUCTOR LOSSES IN STACKS AND RECTIFIER
C. Passive Components
Loss type Stacks Rectifier
The inductors have been modelled as brooks coils. To make
Conduction Losses [MW] 1.40 0.4 them comparable, they have a common current density in their
Switching Losses [MW] 1.55 0 turns, of 1.6 MA m-2. The turns were assumed to be round and
Due to Voltage generation [MW] 0.73 - made of copper. The packing factor for the winding has been
Due to Cell rotation [MW] 0.82 - modelled as 50 %. The volume of each inductor depending on
its application has been summarised in Table V. Even though
Total [MW] 2.95 0.4 the HV2 filter inductance is four times smaller in terms of

5336
 TABLE IV. ELECTRICAL LOSSES IN TRANSFORMER. three-phase modular DC/AC converters. Considering that the
Loss type Transformer DC/DC converter presented in this paper operates at a higher
frequency, its system efficiency is favourable in comparison
Core Losses [kW] 350 with a front-to-front arrangement also.
Winding Losses [kW] 798
The losses impose a lifetime running cost on a converter.
Total [kW] 1148
Considering their power ratings and expected lifetime of at least
Efficiency 99.4% 20 to 25 years, a high efficiency is vital to reduce the overall
inductance (see Table I), its volume is about seven times larger. cost of operation. From this point of view losses in excess of
To maintain the same current density in the turns the cross 2 % may well be too high to make the converter feasible.
sectional area has to be significantly larger as the DC current Therefore it will be important to further reduce the losses of the
on the HV2 side is 10 times larger than on the HV1 side. system.
The measures of the volume provided only take the outer Looking at the loss breakdown for this DC/DC converter it
dimensions of the coil into account. As particularly the filter can be noted that 65 % of the total losses are incurred in the cell
inductors will operate at relatively high voltages they will also stacks. Of this in turn about half is due to the switching of the
require significant voltage insulation. The volume for this will cells. An efficiency improvement could thus be found by
far outweigh the volume of the actual coil. lowering the AC frequency. This will however lead to increased
cell capacitances, requiring more volume for the stacks. The
TABLE V. INDUCTOR PARAMETERS. transformer also, will increase in volume as its cores cross
Inductor Coil Volume [m3] sectional area will have to increase to accommodate the
increase in flux density [10].
HV1 Filter 0.7
HV2 filter 4.7 The cell rotation frequency contributes about half of the
total switching losses. A rotation frequency reduction can
Arm inductance 0.4 reduce the losses but will mean that the maximum and
The conduction losses for the filters and the arm inductors minimum cell voltages will deviate further away from the mean
have been summarised in Table VI. As all the inductors are of cell voltages. This in turn increases the voltage deviation of the
a relatively low value, the losses are consequently low capacitor, unless the cell capacitance is increased.
compared to the transformer and semiconductor losses.
The use of square-waves in this converter makes it a
TABLE VI. LOSSES INCURRED IN PASSIVES. feasible single-phase design. This in turn can provide
significant advantages over a front-to-front arrangement as
Component Loss [kW] presented in [10]. In the latter three phases per converter are
Total for both HV1 filters 3.64 used. When installed in a converter hall the cell stacks of
HV1 Filter Inductor 1.82 different phases have to be separated by a considerable
HV1 Filter Resistor 0.15 distance, to avoid flash-overs. Thus a single-phase arrangement
can provide a significant volume reduction, making it more
Total for both HV2 filters 23.29
suitable for off-shore applications.
HV2 Filter Resistor 11.55
HV2 Filter Inductor 0.09 V. CONCLUSION
Arm inductors (total) 1.58 The paper presents a DC/DC converter topology which is
Total Losses in Passives 28.51 suitable for HVDC tap applications. The converter generates a
square-wave current, using modular cell technology, which is
IV. DISCUSSION OF RESULTS passed through a transformer. The cell stacks as well as the
transformer provide parts of the overall voltage-step, allowing
The total losses for the DC/DC converter, including the for large step ratios (greater than 5:1). Since the square-wave is
semiconductor losses for the cell stacks and the rectifier as well an internal system parameter a frequency higher than 50 Hz can
as the transformer, arm inductor and filter losses, sum to 4.53 be utilised to reduce the transformer and converter volume.
MW giving an estimated system efficiency of 97.7 %. This
compares favourably with the efficiency of another DC/DC Details of the converters method of operation and control
converter with a 10:1 step ratio as described in [17]. structure were introduced. Modular cell stacks are used as
controlled voltage sources to generate the voltage across the
The front-to-front arrangement presented in [9] utilises an primary of the transformer and to control the system currents.
AC frequency of 350 Hz and achieves a system efficiency of The converter operates with square current and voltage
97.6 %. That system consists of two front-to-front connected

5337
waveforms. Ideally these will transition instantaneously
between their limits. As the current paths contain a significant
amount of inductance from the arm inductors and the leakage
inductance of the transformer, the current waveform requires
additional voltage capabilities in the cell stacks to allow for a
quick transition.
Through simulation, a 200 MW, full scale converter
operating with a step-ratio of 10:1 and an internal AC frequency
of 500 Hz has been demonstrated. The simulation was used to
confirm the operability of the proposed converter and its
controller. Device specific loss curves and simulation data were
used in an extensive loss analysis to investigate the converters
performance.
The test-system has been found to operate at an efficiency
of 97.7 %. This compares favourably with other HVDC DC/DC
topologies presented in the literature. A further efficiency
improvement could be achieved by reducing the switching
losses, presently responsible for about a quarter of the total
losses. This could be done by reducing the AC frequency.
(CIPS), 2012 7th International Conference on , vol., no., pp.1,6, 6-8
March 2012
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This step would however significantly increase the volume

of the cells capacitors and the transformer. The single phase
design of the converter allows for a compact design which
would be counteracted by lower the AC frequency. A compact
converter design may be particularly for off-shore applications.
Therefore the relatively high switching losses can be seen to be
a traded-off for a smaller converter footprint.
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