Unit 7

Multi-Level Gate Circuits /

NAND and NOR Gates
Ku-Yaw Chang
canseco@mail.dyu.edu.tw
Assistant Professor, Department of
Computer Science and Information Engineering
Da-Yeh University
 Contents
7.1 Multi-Level Gate Circuits
7.2 NAND and NOR Gates
7.3 Design of Two-Level Circuits Using NAND
and NOR Gates
7.4 Design of Multi-Level NAND and NOR Gate
Circuits
7.5 Circuit Conversion Using Alternative Gate
Symbols
7.6 Design of Two-Level, Multiple-Output
Circuits
7.7 Multiple-Output NAND and NOR Circuits

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7.4 Design of Multi-Level NAND-
and NOR-Gates Circuits
Multi-Level NAND-gate circuits
Simplify the switching function to be realized.
Design a multi-level circuit of AND and OR gates. The
output gate must be OR. AND-gate outputs cannot be
used as AND-gate inputs; OR-gate outputs cannot be
used as OR-gate inputs.
Number the levels starting with the output gate as
level 1. Replace all gates with NAND gates, leaving
all interconnections between unchanged. Leave the
inputs to levels 2, 4, 6, unchanged. Invert any
literals which appear as inputs to levels 1, 3, 5,

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 Multi-Level NAND-gate circuits

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 Contents
7.1 Multi-Level Gate Circuits
7.2 NAND and NOR Gates
7.3 Design of Two-Level Circuits Using NAND
and NOR Gates
7.4 Design of Multi-Level NAND and NOR Gate
Circuits
7.5 Circuit Conversion Using Alternative Gate
Symbols
7.6 Design of Two-Level, Multiple-Output
Circuits
7.7 Multiple-Output NAND and NOR Circuits

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7.5 Circuit Conversion Using
Alternative Gate Symbols
An inverter can be represented by

Inversion bubble
At the input
At the output

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 Alternative Gate Symbols
AND, OR, NAND, and NOR gates
Based on DeMorgans law

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 Alternative Gate Symbols
Why alternative symbols?
Facilitate the analysis and design of NAND and NOR
gate circuits

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 NAND Gate Circuit Conversion

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 Conversion to NOR Gates

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 Conversion of AND-OR Circuit to
NAND Gates
Convert all AND gates to NAND gates
Adding an inversion bubble at the output
Convert all OR gates to NAND gates
Adding inversion bubbles at the inputs
An inverted output drives an inverted input
No further action

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 Conversion of AND-OR Circuit to
NAND Gates
A non-inverted gate output drives an
inverted gate input or vice versa
Insert an inverter
A variable drives an inverted input
Complement the variable

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 Conversion of AND-OR Circuit to
NAND Gates

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 Contents
7.1 Multi-Level Gate Circuits
7.2 NAND and NOR Gates
7.3 Design of Two-Level Circuits Using NAND
and NOR Gates
7.4 Design of Multi-Level NAND and NOR Gate
Circuits
7.5 Circuit Conversion Using Alternative Gate
Symbols
7.6 Design of Two-Level, Multiple-Output
Circuits
7.7 Multiple-Output NAND and NOR Circuits

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7.6 Design of Two-Level,
Multiple-Output Circuits
The realization of several functions of the
same variables
A more economical realization

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 Multi-Output Function
Given Functions
F1(A, B, C, D) = m(11, 12, 13, 14, 15)
F2(A, B, C, D) = m(3, 7, 11, 12, 13, 15)
F3(A, B, C, D) = m(3, 7, 12, 13, 14, 15)

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 Separate Realizations

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 Multiple-Output Simplification
F1 = AB + ACD
F2 = ABC + CD
F3 = ACD + AB
AB: F1 and F3
CD (F2) can be replaced by ACD + ACD
F2 = ABC + ACD + ACD

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 Multiple-Output Realization

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 Comparison

Gate
Gates Level
Inputs

Separate
9 21 2
Realization

Multiple-Output
7 18 2
Realization

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 Multiple-Output Simplification
If several solutions are available
Try to minimize the total number of gates
required
Choose the one with minimum gates inputs

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 Contents
7.1 Multi-Level Gate Circuits
7.2 NAND and NOR Gates
7.3 Design of Two-Level Circuits Using NAND
and NOR Gates
7.4 Design of Multi-Level NAND and NOR Gate
Circuits
7.5 Circuit Conversion Using Alternative Gate
Symbols
7.6 Design of Two-Level, Multiple-Output
Circuits
7.7 Multiple-Output NAND and NOR Circuits

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7.7 Multiple-Output NAND and
NOR Circuits

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 Homework #1
1. 7.1 6. 7.17
2. 7.3 7. 7.19
3. 7.4 8. 7.20
4. 7.8 9. 7.25
5. 7.10 10. 7.26

Paper Submission, due on March 22, 2004.

Late submission will not be accepted.

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