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9/10/2017 GATE 2018 - Previous Solutions & Video Lectures for FREE: Previous GATE Questions on Shift Registers

ers with Solutions (1987 - Till Date)

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Monday, December 8, 2014

Previous GATE Questions on Shift Registers with


Solutions (1987 - Till Date)

1992
4. The initial contents of the 4 bit serial in serial out, right shift, shift
register shown in figure, are 0110. After three clock pulses are applied, the
contents of the shift register will be

a. 0000
b. 0101
c. 1010
d. 1111
Answer: C
Solution : https://www.youtube.com/watch?v=0VtDZLpnhOM

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1996
2. A pulse train can be delayed by a finite number of clock periods using a
a. Serial In Serial Out shift register
b. Serial In Parallel Out shift register
c. Parallel In serial Out shift register
d. Parallel In parallel Out shift register
Answer: A
Solution :
Adsense

11. A 4 bit shift register, which shifts 1 bit to the right at every clock pulse,
is initialized to values 1000 for (Q0Q1Q2Q3). The D input is derived from
Q0, Q2 and Q3 through two XOR gates as shown in figure.

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9/10/2017 GATE 2018 - Previous Solutions & Video Lectures for FREE: Previous GATE Questions on Shift Registers with Solutions (1987 - Till Date)
a. Write the 4 bit values (Q0Q1Q2Q3) after each clock pulse till the
pattern (1000) reappears on (Q0Q1Q2Q3).
b. To what values should the shift register be initialized so that the
pattern (1001) occurs after the first clock pulse?
Solution : https://www.youtube.com/watch?v=w--
ZTa4Udk0

1997
15. Circuit shown in the figure is an NMOS shift register. All transistors are
NMOS enhancement type with threshold voltage VT = 1 volt. Supply used
is VDD = 5 volts.

Two non- overlapping clocks 1 and 2 are as shown in the figure is and
have large pulse widths.
GATEpaper's Treasure All capacitors are initially discharged and the Vin = 0 volts is applied. If
2016 (19) values of capacitors are C1 = 2 pF and C2 = 1 pF. Find out voltage VC2 on
2015 (34) capacitor C2 after 2 goes low. Neglect body effect on VT in your
2014 (143) evaluation.
December (14)
Solution : https://www.youtube.com/watch?
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2006
November (12)
October (20) 4. For the circuit shown, two 4-bit parallel in serial out shift registers
September (7) loaded with the data shown are used to fed the data to a full adder. Initially,
August (8)
all the flip-flops are in clear state. After applying two clock pulses, the
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July (5)
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May (20)
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March (24)

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9/10/2017 GATE 2018 - Previous Solutions & Video Lectures for FREE: Previous GATE Questions on Shift Registers with Solutions (1987 - Till Date)

a. 0, 0
b. 0, 1
c. 1, 0
d. 1, 1
Answer: D
Solution : https://www.youtube.com/watch?
v=8xaQJ8NM_p4

Posted by GATE paper at 15:14

Labels: GATE Questions, Shift Registers

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