International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882 1045

Volume 4, Issue 10, October 2015

Efficient Design of FIR Filter using Modified Booth Multiplier

Nivea Thankachan1, Smitha Cyraic2
1
PG Student, Dept. of Electronics and Communication,
Viswajyothi College of Engineering and Technology Ernakulam, India
2
Asst.Profesor, Dept. of Electronics and Communication,
Viswajyothi College of Engineering and Technology Ernakulam, India

Abstract modified booth multiplier performs the computations

Finite Impulse Response filters are the most important
element in signal processing and communication. Area
optimization and speed are the key requirements of Finite
Impulse Response filters. Finite Impulse Response filter
involves multiplications, additions and shifting
operations. As the multiplier is the slowest element in the
system, it will affect the performance of the FIR filter. In
this paper, Finite Impulse Response filter based on
modified Booth multiplier is designed and compared with
conventional filter, in which former reduces both area and
delay. The design of proposed filter has been carried out
using Radix-8 encoding scheme. The direct form structure
of FIR filter has been used to design the proposed filter as
this approach gives a better performance than common
structures in terms of speed of operation. Here, carry
lookahead adder is used in the FIR filter which further
reduces the delay. In this project, denoising filter is also
designed in Matlab. The proposed filter is simulated and
implemented in Spartan 3 FPGA device.
Index Terms - Digital Signal Processing, FIR filter,
Modified Booth Recoding, Carry Look Ahead adder.
1. INTRODUCTION
Finite Impulse Response (FIR) filters are widely used in
Digital Signal Processing (DSP) applications due to their
stability and linear-phase property. In today scenario, low
power consumption and less area are the most important
parameter for the fabrication of DSP systems and high
performance systems. Nowadays, many finite impulse
response (FIR) filter designs aimed at either low area or
high speed or reduced power consumption are developed.
With the increase in area, hardware cost of these FIR
filters are increasing. This leads to design a low area FIR
filter with the advantage of moderate speed performance.
The implementation of an FIR filter requires three basic
building blocks. They are Multiplication, Addition and
Signal delay. Multipliers consume the most amount of
area in a FIR filter design. As the multiplier is the slowest
element in the system, it will affect the performance of the
FIR filter.
Here, Conventional multipliers are replaced by a modified
Booth multiplier. An efficient implementation of high
speed multiplier using the, Radix-8 modified Booth
algorithm is done. In this project, FIR filter using the
above mentioned multipliers were implemented
separately and their characteristics were analyzed. The
using lesser number of adders and iterative steps. As a
result of which they cover lesser space as compared to the
conventional multiplier. This is a very important criterion
because in the fabrication of chips and high performance
system requires components which are as small as
possible. Modified Booth is twice as fast as conventional
multiplier. It produces only half the number of partial
products (PPs) when compared with an ordinary binary
multiplication. Modified Booth encoding (MBE) scheme
is identified as the most efficient Booth encoding and
decoding scheme.
The direct form structure has been used in designing of
proposed filter as this approach gives a better
performance than common structures in terms of speed of
operation and cost. The design of FIR filter using the
Radix-8 encoding schemes, has been carried out via
Hardware Description Language.
Here, carry lookahead adder is used in the FIR filter which
further reduces the delay. In this project, denoising filter
was also designed in Matlab. The proposed filter is
simulated and implemented in Spartan 3 FPGA device.
2. EXISTING SYSTEM
The conventional design of the FIR filter is shown
in Figure 1.The implementation of an FIR requires three
basic building blocks: Multiplication, Addition and Signal
delay. FIR filter can be expressed as
(1)
Fig.1. Block diagram of conventional FIR filter
Where N represents the filter order, y [n] is the output
signal and bk represents the set of filter coefficients. If x
[n] is the input signal applied, x [n - k] terms are referred
as taps or tapped delay lines. In the conventional design,
present a simple structure of multiplier for FIR filters. It
performs multiplication by generating partial products. If

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 International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
the multiplier digit is a 1, the multiplicand is simply
copied down and represents the product. If the multiplier
digit is a 0 the product is also 0. Therefore the area and
delay will increased. It affects the performance of the FIR
filter.
3. PROPOSED METHOD
As the multiplier is the slowest element in the system, it
will affect the performance of the FIR filter. So, a
modified Booth multiplier is suggested since it reduces
area and it is faster than other conventional multipliers.
The proposed low area-cost FIR filter using a modified
Booth multiplier [2] is shown in Figure 2.
Fig.2 Modified Booth Multiplier Based FIR Filter
A direct form filter is such that at each clock cycle a new
data sample and the corresponding filter coefficient can
be applied to the multipliers inputs. x [n] is given as the
input signal. D-FFs are used as the delay elements.
Modified Booth multiplier block is provided for
multiplying the input signal with the set of filter
coefficients corresponding to the selected filter order.
Then, modified Booth multiplier block will provide the
output signal y [n].
3.1 Floating Point Representation
The coefficients of digital filter are floating point
numbers. The IEEE754 standard is the most widely used
standard for floating point computation, and is followed
by many CPU implementation. The standard defines
formats for representing floating point number and special
values together with a set of floating point operations.
The IEEE754 standard floating-point format consists of
three fieldsa sign bit (S), a biased exponent (E), and a
mantissa (M) . Half-precision numbers have a 1-bit sign,
5-bit exponent, and 10-bit mantissa. The bias will be 15.
Z=(-1^S)*2(E-Bias)*(1.M) (2)
Figure 3 Half- precision floating point format
For example,0.5 can be represented in binary form as
0.10000000.It is represented in floating point form as -1^0
*2^(01111-01110)*1.00000000.
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Volume 4, Issue 10, October 2015
3.2 Modified Booth Multiplier Design
The Modified Booth Multiplier was proposed by O. L.
Macsorley in 1961. The recoding method is widely used
to generate the partial products for implementation of
large parallel multipliers, which adopts the parallel
encoding scheme. The encoding technique in modified
booth algorithm reduces the number of partial products
and thereby reduces the number of additions and pipeline
stages. In MBA process three bits at a time are recorded.
Recoding the multiplier in higher radix is a powerful way
to speed up standard Booth multiplication algorithm. In
each cycle a greater number of bits can be inspected and
eliminated therefore total number of cycles required to
obtain products get reduced. Number of bits inspected in
radix r is given by n = 1 + log2r.
The algorithm used for performing modified booth
multiplication will be:
Pad the LSB of multiplier with one zero.
If n is even pad the MSB with 2 zeroes and if n is
odd pad the MSB by 1 zero.
Divide the multiplier into overlapping groups
Determine partial product scale factor from
modified booth encoding table.
Compute the Multiplicand Multiples
Sum Partial Products
Fig. 4 Architecture of the modified Booth multiplier
Fig 4 shows the architecture of the commonly used
modified Booth multiplier. The inputs of the multiplier
are multiplicand X and multiplier Y. The Booth encoder
encodes input Y and derives the encoded signals. The
Booth decoder generates the partial product using the
encoded signals and the other input X. The carry save
adder computes the last two rows by adding the generated
partial products. The last two rows are added to generate
the final multiplication results using the carry look-ahead
adder.
3.3Modified Booth Multiplication Algorithm (Radix-8)
This Booth multiplier is known as radix-8 [10] because it
perform the 8 different types of operations on the
multiplicand that are +M, +2M, +3M, +4M, 4M, 3M,
2M and M where M denotes the Multiplicand. All the
multiples with except 3M are easily obtainable, by simply
shifting and complementing. The generation of the 3M
(3 multiplicand), which is referred to as a hard multiple,
 International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
cannot be obtained by simple shifting and
complementation. It can be produce either M+2M or
4MM. Here in this project, it is produced by M+2M. For
example of 88 bit multiplication, a simple multiplier
generates the 8 partial product rows, but by radix-8 booth
multiplier it is reduced to 3.It means that radix-8 booth
multiplier reduces the partial product rows by N/3 where
N in number of bits in multiplier.
Table 1 Booth Encoding Table (Radix-8)
Multiply by zero means the multiplicand is multiplied by
0. Multiply by 1 means the product still remains the
same as the multiplicand value. Multiply by -1 means
that the product is the twos complement form of the
number. Multiply by -2 is to shift left one bit the twos
complement of the multiplicand value and multiply by 2
means just shift left the multiplicand by one place.
Multiplying the multiplicand by 3 is equivalent to
addition of multiplicand and left shifted multiplicand by
one digit. Multiply by -3 means addition of twos
complement of multiplicand and shift left one bit the
twos compliment of the multiplicand value. Multiply by
4 means shift left the multiplicand by two places.
Multiply by -4 means shift left the twos complement of
multiplicand by two places.
Fig.5 Bit Pairing as per Radix 8 Booth Recoding
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Volume 4, Issue 10, October 2015
Let the two numbers to be multiplied are X = 25 and Y =
39.
Multiplier X = 25 = 011001
Multiplicand Y = 39 = 100111
X*Y= 975
PP1, PP2, PP3 are the partial products formed. The first
partial product is determined by four digits LSB of
multiplier with an appended zero. This 4 digit number is
1110 which mean that the multiplicand A has to multiply
by -1. To multiply by -1, the process takes twos
complement of the multiplicand value. Hence, the first
partial product is 1100111. All of the partial products will
have 7 bits length. Next, the second partial product is
determined by next four bits i.e. multiply by -3. Multiply
by -3 means addition of twos complement of
multiplicand and shift left one bit the twos compliment of
the multiplicand value. So, the second partial product is
10110101. The third partial product is determined by next
four bits i.e. to multiply by 1. Multiply by 1 means the
partial product will be same as multiplicand. So, the third
partial product is 0011001.The final result will be the
summation of these partial products. Thus the final
product will be 001111001111.
3.4 Carry Lookahead Adder
Here, carry lookahead adder [13] is used in the FIR filter
which further reduces the delay. A carry-lookahead adder
increases speed by reducing the amount of time required
to determine carry bits. The carry-lookahead adder
calculates one or more carry bits before the sum, which
reduces the wait time to calculate the result of the larger
value bitsl.The carry lookahead adder calculate the carry
signal in advance based on the input signal ,thereby it
solves the problem of delay.
3.5Application of FIR Filter
Noise is an unwanted interference in any form of
communication generally degrades the quality of the
information signal Denoising filter was designed in
Matlab.
Fig.6 Denoising
There are so many techniques to improve the signal
quality or to regenerate the signal. In this paper present a
method of denoising using modified booth multiplier
based FIR filter and it is done in matlab.
4. SOFTWARES AND HARDWARES USED
Xilinx ISE, MATLAB are the software used for
simulation and project is implemented using Spartan 3
FPGA.
5. RESULTS
The simulation results of conventional FIR filter,
modified booth multiplier based FIR filter are shown
below.
 International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
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Volume 4, Issue 10, October 2015

5.1 Conventional FIR Filter floating points. So the mantissa part of the coefficients
The simulation results for the conventional FIR filter is and the input will be multiplied in the multiplier part.
obtained as shown in Figure 7

Fig.9 Modified booth multiplier (Radix-8) based FIR

filter
Fig.7 Conventional FIR filter
When rst=1, reset operation is done. When rst=0, the
In this, design a filter having the equation, y(n) = - 0.3183 input value will be enters into the D flipflop and then the
x(n-3) + 0.5 x(n-5) - 0.3183 x(n-7).Since the coefficients corresponding mantissa part will multiplied together. The
-0.3183, 0.5 and -0.3183, are in the floating points. So resultant exponent will be the largest one among them and
they are represented in IEEE standard floating point
the resultant sign bit will be the obtained by taking xor of
representations. They have sign bit, mantissa and the corresponding sign bits. The resultant mantissa will be
exponent parts. The input will be also represented in 0101110011000000000 and the resultant exponent will be
floating points. So the mantissa part of the coefficients 01111 and the sign bit will be 1.Thus the output will be in
and the input will be multiplied in the multiplier part. the form 1.0101110011000000000*2^15.
When rst=1, reset operation is done. When rst=0, the The Design summary for the modified booth multiplier
input value will be enters into the D flipflop and then the
(Radix-8) based FIR filter is obtained as shown in Figure
corresponding mantissa part will multiplied together. The
10
resultant exponent will be the largest one among them and
the resultant sign bit will be the obtained by taking xor of
the corresponding sign bits. The resultant mantissa will be
0101110011000000000 and the resultant exponent will be
01111 and the sign bit will be 1.Thus the output will be in
the form 1.0101110011000000000*2^15
The Design summary for the conventional FIR filter is
obtained as shown in Figure 8 Fig.10 Design Summary of Modified booth multiplier
(Radix-8) based FIR filter

By analyzing the design summary (Figure 10) it is clear

that area of the modified booth multiplier (Radix-8) based
FIR filter is very high and the number of slices is 582 and
number of 4 input LUTs is 1065.
By analyzing the timing report it is clear that delay of the
modified booth multiplier (Radix-8) based FIR filter is
Fig.8 Design Summary of Conventional FIR filter low compared to conventional FIR filter and radix-4 FIR
By analyzing the design summary (Figure 8) it is clear that filter and is 59.560 ns.
area of the Conventional FIR filer is very high and the 5.3Application
number of slices is 510 and number of 4 input LUTs is Denoising was done in Matlab. The Figure 11 shows the
918. original signal with frequency 1 KHz.
By analyzing the timing report (Figure 4.3) it is clear that
delay of the Conventional FIR filer is very high and is
61.678 ns.
5.2 Modified Booth Multiplier (Radix-8) Based FIR Filter
The simulation results for the modified booth multiplier
(Radix-8) based FIR filter is obtained as shown in Figure 9
In this, design a filter having the equation, y(n) = - 0.3183
x(n-3) + 0.5 x(n-5) - 0.3183 x(n-7).Since the coefficients
-0.3183, 0.5 and -0.3183, are in the floating points. So
they are represented in IEEE standard floating point
representations. They have sign bit, mantissa and
Fig.11 Original Signal
exponent parts. The input will be also represented in

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 International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
The Figure 12 shows the original signal combined with
high frequency signal.
Fig.12 Original signal combined with high frequency
noisy signal
Noisy signal has frequency of 10 KHz. These noisy signal
is passed to proposed filter. The Figure 13 shows the
filtered signal.
[10] Paladugu Srinivas Teja Design of Radix-8 Booth Multiplier
using Koggestone
Applications EEIEJ, Vol. 1, No. 1, February 2014.
Fig.13 Filtered signal
Noisy signal shown in the Figure 13 was passed through
the modified booth multiplier based FIR filter and the
output will be the signal, which is free from the noise.
6. CONCLUSION
A highly area-efficient Finite Impulse Response
filter based on modified Booth multiplier is designed and
compared with conventional filter, in which former
reduces both area and delay. The design of proposed filter
has been carried out using, Radix-8 encoding scheme. The
results show that the modified Booth multiplier based FIR
(radix-8) filter leads to smallest area and delay. The FIR
filter is modified using carry lookahead adder, which
further reduces the delay. This FIR filter is also applicable
in communication purpose. Denoising filter is also
designed using Matlab.
REFERENCES
[1] D. Jaya Kumar, Dr.E. Logashanmugam, Performance
Analysis of FIR filter using Booth Multiplier, IEEE July 2014.
[2] Shelja Jose, Shereena Mytheen ,Modified Booth Multiplier
Based Low-Cost FIR Filter Design International Journal of
Engineering Science and Innovative Technology (IJESIT)
Volume 3, Issue 5, September 2014.
[3] Sarita Chouhan1,Yogesh Kumar2, Low power designing of
FIR filters, ISSN No: 2250-3536 ,May 2012.
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Volume 4, Issue 10, October 2015
[4] Kavita, Jasbir KaurDesign and Implementation of an
Efficient Modified Booth Multiplier using VHDL Proceedings
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[5] Sukhmeet Kaur, Sumanand Manpreet Signh Manna
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AUTHOR
Nivea Thankachan, Pursuing M.Tech in VLSI and
Embedded Systems, Viswajyoythi College of Engineering
and Technology, Vazhakulam, Kerala
email: niveathankachan@gmail.com