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IES IPS ACADEMY

DEPARTMENT OF ELECTRONICS & COMMUNICATION


Name: Branch: EC Year: IV
Subject: VLSI Design Course: BE Semester: VII
Subject Code: EC705

EXPERIMENT- 1

AIM: -Design an NMOS generator using tanner EDA.

APPARATUS REQUIRED: - Tanner EDA.

THEORY: -

N-type metal-oxide-semiconductor logic uses n-type metal-oxide-semiconductor field


effect transistors ( MOSFET) to implement logic Gates and other digital circuits. NMOS
transistors have four modes of operation: cut-off (or sub-threshold), triode, saturation
(sometimes called active), and velocity saturation.

The n-type MOSFETs are arranged in a so-called "pull-down network" (PDN) between
the logic gate output and negative supply voltage, while a resistor is placed between the
logic gate output and the positive supply voltage. The circuit is designed such that if the
desired output is low, then the PDN will be active, creating a current path between the
negative supply and the output.

MOS Transistor:
MOS transistors conduct electrical current by using an applied voltage to move charge
from the source side to the drain side of the device. A MOS transistor is a majority-carrier
device In an n-type MOS transistor, the majority carriers are electrons In a p-type MOS
transistor, the majority carriers are Holes
Threshold voltage:
It is defined as the minimum Vgs (gate to source) voltage at which an MOS device begins
to conduct (turn on)
MOS transistor symbols

Fig1.1
IES IPS ACADEMY
DEPARTMENT OF ELECTRONICS & COMMUNICATION
Name: Branch: EC Year: IV
Subject: VLSI Design Course: BE Semester: VII
Subject Code: EC705

Fig1.2
Steps to perform experiment:-

1. Draw the NMOS generator schematic in S-edit window.


2. Generate the T-spice code for the Schematic drawn, by clicking on T button.
3. Insert the necessary commands like File, Analysis, Output etc.
4. Run the code using Run Simulation button.
5. Analyse the generated waveform

SCHEMATIC FOR NMOS GENERATOR:-

T-SPICE CODE

* SPICE netlist written by S-Edit Win32 Demo 9.12


* Written on Feb 3, 2014 at 11:05:50

* Waveform probing commands


IES IPS ACADEMY
DEPARTMENT OF ELECTRONICS & COMMUNICATION
Name: Branch: EC Year: IV
Subject: VLSI Design Course: BE Semester: VII
Subject Code: EC705
.probe
.options probefilename="nmos.dat"
+ probesdbfile="C:\Program Files\Tanner EDA\Demo\T-Spice\tutorial\schematic\nmos.sdb"
+ probetopmodule="Module0"

* Main circuit: Module0


M1 out in Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
R2 Vdd out 50 TC=0.0, 0.0
v3 Vdd Gnd 5.0
v4 in Gnd 0.0
.include "C:\Program Files\Tanner EDA\Demo\T-Spice\tutorial\schematic\ml5_20.md"
.dc v4 0 5 0.5 sweep v3 0 5 0.5
.print dc i(M1,out)
* End of main circuit: Module0
IES IPS ACADEMY
DEPARTMENT OF ELECTRONICS & COMMUNICATION
Name: Branch: EC Year: IV
Subject: VLSI Design Course: BE Semester: VII
Subject Code: EC705

TSPICE SIMULATION STATUS


Simulation status
T-Spice - Tanner SPICE
Version Demo 9.12
Product Release ID: T-Spice Win32 Demo 9.12.20040112.04:26:10
Copyright (c) 1993-2004 Tanner Research, Inc.

Parsing "C:\Program Files\Tanner EDA\Demo\T-


Spice\tutorial\schematic\Module0.sp"
Including "C:\Program Files\Tanner EDA\Demo\T-
Spice\tutorial\schematic\ml5_20.md"
Warning : unused model "pmos"

Probing options:
probefilename = nmos.dat
probesdbname = C:\Program Files\Tanner EDA\Demo\T-
Spice\tutorial\schematic\nmos.sdb
probetopmodule = Module0

Device and node counts:


MOSFETs - 1 MOSFET geometries - 1
BJTs - 0 JFETs - 0
MESFETs - 0 Diodes - 0
Capacitors - 0 Resistors - 1
Inductors - 0 Mutual inductors - 0
Transmission lines - 0 Coupled transmission lines - 0
Voltage sources - 2 Current sources - 0
VCVS - 0 VCCS - 0
CCVS - 0 CCCS - 0
V-control switch - 0 I-control switch - 0
Macro devices - 0 External C model instances - 0
Subcircuits - 0 Subcircuit instances - 0
Independent nodes - 1 Boundary nodes - 3
Total nodes - 4

*** 1 WARNING MESSAGE GENERATED DURING SETUP

Warning : Negative mos conductance for device M1


v(d), v(g), v(s), v(b) = 0.000000e+000 0.000000e+000
0.000000e+000 0.000000e+000
vds, vgs, vbs = 0.000000e+000 -0.000000e+000 -0.000000e+000
IES IPS ACADEMY
DEPARTMENT OF ELECTRONICS & COMMUNICATION
Name: Branch: EC Year: IV
Subject: VLSI Design Course: BE Semester: VII
Subject Code: EC705
gds, gm, gmbs = -1.137440e-001 9.489429e-013 -9.489493e-013
ids = -1.137440e-013

* SIMULATION STATISTICS:
* DC operating point
* Total DC operating points =1
* Total Newton iterations =1
* Total Current evaluations =3
* DC sweep
* DC transfer points = 120
* Successful transfer points = 120
* Failed transfer points =0
*
* Matrix statistics: OP DC
* Matrix factors 1 186
* Matrix solves 1 186
* Size 1 1
* Initial elements 1 1
* Final elements 1 1
* Fill-ins 0 0
* Initial density 100.00% 100.00%
* Final density 100.00% 100.00%
*
* Total matrix factorizations = 187
* Total matrix-vector solves = 187
* Total matrix solve time (seconds) = 0
*
* T-Spice process times
* Newton solver 0.02 seconds
* Current evaluations 0.00 seconds
* Jacobian construction 0.02 seconds
* Linear solver 0.00 seconds
*
Parsing 0.01 seconds
DC Analysis 0.02 seconds
Overhead 0.00 seconds
-----------------------------------------
Total 0.03 seconds

Simulation completed with 2 Warnings

W EDIT WAVEFORM VIEWERTRANSFER CHARACTERISTICS


IES IPS ACADEMY
DEPARTMENT OF ELECTRONICS & COMMUNICATION
Name: Branch: EC Year: IV
Subject: VLSI Design Course: BE Semester: VII
Subject Code: EC705

T-SPICE CODE

* SPICE netlist written by S-Edit Win32 Demo 9.12


* Written on Feb 3, 2014 at 11:05:50

* Waveform probing commands


.probe
.options probefilename="nmos.dat"
+ probesdbfile="C:\Program Files\Tanner EDA\Demo\T-Spice\tutorial\schematic\nmos.sdb"
+ probetopmodule="Module0"

* Main circuit: Module0


M1 out in Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
R2 Vdd out 50 TC=0.0, 0.0
v3 Vdd Gnd 5.0
v4 in Gnd 0.0
.include "C:\Program Files\Tanner EDA\Demo\T-Spice\tutorial\schematic\ml5_20.md"
.dc v3 0 5 0.5 sweep v4 0 5 0.5
.print dc i(M1,out)
*End of main circuit: Module0
IES IPS ACADEMY
DEPARTMENT OF ELECTRONICS & COMMUNICATION
Name: Branch: EC Year: IV
Subject: VLSI Design Course: BE Semester: VII
Subject Code: EC705

TSPICE SIMULATION STATUS

T-Spice - Tanner SPICE


Version Demo 9.12
Product Release ID: T-Spice Win32 Demo 9.12.20040112.04:26:10
Copyright (c) 1993-2004 Tanner Research, Inc.

Parsing "C:\Program Files\Tanner EDA\Demo\T-


Spice\tutorial\schematic\Module0.sp"
Including "C:\Program Files\Tanner EDA\Demo\T-
Spice\tutorial\schematic\ml5_20.md"
Warning : unused model "pmos"

Probing options:
probefilename = nmos.dat
IES IPS ACADEMY
DEPARTMENT OF ELECTRONICS & COMMUNICATION
Name: Branch: EC Year: IV
Subject: VLSI Design Course: BE Semester: VII
Subject Code: EC705
probesdbname = C:\Program Files\Tanner EDA\Demo\T-
Spice\tutorial\schematic\nmos.sdb
probetopmodule = Module0

Device and node counts:


MOSFETs - 1 MOSFET geometries - 1
BJTs - 0 JFETs - 0
MESFETs - 0 Diodes - 0
Capacitors - 0 Resistors - 1
Inductors - 0 Mutual inductors - 0
Transmission lines - 0 Coupled transmission lines - 0
Voltage sources - 2 Current sources - 0
VCVS - 0 VCCS - 0
CCVS - 0 CCCS - 0
V-control switch - 0 I-control switch - 0
Macro devices - 0 External C model instances - 0
Subcircuits - 0 Subcircuit instances - 0
Independent nodes - 1 Boundary nodes - 3
Total nodes - 4
*** 1 WARNING MESSAGE GENERATED DURING SETUP

Warning : Negative mos conductance for device M1


v(d), v(g), v(s), v(b) = 0.000000e+000 0.000000e+000
0.000000e+000 0.000000e+000
vds, vgs, vbs = 0.000000e+000 -0.000000e+000
-0.000000e+000
gds, gm, gmbs = -1.137440e-001 9.489429e-013 -9.489493e-
013
ids = -1.137440e-013
* SIMULATION STATISTICS:

* DC operating point
* Total DC operating points =1
* Total Newton iterations =1
* Total Current evaluations =3
* DC sweep
* DC transfer points = 120
* Successful transfer points = 120
* Failed transfer points =0
*
* Matrix statistics: OP DC
* Matrix factors 1 243
* Matrix solves 1 243
* Size 1 1
IES IPS ACADEMY
DEPARTMENT OF ELECTRONICS & COMMUNICATION
Name: Branch: EC Year: IV
Subject: VLSI Design Course: BE Semester: VII
Subject Code: EC705
* Initial elements 1 1
* Final elements 1 1
* Fill-ins 0 0
* Initial density 100.00% 100.00%
* Final density 100.00% 100.00%
*
* Total matrix factorizations = 244
* Total matrix-vector solves = 244
* Total matrix solve time (seconds) = 0.016
*
* T-Spice process times
* Newton solver 0.03 seconds
* Current evaluations 0.01 seconds
* Jacobian construction 0.00 seconds
* Linear solver 0.02 seconds
*

Parsing 0.00 seconds


DC Analysis 0.03 seconds
Overhead 0.00 seconds
-----------------------------------------
Total 0.03 seconds

Simulation completed with 2 Warnings

W EDIT WAVEFORM VIEWEROUTPUT CHARACTERISTICS


IES IPS ACADEMY
DEPARTMENT OF ELECTRONICS & COMMUNICATION
Name: Branch: EC Year: IV
Subject: VLSI Design Course: BE Semester: VII
Subject Code: EC705

Viva Questions:-

Q.1 What is MOSFET?


Q.2 What is the difference between FET and MOSFET?
Q.3 What is NMOS?
Q.4 Explain different operating regions of NMOS.
Q.5 Give the comparison between BJT and MOSFET.