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V1
9Vdc
U1 16 15
VD ZE
D* NE
C3 0 R
14 10
3 SIG_IN DEMO_OUT
0.1u C1 4 COMP_IN Rs
V2
VOFF = 0 0.01u 6 VCO_OUT 2
C1 COMP1_OUT 100k
VAMPL = 7 13
FC = 11 C2 COMP2_OUT 1 R3
R1 VS
PH_PULSE 0
MOD = 12 S* VCO_IN 9 10k
FM = R1 10k 5 R2
0 INH
0 8 CD4046 C2
0.1u
You will use the headphone output of your laptop and Cool Edit software
as the source V 2 that provides the FM signal for demodulation. Here is a
possible layout:
In this layout, pins 5 and 8 are connected to ground simply by bending and
soldering them to the adjacent ground buss on the backside of the PC
board. Pin 16 connects to the 9V buss in a similar fashion. Also, pin 9
connects to the junction of R3 and C2 on the backside of the PC board.
2. With no input to the PLL, the VCO in a 4046 PLL made with Phase
Comparator I idles at a center frequency, f o , that depends mainly on R1
and C1 , but also varies with the power supply voltage, Vcc , and from chip to
chip. The data sheet for the CD4046BE describes typical dependence of f o
on these parameters in the form of a parameterized log-log plot. With the
values for the circuit of part 1, note that the plot indicates a typical value for
f o lies somewhere between 1kHz and 10 kHz , although a note on the plot
indicates that the values of f o for a particular chip can vary by 50% from
the value indicated on the chart.
With the input of your PLL circuit shorted to ground (with a black alligator
clip, for instance), display the output voltage (that is, the voltage at pin 10
and the voltage across the resistor Rs ) in the FFT Analyzer of the Real Time
Analyzer to determine the approximate value of f o . Ideally, the output
voltage should be absolutely zero with no input to the demodulator. In
practice, a small amount of the VCO output leaks through, enough to let
you observe the VCO frequency of oscillation. Because this leakage signal is
very small, its Fourier spectrum will appear noisy. Once you have identified
the frequency spike corresponding to the VCO frequency, you should
adjust the frequency range of the FFT Analyzer to focus in on the range
near the VCO frequency so that you can use the cursor to obtain a
reasonably accurate measurement of its value. Include a screen shot of the
Fourier spectrum of the output voltage, and record your estimate for f 0 .
Why not observe the output of the VCO directly at pin 4? Because the
input impedance of the microphone input on your laptop is low enough to
affect the operation of the VCO, a very low power CMOS circuit that is
easily disturbed. The output terminal, pin 10, on the other hand, is driven
by a voltage follower, a circuit that is often used to replicate a voltage from
a circuit easily disturbed by measurement as the Thevenin voltage of a
circuit with a low Thevenin resistance.
A solution:
1 2 f L
fC
1
where
f L fo
1 R3 C2
f L fC f f L fC
A solution:
1 2 f L 1 2 9000 Hz
fC 1200 Hz
2 1 2 103 sec
A solution:
1 1
B 2 f 2 f m 2 f 1 2 400 Hz 1 1.6 kHz
1
With a center frequency of fo 9.0 kHz , the range of frequencies
estimated according to Carson's rule should be:
B B
fo f fo
2 2
Here is a screen shot of the Fourier spectrum of the input to the PLL:
The main Fourier spectrum of the input signal lies in the range
6.5 kHz f 11.5 kHz , in only fair agreement with the approximate
frequency range calculated from Carson's rule:
8.2 kHz f 9.8 kHz . The extra bandwidth may be due to
harmonics introduced by nonlinear distortion in the audio system in
my laptop. Certainly, the secondary spectrum centered around
18 kHz reflects second harmonic nonlinear distortion in the
imperfect audio system. Notice, however, that the peak of the
secondary spectrum is more than 50 dB below the peak of the main
spectrum, more than 100 times smaller in amplitude. The
logarithmic vertical scale magnifies, for good purpose, small
amplitudes so that they are more visible.
5. As you feed the FM modulated signal generated in part 4 from Cool Edit
through the headphone output on your laptop to the input of the PLL, use
the Realtime Analyzer Oscilloscope to display the PLL output, which should
show the modulating signal, a 400 Hz sine wave. For best results, make the
output from your large. Include a screen shot of the output waveform, as
well as a check of its frequency calculated from the period of the displayed
sinusoid.
A solution:
A solution:
A solution:
Here is a screen shot of the PLL output waveform at low deviation
(early):
A solution:
Here is a screen shot of the PLL output waveform with low carrier
frequency (early), but after capture:
Here is a screen shot of the PLL output waveform with high carrier
frequency (late):
These two screen shots show that the PLL can demodulate FM
signals with a broad range of carrier frequencies, a range of
somewhat less than 2 to 1. In contrast, ratio detectors, which rely on
tuned circuits for operation, can function over a range of perhaps
10 % of the carrier frequency.
9. OrCAD PSpice 10.0 Demo does not have a PSpice model for the 4046 PLL
IC. Thus, use instead the Cadence PSD 15.0, full strength industrial software
available on the computers available in Simrall 131. The Cadence software
uses the same Capture schematic capture environment as OrCAD PSpice
Demo 10, but includes the PSpice model CD 4046 in the MIX_MISC library.
In the simulation, use the component values shown in part 1. To produce
the FM modulated input signal, use the PSpice single frequency FM voltage
source, VSFFM, available in the SOURCE library. Set the carrier frequency to
the value you used in the earlier parts. Set f m 400 Hz and f 400 Hz so
that the modulation index 1 . Note that the MOD property for the
VSFFM source corresponds to the modulation index, . For the moment,
set the amplitude of the source to zero so that there is no input to the PLL,
attach a voltage probe to the VCO output, run a transient simulation for a
few milliseconds, and from the resulting plot determine the approximate
value for the center frequency f o , the frequency at which the VCO
oscillates when no input is present. Recall the large tolerance on the center
frequency of particular CD4046BE chips mentioned in the data sheet. Thus,
the VCO idle frequency produced by the simulation can be far different
than the one that you measured. As a consequence, the simulated PLL may
not capture and lock onto the FM modulated input signal during the
simulation. To deal with this problem, adjust the value of capacitor C1 until
the simulated VCO frequency roughly matches the center frequency you
measured for your particular circuit. Note and record this value. Once you
have accomplished adjustment of the center frequency of the simulation,
set the amplitude of the VSFFM source to 0.5V , add voltage probes to the
output of the PLL (pin 10) and to the top of the VSFFM source, and run the
simulation for about 10 cycles of the modulation frequency, f m 400 Hz .
Set the maximum step size during simulation to 1 sec . Ignore the
countless simulation warnings. Include screen shots of your Capture
schematic and of your simulation output plots. The output voltage of the
PLL should be roughly sinusoidal with frequency 400 Hz . Include, in
addition, a screen shot of the Fourier spectrum of the FM output of the
VSFFM PSpice source and compare this spectrum with the result of
Carsons rule that you calculated in part 4.
A solution:
Note that the PLL locks in after about 8 m sec . The output waveform
is roughly sinusoidal with period of about 2.5 m sec , which
corresponds to a frequency of about 400 Hz .