Succeeding in Implementing a Low-Power SoC with Power

Islands

Bruno Bailly, Andra Bonzo,

Frdric Bunoz, Guillaume Cogniard,
Faustine Coguen, Lucille Engels,
Sbastien Gaubert, Grgoire Gimenez,
Rmi Malaquin, Hai Yu

Dolphin Integration
Meylan, France

www.dolphin-integration.com

ABSTRACT

With the growth of markets related to the Internet of Things, the requirements in terms of very
low-power consumption for the connected things push SoC/ASIC designers and architects to
hunt down mA, and even A, from specification until first silicon prototype validation.
The level of experience in low-power strategy definition and implementation is very different
between teams. The content of a low-power SoC may vary from one Always-On block driving the
rest of the SoC as an extinction island, up to the first implementation of a closed-loop system to
perform adaptive voltage scaling.
The purpose of this paper is to give an overview of the possible power gains at the different steps
of a SoC development, starting from the requirements, through the choice of the best partitioning
of the SoC into power islands and its synoptic, down to the silicon measurements, with a specific
focus on the RTL to GDSII integration flow.
Dolphin Integration will share traps and tricks, inputs and outputs, and types of models required
at each step in the integration flow for a low-power design: how to implement retention power
islands, how to secure the functionality at SoC level by a combined verification with Synopsys
tools and other solutions.
 Table of Contents
1. Introduction.............................................................................................................................. 3
2. How to Handle Power Optimization........................................................................................ 3
3. SoC Partitioning Into Power Islands........................................................................................ 4
4. Relevance of a Public Benchmark ........................................................................................... 6
5. Low-Power RTL2GDSII Integration Flow.............................................................................. 8
6. Integration Issues in Power Island Construction ................................................................... 14
7. Benchmark Results ................................................................................................................ 17
8. Conclusion ............................................................................................................................. 24
9. References.............................................................................................................................. 25
10. Acronyms............................................................................................................................. 25

Table of Figures
Figure 4-1: Motu-Uta+ functional synoptic.................................................................................... 6
Figure 4-2: Motu Uta+ with an example of power management network..................................... 7
Figure 4-3: Motu Uta+: Synoptics with main integration issues .................................................... 8
Figure 5-1: Low-power RTL2GDSII global integration flow ........................................................ 9
Figure 5-2 : Decision tree for ring vs grid implementation .......................................................... 13
Figure 6-1: Low-Power RTL2GDSII integration flow with Mode Transition Checks ................ 15
Figure 7-1: Motu Uta+ with island implementation (the RTC-AO includes SCU/IWU and the
ICU) .............................................................................................................................................. 17
Figure 7-2: Power integrity check of the power network during mode transitions with a Power
Distribution Network Capacitance of 100 pF ............................................................................... 23
Figure 7-3: Power integrity check of the power network during mode transitions with a Power
Distribution Network Capacitance of 1 nF ................................................................................... 24

Table of Tables
Table 2-1 - Low-Power technique impacts in RTL2GDSII integration flow................................. 4
Table 6-1 Key checks,models and EDA-solution in power island construction for Motu-Uta+16
Table 7-1 Motu-Uta+ application mode table............................................................................ 18
Table 7-2 Motu-Uta+ activity table ........................................................................................... 18
Table 7-3 - Motu-Uta+ power consumption table ........................................................................ 18

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1. Introduction

Splitting a SoC into power islands is an effective technique to reduce dynamic and leakage
power, that has gained in popularity over the past years. The power-island allocation requires a
good knowledge of the embedded functions in an applicative context in order to reach the
optimal power consumption, an identification of models and verifications to be performed in
order to guarantee both the power consumption and the functionality and finally, a mastery of the
use of EDA solutions to automate the verifications that are increased with the number of cases to
cover.

The level of experience in power island definition and implementation is very different between
design teams. The purpose of this paper is to show, using a public benchmark provided by
Dolphin Integration, the main integration issues in a low-power flow and how to solve them
thanks to the existing reference manuals and the expertise of Dolphin Integration in mixed-signal
and logic circuits. Thanks to the public benchmark, design teams will be able to compare
different physical libraries or implementation choices to assess the performance and the lead
time required to apply these technics to their own SoCs.

Dolphin Integration will share traps and tricks, relevant inputs or outputs, and types of models
required (e.g. current profiles during transitions of modes) at each step of the integration flow,
such as: how to reach the targeted low-power gain by progressive adjustments, how to secure the
functionality at SoC level by a combination of verification steps with Synopsys tools (structural
verifications) and other solutions for Mode Transition checks and Noise Propagation checks
(dynamic verification).

2. How to Handle Power Optimization

Before RTL level, the major choices that will impact the power consumption optimization of a
SoC are:
! hardware/software re-partitioning
! bus architecture
! interfaces
! memory organization
! voltage islands
! pipelining
! configuration modes for application needs
! asynchronous logic
! dual Voltage Frequency Scaling

During RTL2GDSII, the major factors that will impact the power consumption of a SoC are:
! IP selection
! technology option selection (body bias, FDSOI, )
! memory cut selection

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 ! power island with power gating strategy (distributed power grid or ring methodology; in-
rush current control; retention)
! clock gating strategy
! multi VT strategy
! clock tree de-skewing

Technics Power Flow Technic Impact and Relevance

Consumption Gain Change in RTL2GDSII
Effort
Schematics/ Synthesis P&R
RTL
Technology Dynamic & Static none - medium to medium
Choice high
Library Dynamic & Static none - medium to medium
Choice high
MultiVt Dynamic & Static low - high high
library 10 to 20 % (1)
Clock Gating Dynamic between 30- medium high high medium
40% (1)
Voltage Dynamic medium high medium medium
Island 20 to 30%(1)
Power Island Mainly Static (x100, medium high high high
x1000) to high
DVFS Dynamic & Static high high high high

Table 2-1 - Low-Power technique impacts in RTL2GDSII integration flow

(1)
These figures are technology dependant here, they are given for a 55/65nm technology.

3. SoC Partitioning Into Power Islands

To explain the relevance of the partitioning into power islands, lets imagine coming back home
after work and switching on, at the same time, all the lights of your home: the kitchen, the
bedroom, the corridor (data bus), the bathroom, the small night light of the childrens bedroom
(retention): this is what happens when you power on a SoC without power islands!
In your home, there is a general circuit breaker providing the power to all the rooms and at least
one switch per room: the electrical power consumption can be adjusted depending on where you
really need the lights and on the number of electrical objects connected per room (washing
machine, coffee machine, ). For a SoC, the same can be achieved: each island can be switched
on or off depending on the usage of the circuit.

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The types of power islands for a SoC can be various depending on the available power supply
sources and the level of power consumption that is required:
! Voltage island: The island is defined as a voltage area. To cut the power supply of the
island, it is necessary to switch the power supply off directly. The island can be
surrounded by level shifters and/or isolation cells.
! Power island with extinction: In this case, the power supply is provided to the voltage
island by power switches (implemented either in a ring or grid style). All the cells inside
the power island (standard cells or macros such as memories) are switched off at the
same time.
! Power island with retention: In this case, the power supply is provided to the voltage
island by power switches, as for the Power island with extinction. All the standard cells
inside the power island are switched off at the same time when the power switches are cut
off except the flip-flops and the bitcells of memories (if any) which are powered directly:
the information is retained.
! Power island with retention and extinction: In this case, the power supply is provided to
the voltage island by two rings of switches. All the standard cells inside the power island
are switched off at the same time when the first ring of switches is cut off except the flip-
flops and the bitcells of memories which are powered through the second ring of
switches: the information is retained unless the second ring of switches is cut off.
! Power island with partial retention: As for the Power island with retention, but only a
subset of flip-flops and bitcells are powered directly to retain the relevant information.

Each type of voltage or power island can either embed only standard cells (logic island), only
memories (memory island), or both of them (composite island). There are various types of power
switch implementations that will be detailed later.

To assess a good partitioning in power islands of a SoC, a relevant practice is to compute a

Figure-of-Merit (FoM) that will be used as the reference during the RTL2GDSII flow. The
FoMBATTERY-LIFE will define the efficiency of the SoC implementation for increasing the life of
the battery. The higher the FoM BATTERY-LIFE is, the longer the life of the battery will be.

The FoM BATTERY-LIFE is computed by adding the power consumption of each voltage/power
island for the different operation modes weigthed by the duration of being active in each mode
(in %).

Where:
! n is the number of islets in the SoC
! mode indicates the functioning mode of the activity table
! PowerCunsomption is the power consumption of the islet depending on the mode
! Duration is the time spent in the mode (in % of the time depending on the usage of the
SoC)

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This FoM does not take into account the efficiency of the regulators used for providing the
power supply. In the case of a SoC embedding the regulators, please refer to Dolphin Integration
publication [5].

4. Relevance of a Public Benchmark

In 2009, Dolphin Integration announced the release in public domain of its Motu Uta benchmark,
a flexible logic circuit designed to represent complex designs. With Motu Uta, the benchmarking
process of standard-cell libraries became not only objective but also fast.
In 2015, Dolphin Integration extends its public benchmark Motu Uta+ with a functional
allocation into power islands to evaluate its own low-power set of solutions named Low-Power
Panoply (LOPAN) and the potential gain in power consumption by using a construction in power
islands.

Motu Uta+ is now a representation of a low-power SoC with several power islands (Figure 4-1):
! One logic block (CPU and peripherals)
! One large logic power island with the possibility of extinction or partial retention
(coprocessor)
! One memory island with retention

It is delivered with a test bench and open source CPU independent application code examples.
Various scenarii of operational modes can be easily compared.

Figure 4-1: Motu-Uta+ functional synoptic

Motu Uta+ includes following blocks required to control the power network:
! The always-on Start-up Control Unit (SCU)
! The always-on Interrupt Wake-up Unit (IWU)

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 ! The power switches driven by the Dolphin Integration patented Transition Ramp Cell
(TRC)
! The Island Control Unit (ICU, one block per power island) that controls the clocks, the
resets as well as the wake-up and put-to-sleep transitions: these units communicate with
the SCU through the Power Island Control Link (PICL) and/or the Power Island Direct
Link (PIDL).

Figure 4-2: Motu Uta+ with an example of power management network

The main advantages of such a distributed power management control (see Figure 4-2 above)
are:

! Dead locks are avoided in a centralized power management control

! Each power/voltage island has a limited set of commands to simplify the exchange with
the top level power management control unit.
! Each power/voltage island can make its request to the regulator an arbitration will be
designed at regulator level.

The method to assess performances with Motu Uta+ consists in low-power verification,
synthesis, placement & routing up to the final STA on the same circuit in order to compare
various implementation styles or libraries. With the public Motu Uta+ benchmark, Dolphin
Integration helps SoC designers to learn how to perform the physical implementation in power
islands from RTL to GDSII, to assess the type of verifications to be performed, to compare the
different implementations, and to measure the benefits of using the proposed low-power panoply.

Through Motu-Uta+, the SoC designer will be able to select the best low-power panoply by
performing dry-runs on a representative low-power SoC.
Motu Uta+ also helps designers understanding the mandatory verification steps in addition to the
standard flow to make a SoC work with power islands: the Figure4-3 shows the integration
issues that can be verified through Motu Uta+ to cope with the supply of a SoC:

1. Power network startup sequence (in-rush current)

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 2. Regulator output voltage setting
3. Regulator load current per mode (load current profiles)
4. Impact of power island mode transition on power supply (low frequency IR-Drop)
5. Impact of side load aggression on power island functionality (noise propagation through
the power network)

Figure 4-3: Motu Uta+: Synoptics with main integration issues

5. Low-Power RTL2GDSII Integration Flow

The overall low-power integration flow is described in the Low-Power Methodology from
Synopsys [1] and an overview can be given in Figure 5-1:

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 Figure 5-1: Low-power RTL2GDSII global integration flow

Dolphin Integration has experimented the low-power flow from Synopsys, and provides
recommendations to make your low-power SoC a success:

1. At RTL level, a specific testbench environment must be put in place to perform low-power
checks such as:

The Retention Verification implies checking

! The overall retention process - that the state has been correctly saved, that the state is
restored correctly and that the overall function works properly after power-up without X
propagation.
! That the retention with retained values are really different from the ones during the reset.
! The impact of the reset on the retention flip-flops.
! The retention sequences to avoid dead-locks.

The Voltage and Frequency Stepping Verification consists in

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 ! Checking the transition modes and the associated sequences to secure the overall
functionality of the circuit according to the power state table.
! Defining the level of modelling of the different elements from the power source downto
the different power islands to ensure a proper functionality and to secure the overall
integration of the power management network.

2. The ultimate link in a low-power construction is the generation of the UPF file which will be
the reference all along the integration flow. The important tips experienced in the UPF file
generation are the following:

First in the specification, the mandatory information to be clarified by the SoC designers are the
following :
! Specify voltage level(s) for each silicon IP for power state table creation.
! Define power domains versus logic design hierarchies.
! Identify the power elements and its power control signals (liberty file, *.lib).
! Define level shifter insertion strategy (applies to : inputs/outputs, location : self/parent,
etc.).
! Define retention mode and isolation cells insertion strategy.
! Specify static/dynamic UPF verification plan (RTL, netlist).

Some UPF tips practiced by Dolphin Integration in the file generation are:

! Create power domain only when necessary: indeed any power domain implies a voltage
area for place and route.
o For example create a power domain for a dual voltage memory instance to enable
the correct insertion of the level shifters at top level.

! Verify the existence and names of the power/ground pins in liberty files: power control
signal name must be coherent between UPF file and liberty file.

! The power state table format needs to be compatible with the back-end implementation
tools (ICC)
o For example, to specify the power supply levels, dont use triplet
(add_port_state VDD_TOP -state { PWR_NV 1.08 1.20 1.32
}) because this type of declaration is not recognized by ICC. It is recommended
to use the following syntax:
o add_port_state VDD_TOP -state { PWR_NVH 1.32}
add_port_state VDD_TOP -state { PWR_NVN 1.20}
add_port_state VDD_TOP -state { PWR_NVL 1.08}
add_pst_state NVH -pst MEM_PST -state [concat PWR_NVH]
add_pst_state NVN -pst MEM_PST -state [concat PWR_NVN]
add_pst_state NVL -pst MEM_PST -state [concat PWR_NVL]

! Check the warnings during the level shifter (isolation/retention cells) insertion: all the
post-synthesis multi-voltage related reports should be carefully examined; analysis and
correction of all the error/warning messages are mandatory. To give some examples,

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 check that the location of level shifter in the netlist hierarchy is consistent with the level
shifter strategy; check that all ports of a module in extinction are connected to an
isolation cell.

The UPF generation requires a good understanding of the SoC specification regarding the power
partition to avoid bad implementation during the synthesis or the place and route like the
suppression of isolation cells.

3. The low-power functional verifications require a combination of

! Static verifications with the Synopsys EDA solution, Verification Compiler Static Low
Power (VC LP [2])
! Dynamic verifications by simulations for correct switch control, in-rush current control
such as Mode Transition Checks (MTC) and Noise propogation Checks (NPC) with
Dolphin Mixed Signal Simultor, SMASH

4. Global Low-Power physical implementation

In addition to the existing reference manuals provided by Synopsys, some additional usefull tips
in physical implementation as experienced at Dolphin Integration can be shared:

! Check that available power management cells are in line with low-power intent from the
UPF file: Availability of level shifters, isolation cells, enable level shifters, power
switches, Always-On buffers for instance.
! Be aware that the power intent should also be coherent with physical intent : for example
if no voltage area is intended to be created , level shifters must be inserted in parent
power domain (-location self option can not be used).
! Be aware that the power intent should also be coherent with timing constraints :
capacitance drive capability and transition range of power management cells should be
wide enough to meet timing constraints on macro cells inputs.
! Check that all libraries have pg pin descriptions. If not, Synopsys has developed a pg-pins
insertion script to add them which is very useful.
! The required scenario list for Place&Route and Static Timing Analysis should be
identified according to the UPF state table. Not all scenarios are relevant.
! Prefer automatic insertion and connection of power management cells by tools according
to the UPF; only power switches should be added manually.
! Power management cells consistency should be verified all along the flow with a
dedicated signoff tool (VCLP).
! Use an equivalence checking tool that can read UPF to avoid false failing points related
to added low-power cells.
! Power domains should be placed and shaped related to their power supply locations
(pad, embedded regulators...) .
! Power grid patterns should be adapted according to the number of power straps to route.
! Take into account the congestion induced by routing signal which cannot cross power
domains.

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5. Focus on power island implementation: how to choose between ring and distributed power
grid.
The choice depends on the following metrics:
! IR-Drop hot points: in case many IR-Drop hot points are present in the design grid
! Ease of implementation
! Congestion

From a static IR-Drop point of view both implementations give approximately the same results.
But the distributed implementation reaches better IR-drop values, with the drawback of having
an increase of overall leakage due to always-on buffering of power switches command.

For the dynamic IR-Drop analysis the use of additional VDD straps allows the ring distribution
to approximately reach the grid implementation performances.

Regarding the ease of implementation, Synsopsys ICC has been improved and now embed
optimized commands that really ease the insertion of the power switches either in ring or
distributed power grid.

In ring:

The main constraints are on the design of the power switch, which is the responsibility of the
library provider. Most of the integration work is to choose the right size of the power switch.
Many power switch sizes must be available to deal with different island areas. Moreover
integrators dont have to worry about the routing of the power switch control signal, because it is
propagated thanks to the abutment of the cells.

In distributed power grid:

Constraints are on the implementation of the power switches array. It can be useful to have 2 or 3
different size of power switches in order to make some local post-routing adjustments, but
globally the same power switch will be always used. Only the density of these power switches
(i.e. the pitch of the power-switch array) will be tuned to meet the design requirement. The
routing of the command of power switches may be challenging.
Finally the grid implementation style requires more user operations since an always-on buffer
tree needs to be created to propagate the control signal of power switches. It complicates the
implementation and may create problems that are not present in the ring distribution. The macro
insertion is also easier in ring implementation.

Furthermore the ring insertion of the power switches can be done separately from the physical
implementation of the power island. Each island can be managed as a hard block and power
switches can be inserted at the top level. It gives an additional freedom when partitioning a
circuit. It could be useful when focus on speed optimisation of the island is required.

As soon as the congestion is an issue, the global power island area will be worst in distributed
power grid than in ring.

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Figure 5-2 presents the decision graph to select the best implementation style taking into account
the design context.

Figure 5-2 : Decision tree for ring vs grid implementation

Additionals recommendations for SoC integrators:

! For distributed power grid implementation it is possible to optimize the final off-leakage.
In case there is a big IR-Drop difference between the periphery and the center of the
island, it is possible to reduce the size of the power switches in the periphery to gain in
leakage while keeping the same maximum static and dynamic IR-Drop values.
! For ring implementation it is possible to optimize the island IR-Drop versus the top IR-
Drop. If some sides of the power island are located close to the power supply sources it is

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 possible to lower the power switches density of these sides while increasing the density
of the other sides (keeping a constant number of power switches).
! It is also possible to mix the two implementation styles. Create a ring to deal with
congestion issue. Then add power switch close to the potential IR-Drop hot points to
locally decrease the power grid resistivity and lower the dynamic IR-Drop.

6. Integration Issues in Power Island Construction

The main issues highlighted in the low-power flow through Motu-Uta+ are in the dynamic
verifications through simulations to be performed in order to insure a correct functionality and to
guarantee the expected level of performance.

For example, to check the impact of the power island mode transition on power supply (number
4 in figure 4.3), two cases have to be considered : the mode and voltage change including power
up and the mode change without voltage change (load transient). In such analysis, the key points
are:
! The voltage level of the island with checking under and overshoots
! The switching sequence for mode and voltage change
! The voltage fluctuations (including regulator transient) due to mode changes of an island
and their impact on the island supplied by the same regulator (direct aggression)

To perform those checks various simulation models are required depending on the function
! For a Regulator: the output impedance (Zout)
! For the Power Distribution Network (PDN): the R, L, C network
! For the aggressor island : the load current profile (LCP)
! For the potential victim island: the Power Supply Noise Tolerence Template (PSNT2) or
noise transfer function (PSNTF)

For pure logic simulation, Dolphin Integration has introduced a pure logic model dedicated to
check the mode change impact on the functionality: the Mode Transition Digital Model
(MTDM).

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 Figure 6-1: Low-Power RTL2GDSII integration flow with Mode Transition Checks

The Table 6-1 provides the key checks (listed and shown in Figure 4-3 for the case MOTU
UTA+), the required type of models for the different blocks of the SoC and when these checks
have to be done in the RTL2GDSII flow:

Issue Key Checks MTC Models required Simulation Type & RTL2GDSII steps
EDA Solutions
#1 Check the power-up sequences Control Units: MTDM Logic simulation RTL level
Regulator: F&TDM with MVSIM [3] Gate level
#2 Check the different voltage Regulator: AMS Mixed-signal Gate level
regulator setting PDN: R, L, C network simulation with with extractions

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 Power Island: ZIN per mode SMASH
#3 Check the compliance between - Regulator: Imax Mixed-signal RTL level
the load current profiles and - Aggressor island: ZIN per simulation with Gate level
the regulator current template mode SMASH
#4 Check the current profile of - Regulator: PSNTF, ZOUT Mixed-Signal RTL level
the different loads during - Power Distribution Simulation Gate Level with
mode transitions Network: R, L, C network with SMASH extractions
Power integrity check of the - Aggressor island: ZIN
power network during mode - Victim island: PSNT2 IR-Drop analysis
transitions with PrimeRail
#5 Functional verifications of the - Regulator: CBTF, Mixed-Signal RTL level with
power islands during mode PSNTF, ZOUT Simulations with preliminary figures
transitions (including regulator - Reference: PSNTF, SMASH Gate level with
transient) CBTF, ZOUT extracted values
- Power Distribution Fast Spice
Network: R, L, C network simulation possible
- Aggressor Island: ZIN case by case
- Victim Island: PSNT2
Table 6-1 Key checks,models and EDA-solution in power island construction for Motu-Uta+

Where:
F&TDM : Functional and timing Digital Model VSIA Definition
MTDM : Mode Transition Digital Model Dolphin Integration Definition

The major difficulty is to define the good level of modeling to setup a simulation environment
for dynamic verifications focused on power consumption and IR-Drop analysis in order to
! Confirm the power island partitioning and regulator selection
! Measure the power savings at SoC level
! Assess the low-frequency & high frequency IR-Drop budgets and monitor these budgets
at each step of the RTL2GDSII flow
! Optimize the overall Bill of Material (number of external power regulators, capacitances
or inductances)

The models for different elements should be provided by the different silicon IP providers
(regulator, etc) or by the library provider (power island model). The different parasitics can be
extracted by the Synopsys tool at the proper step during the physical implementation.
Those checks must be part of the verification plan at SoC level. The main purpose is to guarantee
the functionality and the level of performance (power consumption gain) during the required
mode transition.

Once the simulation models exist, the other challenge is to define the relevant simulations to be
performed to control the physical implementation from RTL to GDSII.

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7. Benchmark Results
1. The FoMBATTERY-LIFE Computation on Motu-Uta+
The Figure 7-1 and the Figure 7-2 provide the implementation of MOTU UTA+ with and
without island. The power supply is generated by an external regulator.

Figure 7-1: Motu Uta+ with island implementation (the RTC-AO includes SCU/IWU and the ICU)

Figure 7-2: Motu Uta+ without island implementation

The activity of each block is provided in the Table 7-1 below (Application mode table):
depending on the application mode each block is used or not (clock off without island, power
supply off with island). For the implementation without power island, in order to reduce the
power consumption when a logic block is not used, we put the clocks in mode OFF (=ClockOFF
in the table, which means that the consumption of the logic block is exclusively a leakage

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current); for the implementation with power island, when an island is unused the power supply is
cut-off through the power switches (=OFF in the table).

Functions/ RTC CPU CoProcessor RAM

Application Modes
Standby waiting for user trigger
ON ClockOFF/OFF ClockOFF/RET ClockOFF/RET
(99 % of time)
Processing the user trigger
ON ON ClockOFF/RET ON
(0.1 % of time)
Treatment
ON ON ON ON
(0.1 % of time)
Data transfer to the RAM
ON ClockOFF/OFF ClockOFF/OFF ON
(0.8 % of time)
Table 7-1 Motu-Uta+ application mode table
Where :
RET is retention

From the application mode table it is possible to derive the activity Table 7-2 providing the time
spent by each islet in the different modes:

Islet / RTC CPU CoProcessor RAM

Functioning Mode
Off 99.8 % 99.9 % 99 %
Always On 100 %
On 0.2 % 0.1 % 1%
Table 7-2 Motu-Uta+ activity table

The Table 7-3 details the power consumption of each logic block/islet depending on the activity.

Islet / RTC CPU CoProcessor RAM

Functioning Mode (W) (mW) (mW) (mW)
Off with power switches
or retention mode NA 0.00015 0.002 0.080
(RAM)
Off with clock off NA 0.012 0.162 0.300
On 10 1.931 3.636 3.8

Table 7-3 - Motu-Uta+ power consumption table

The FoMBATTERY-LIFE for the implementation without island and with island is easily computed:

Islet FoMBATTERY-LIFE = 7308

Non-Islet FoMBATTERY-LIFE = 1900

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The FoMBATTERY-LIFE of the solution with power islands is more than 3 times and a half the FoM
of the non-power island solution: the life of the battery is more than 3 times and a half longer!

2. The SoC designer has to write the UPF file

# TRC Cell STRUCTURE DEFINITION

set USE_TRC 1
if { $USE_TRC } { set iso_ctrl_port "trc/ISOLATE" ;
# Isolation Control of ISLET with TRC structure set ctrl_port
"trc/ICTRL" ;
# Power switch control pins with TRC structure
set retention_signal "trc/RETAIN" ;
# Retention control pin with TRC structure
} else {
set iso_ctrl_port "isolate_pad_i" ;
# Isolation Control of ISLET without TRC structure set ctrl_port
"trc_pwr_ctrl_pad_i" ;
# Power switch control pins without TRC structure
set retention_signal "trc_ret_ctrl_pad_i" ;
# Retention control pin without TRC structure
}
# POWER DOMAIN DEFINITIONS
# Define Top module to apply Power definition
set_design_top"curling_top_testbench/dut"
# Power domain Top
create_power_domain PD_TOP
create_power_domain PD_RET -elements [list coproc "motu_uta/or1200_top0"]
# Power Supply connection
#---------------------------------------------------------------------
# VDD of power domain Top
create_supply_port VDD_TOP
create_supply_net VDD_TOP -domain PD_TOP
connect_supply_net VDD_TOP -ports VDD_TOP
create_supply_net VDD_TOP -reuse -domain PD_RET
# VSS of power domain Top
create_supply_port VSS
create_supply_net VSS -domain PD_TOP
connect_supply_net VSS -ports VSS
#----------------------------------------------------------------------------
# Power domain RETENTION
create_supply_port VDD_RET create_supply_net VDD_RET -domain PD_TOP
connect_supply_net VDD_RET -ports VDD_RET create_supply_port VDD_RET_OUT -
domain PD_RET create_supply_net VDD_RET_OUT -domain PD_TOP -resolve parallel
create_supply_net VDD_RET_OUT -reuse -domain PD_RET -resolve parallel
connect_supply_net VDD_RET_OUT -ports VDD_RET_OUT
create_supply_net VSS -reuse -domain PD_RET
#----------------------------------------------------------------------------
# supply set for power domain Top
set_domain_supply_net PD_TOP -primary_power_net VDD_TOP -
primary_ground_net VSS
set_domain_supply_net PD_RET -primary_power_net VDD_RET_OUT -
primary_ground_net VSS
# LEVEL SHIFTER
#----------------------------------------------------------------------------
# DO NOT INSERT LS ON ISLET #
set_level_shifter LS

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-domain PD_RET \ #
-threshold 2.0 \ #
-location parent
# ISOLATION CELLS
#---------------------------------------------------------------------------
# Define Isolation insertion strategy
set_isolation ISO_I
-domain PD_RET \
-isolation_power_net VDD_TOP \
-isolation_ground_net VSS \
-applies_to inputs \
-clamp_value 0
set_isolation ISO_RESET
-domain PD_RET \
-isolation_power_net VDD_TOP \
-isolation_ground_net VSS \
-elements [list "coproc/hresetn" "coproc/crstn"
"motu_uta/or1200_top0/iwb_rst_i" "motu_uta/or1200_top0/dwb_rst_i" ] \
-clamp_value 1 set_isolation ISO_O -domain PD_RET \
-isolation_power_net VDD_TOP \
-isolation_ground_net VSS \
-applies_to outputs \
-clamp_value 0
#---------------------------------------------------------------------------
# Define Isolation control
set_isolation_control ISO_I
-domain PD_RET \
-isolation_signal $iso_ctrl_port \
-isolation_sense high \
-location parent
set_isolation_control ISO_RESET
-domain PD_RET \
-isolation_signal $iso_ctrl_port \
-isolation_sense high \
-location parent
set_isolation_control ISO_O
-domain PD_RET \
-isolation_signal $iso_ctrl_port \
-isolation_sense high \
-location parent
#--------------------------------------------------------------------------
# Map Isolation
map_isolation_cell ISO_I
-domain PD_RET \
-lib_cells [list ick_is0id1 ick_is0id2 ick_is0od1 ick_is0od2]
map_isolation_cell ISO_RESET
-domain PD_RET \
-lib_cells [list ick_is1id1 ick_is1id2 ick_is1od1 ick_is1od2]
map_isolation_cell ISO_O
-domain PD_RET \
-lib_cells [list ick_is0id1 ick_is0id2 ick_is0od1 ick_is0od2]
# POWER SWITCH
#----------------------------------------------------------------------------
# Define Power switch insertion strategy
create_power_switch SW
-domain PD_TOP \
-input_supply_port {VDD_IN VDD_RET} \
-output_supply_port {VDD_OUT VDD_RET_OUT} \

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-control_port [list ICTRL $ctrl_port ] \
-on_state {power_on VDD_IN {!ICTRL}} \
-off_state {power_off {ICTRL}}
#---------------------------------------------------------------------------
# RETENTION
#----------------------------------------------------------------------------
# Define Retention strategy
set_retention RET
-domain PD_RET \
-retention_power_net VDD_TOP \
-retention_ground_net VSS set_retention_control RET
-domain PD_RET \
-save_signal [list $retention_signal low] \
-restore_signal [list $retention_signal high]
#----------------------------------------------------------------------------
# Map Retention cells
map_retention_cell RET
-domain PD_RET \
-lib_cells [list ick_rdfcnd1 ick_rdfcnd2 ick_rdfcnpnd1 ick_rdfcnpnd2
ick_rdfd1 ick_rdfd2 ick_rdfpnd1 ick_rdfpnd2 ick_rsdfcnd1 ick_rsdfcnd2
ick_rsdfcnpnd1 ick_rsdfcnpnd2 ick_rsdfd1 ick_rsdfd2 ick_rsdfpnd1 ick_rsdfpnd2
]
# POWER STATE TABLE DEFINITION
#----------------------------------------------------------------------------
# Power supply level description
add_port_state VDD_TOP -state { PWR_NV 1.08 }
add_port_state VDD_RET -state { PWR_NV 1.08 }
add_port_state VDD_RET -state { PWR_RET 1.08 }
add_port_state VDD_RET -state { PWR_OFF off }
add_port_state VDD_RET_OUT -state { PWR_NV 1.08 }
add_port_state VDD_RET_OUT -state { PWR_RET 1.08 }
add_port_state VDD_RET_OUT -state { PWR_OFF off }
add_port_state VSS -state { PWR_0 0.00 }
#----------------------------------------------------------------------------
# POWER STATE TABLE
create_pst PST -supplies { VDD_TOP VDD_RET VDD_RET_OUT VSS }
add_pst_state OFF -state { PWR_NV PWR_OFF PWR_OFF PWR_0 } -pst PST
add_pst_state EXTINCTION -state { PWR_NV PWR_RET PWR_OFF PWR_0 } -pst PST
add_pst_state RETENTION -state { PWR_NV PWR_RET PWR_RET PWR_0 } -pst PST
add_pst_state ON -state { PWR_NV PWR_NV PWR_NV PWR_0 } -pst PST

3. The SoC designer has to write the script for static Low-Power verification to be used with
VCLP

## To view what had VCLP understood of the UPF

report_upf > report_upf.rpt
## To check if there is no problem with pst
report_pst_state -only_invalid > report_pst_state.rpt
## Custom waivers to add depending on the project
#waive_lp -add FLT-LS_INST_REDUND -comment "LS redundant for balancing
reference and data paths" -tag "LS_INST_REDUND" -filter {(Sink =~
"*/i_tmux/i_mux_do_*sb/B") AND (LogicSource:PinName =~
"*/i_tmux/i_mux_sh_ck/Z")}
## Generate the reports

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report_lp > report_lp.rpt
## Additional report for std cells main rail connections
set keep_searching true
ls_scmr_checks -file report_scmr.rpt
## Start gui and debug if errors/warning are found
if { [catch { exec egrep "error|warning" report_lp.rpt } ] == "0" || [catch {
exec egrep "error|warning" report_scmr.rpt } ] == "0" } { view_activity }
## Write waivers list #waive_lp -tcl
## Lists of all available checks
#configure_lp_tag -all -verbose
## Lists of all disabled checks
#configure_lp_tag -verbose

4. The SoC designer has to perform dynamic low-power checks by running the simulations listed
in Table-6.1: the following Figure7-1 and 7-2 show the results for the simulations. The power
integrity check is done on all transition among the modes described in Table-7.1.
The Figure 7-1 provides the results in the case of the decoupling capacitance of the power
mangement network of 100 pF: in this case the transistion between the Standby mode waiting
for user trigger to Processing the user trigger creates an error on the retention cells of the
coprocessor due to a too low-power supply value during the transition.
The same simulation shows an error on the CPU between Processing the user trigger and
Treatment when the coprocessor is switch on.
The Figure 7-3 provides the results of the same patterns on the SoC but with a target decoupling
capacitance of the power management network of 1 nF: in this case no errors are detected.

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Figure 7-2: Power integrity check of the power network during mode transitions with a Power Distribution
Network Capacitance of 100 pF

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 Figure 7-3: Power integrity check of the power network during mode transitions with a Power Distribution
Network Capacitance of 1 nF

The goal of this simulation at an early stage of the design is to provide a target value for
decoupling capacitance of the power mangement network to ensure the functionality of the
power island: during the P&R flow, this value can be extracted from the physical information in
order to check if some corrective actions (add extra decoupling filler cells for instance) are
necessary.

8. Conclusion

This paper has introduced a method to compute the expected gain in power consumption through
a Figure of Merit and a robust flow to implement a low-power SoC into power islands through a
public benchmark. The EDA solutions do exist to manage the physical implementation of such
power island architecture but it remains to the responsiblity of the SoC designer to define the
type of verifications to be performed to validate the SoC power consumption performance in its
application. It has been highlighted the relevance of the dynamic verifications and the modeling
of the different elements of the power management network to complete the static verifications
proposed in standard low-power flow. To be able to optimize the power management network,
those dynamic verifications including the mode transition checks become mandatory to reach the
targeted specifications in power consumption from the battery point of view as demonstrated
through some results shown with the public benchmark Motu-Uta+.

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9. References

[1] Synopsys Inc - Low Power Methodology Manual

[2] Synopsys Inc - VC LP ref. manual
[3] Synopsys Inc. - MVSIM ref. manual
[4] Low Power SoC Design and Automation - Matt Severson Qualcomm CDMA Technologies July 27,
2009
[5] Guidelines to identify your optimal power management solution depending on your application
challenges (on Linkedin)

10. Acronyms

CBTF : Current Backward Transfer Function

CPU: Central Processing Unit
DVFS: Dynamic Voltage and Frequency Scaling
EDA: Electronic Design Automation
F&TDM : Functional and timing Digital Model VSIA Definition
GDSII: Layout binary format
MTC: Mode Transition Checks
MTDM : Mode Transition Digital Model Dolphin Integration Definition
NPC: Noise Propagation Checks
PDN: Power Distribution Network
PSNTF : Power Supply Noise Transfer Function
PSNT2 : Power Supply Noise Tolerane Template
P&R: Place and Route
RTL: Register Transfer Level
SLASH : SMASH with integrated schematic editor
SMASH : Dolphin Integration Mixed Signal Simulator for logic and mixed signal circuits
SoC : System-on-Chip
STA: Static Timing Analysis
TRC : Transition Ramp Cell (patented)
UPF: Unified Power Format
VCLP: Verification Compiler Static Low Power
VSIA : Virtual Socket Interface Alliance
ZIN/ ZOUT : Input /Output Impedance

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