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8 7 6 5 4 3 2 1

CK ENG
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
M3911/16/05
- DVT REV

06
ZONE ECN

400374
DESCRIPTION OF CHANGE

ENGINEERING RELEASED
APPD

DATE

09/16/05
APPD

DATE

06/22/04

PAGE DRI PDF CIRCUIT PAGE DRI PDF CIRCUIT


D 1 JD JD
1 TABLE OF CONTENTS 53 JD JD
43 PCI-E - AIRPORT MINI-PCIE CONN D
2 JD JD
2 SYSTEM BLOCK DIAGRAM 54 JD JD
44 PCI-E - UNUSED PORTS
3 RT RT
3 POWER BLOCK DIAGRAM 58 MS MS
45 SMC - H8S2116
4 JD JD
4 TABLE ITEMS & REVISION HISTORY 59 MS MS
46 SMC - SMB BUSSES, MISC
5 JD JD
5 FUNC TEST 60 MS MS
47 SMC - LPC+ CONN
6 RT RT
6 POWER CONNECTOR / POWER ALIAS 61 JH JH
48 SMC - GPU/NB THERMAL SENSOR
(M42)
7 MS JD
7 CPU - BUS INTERFACE RX
63 MS JD
49 SMC - SPI BOOTROM
(M42)
8 MS JD
8 CPU - PWR & GND 65 MS MS
50 SMC - FANS
9 MS JD
9 CPU - DECAPS 66 MS MS
51 SMC - FANS
10
(M42) MS JD
10 CPU - THERMAL SENSOR 67 JD JD
52 SMC - TPM
M42
11 MS JD
11 CPU - ITP CONN SO
68 PT JD
53 AUDIO - CODEC,VREG,MIC BIAS
M1
12 PS JH
12 NB - CPU INTERFACE SO
72 PT JD
54 AUDIO - INTERNAL SPEAKER AMP
M1
13 PS JH
13 NB - VIDEO INTERFACE SO
73 PT JD
55 AUDIO - I/O CONNS,EMC
C 14 PS JH
14 NB - MISC INTERFACES SO
74 PT JD
56 AUDIO - DETECT TRANSLATORS C
M1
15 PS JH
15 NB - DDR2 INTERFACE RP
75 RT RT
57 VR - CPU CORE
M1
16 PS JH
16 NB - POWER 1 RP
76 RT RT
58 VR - CPU I-V SENSE CKT
M1
17 PS JH
17 NB - POWER 2 RP
77 RT RT
59 VR - "S0" 1.2V & 2.5V (GRAFIX)
M1
18 PS JH
18 NB - GROUNDS RP
78 RT RT
60 VR - "S0" 1.8V
19 PS JH
19 NB - DECAPS RP
79 RT RT
61 VR - "S3" 1.8V
M1
20 PS JH
20 NB - CONFIG STRAPS RP
80 RT RT
62 VR - "S0" 1.5V
21 JD JD
21 SB - RTC,LAN,AUDIO,ATA,CPU,LPC RP
81 RT RT
63 VR - "S0" 1.05V
22 JD JD
22 SB - PCIE,SPI,USB,DMI,PCI RP
83 RT RT
64 VR - "S3" 3.3V AND 5V
23 JD JD
23 SB - SMB,GPIO,PM,CLKS JH
84 JH JH
65 GPU - M56 PCI-E
24 JD JD
24 SB - POWERS AND GROUNDS M1
85 JH JH
66 GPU - VCORE SUPPLY
25 JD JD
25 SB - DECAPS M1
86 JH JH
67 GPU - M56 CORE PWR
26 JD JD
26 SB - MISC M1
87 JH JH
68 GPU - M56 FRAME BUFFER
27 JD JD
27 SB - SMB BUS CONNECTIONS M1
88 JH JH
69 GPU - MISC
B B
28 PS JD
28 DDR2 - SO-DIMM CONN A M1
89 JH JH
70 GPU - GDDR SDRAM A
29 PS JD
29 DDR2 - SO-DIMM CONN B (REVERSED) M1
90 JH JH
71 GPU - GDDR SDRAM B
30 PS JD
30 DDR2 - TERMINATION M1
91 JH JH
72 GPU - M56 GPIO,DVO,MISC
M1
31 RT RT
31 DDR2 - VTT SUPPLY M1
92 JH JH
73 GPU - M56 CLOCKS
M42
33 JD JD
32 CLOCKS - GENERATOR M1
93 JH JH
74 GPU - M56 VIDEO INTERFACES
34 JD JD
33 CLOCKS - TERMINATIONS JH
94 JH JH
75 GPU - INTERNAL DISPLAY CONNS
38 JD JD
34 ATA (SATA AND IDE) CONNS JH
95 JH JH
76 GPU - TPS
41
(M42) JD JD
35 LAN - YUKONS PCIE INTERFACE JH
96 JH JH
77 GPU - TMDS,INVERTER,EXT VGA
42 JD JD
36 LAN - YUKONS PWR, MISC JH
97 JH JH
78 GPU - EXTERNAL DISPLAY CONNS
43 JD JD
37 LAN - CONN
44 JD JD
38 FIREWIRE - FW323-06 DIMENSIONS ARE IN MILLIMETERS

45 JD JD
39 FIREWIRE - DECAPS METRIC Apple Computer Inc.
XX

A 46 JD JD
40 FIREWIRE - CONNS X.XX
DRAFTER DESIGN CK NOTICE OF PROPRIETARY PROPERTY A
47 JD JD
41 USB - CONNS X.XXX
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
49 JD JD
42 USB - FLASH CONN ANGLES
ENG APPD MFG APPD
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
QA APPD DESIGNER TITLE
DO NOT SCALE DRAWING

RELEASE SCALE SCHEM,M39


NONE

SIZE DRAWING NUMBER REV.


MATERIAL/FINISH
NOTED AS D 051-6950 06
THIRD ANGLE PROJECTION APPLICABLE SHT 1 OF 111

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
J0700
CPU J1101
(1.83/2.17GHZ) ITP
CORE (~1.2V) CONN
PAGE 8 PAGE 11

PAGE 7
J9700 J9402

MINI-DVI LVDS
(TMDS - VGA) (INTERNAL) 64-BIT
FSB
D PAGE 97 PAGE 94 667MHZ D
J2800
J2900
PAGE 12
GDDR3

MAIN MEMORY
DDR2 - DUAL CHAN
64-BIT PAGE PAGE
U8900, U8950
1.8V/700MHZ(?)
93 93
U1200
1.8V/667MHZ DIMM PARALLEL

PAGE 15
64-BIT

PAGE 84
PAGES 87
PCIE
FRAME GPU PCIE X16 NB TERM
BUFFER A U8400 2.5GHZ PAGE CORE (1.05V) PAGES 30
13 PAGE 16-17
PAGE 89

PAGES 87 PAGE 28-29 U3301


MISC DMI
GDDR3
PAGE 14 PAGE 14 CK410
64-BIT CLOCKS TERMS
1.8V/700MHZ(?) 4-BIT
PAGE 33 PAGE 34
DMI
1.2V/800MHZ
CONTROL = 2.5V J2901 ALS+ATS TSENS
U9000, U9050

U1000 CPU TSENS


FRAME
U6100 GPU+NB TSENS
BUFFER B
C PAGE 90
U6300/01
J6601 HD TSENS

J6602 ODD TSENS


C
SPI J6500,J6501,J6600 FAN CONNS
BOOTROM
PAGE 63

RMT MLB FAN


U5800
U6700 J6000
SMC TPM LPC+ CONN
JE310/JE320/JE330 JE350 U4800 J4700
PAGE 58 PAGE 67 PAGE 60
JC900 USB BNDI FLASH BT
INTERFACE
SATA CONNECTORS PAGE 47 CTLR CONN

PAGE 21
DMI SPI

LPC
SATA2
0 2 4 PAGE 47 3 7
PAGE 48 PAGE 48
CONNECTOR
PAGE 21
SATA
PAGE 22 PAGE 22
HARD DRIVE 1.2V/1.5GHZ 4-BIT (3.3V/33MHZ)

CAMERA
PAGE 38
SATA0

1 0,2,4
U2100

IR
JE500
JC901
MEDIA CARD CONNECTOR
SB J5300 (AIRPORT CONN)
PAGE 21

UATA

UATA

PAGE 22
UATA/133
CF SD

USB
CORE (1.05V)

3,7
CONNECTOR 3.3V/133MHZ PAGE 49
OPTICAL

5
PAGE 38
#2-5
PORT

6
B CORE GPIOS B
PAGE 22
PCI-E

X1 - 1.5GHZ
PORT
#1

PAGE 24 PAGE 23

PAGE 23
SMB
PCI AZALIA
X1 - 1.5GHZ
PORT
#0

PAGE 22 PAGE 21 J2800 U3301 J5300


J2900
DIMMS CK410M AIRPORT

33MHZ
32-BIT

U6800
S/PDIF OPTICAL OUT
AUDIO CODEC J7303

J5300 U4101
STA9221 COMBO OUT
PAGE 68 CONNECTOR
MINI-PCIE YUKON FW323-06 PORT A PAGE 153
PORT C
LINE OUT
AIRPORT GIG ETHERNET FIREWIRE A
PAGE 44
PORT F PORT B
System Block Diagram
PAGE 53 PAGE 41 0 1 2 J7301
A SPEAKER
AMP
SPEAKER NOTICE OF PROPRIETARY PROPERTY
A
4 Diff pairs 2 Diff pairs CONNECTOR
PAGE 72
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PAGE 73 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
JD600 JE000, JE001 J7300 JE350 AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
ETHERNET FIREWIRE A LINE IN MIC IN
II NOT TO REPRODUCE OR COPY IT
CONNECTOR CONNECTORS CONNECTOR BNDI
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
PAGE 43 PAGE 46 INTERFACE
PAGE 73
SIZE DRAWING NUMBER REV.

D 051-6949 09
APPLE COMPUTER INC.
SCALE SHT OF
NONE 2 111

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

AC/DC POWER SUPPLY

12V, 180W, 15A


S5

DC/DC BOARD

D D
12V, 12A 5V, 4A 3.3V, 4A

12V_S5 12V_S0 5V_S5 5V_S0 3_3V_S5 3_3V_S0

CPU_CORE FANS AUDIO ENET NB_GPIO


PPVCORE_CPU_S0 HARD DRIVE PP4V5_AUDIO_ANALOG PP3V3_S3 PP2V5_S0 GPU_GPIO
1.3V @ 36A LCD 4.5V @ ?A 2.5V @ 0.9A
SPEAKER AMP FET
PAGE 75 PAGE 68 PAGE 83 PAGE 77

CPU_FSB OPTICAL ENET_CORE


PP1V05_S0 NB_CORE PP5V_S3 HARD DRIVE PP1V2_S3
1.05V @ 8.9A NB_FSB 1.2V @ 2.5A
SB_CORE FET
PAGE 81 PAGE 83 PAGE 77

GPU_PCIE
NB_DRAM PP1V2_S0
PP1V8_S3 DRAM_CORE PP0V9_S0
1.8V @ 10A DRAM_IO 0.9V @ 1A FET
PAGE 77
PAGE 79 PAGE 31

C PP1V5_S0
CPU_AVDD
NB_PCIE
USB
C
1.5V @ 8A SB_IO
PAGE 80

GPU_CORE
PP1V0R1V2_S0_GPU
1.2V @ 15A
PAGE 85

GPU_DRAM
PP1V8_S0 GDDR_IO
1.8V @ 8A
PAGE 78

PANEL INVERTER
FIREWIRE

B B

Power Block Diagram


A NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-6949 09
APPLE COMPUTER INC.
SCALE SHT OF
NONE 3 111

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

COMMON TABLE_5_HEAD
M38 TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_ITEM TABLE_5_ITEM

511S0025 1 IC,CPU-SKT,479BGA J0700 CRITICAL 051-6949 1 PCB,SCHEM,MLB,M38 SCH1 17_INCH_LCD


TABLE_5_ITEM TABLE_5_ITEM

338S0269 1 IC,945GM,NORTHBRIDGE U1200 CRITICAL 820-1919 1 PCB,FAB,MLB,M38 MLB1 17_INCH_LCD


TABLE_5_ITEM TABLE_5_ITEM

D 343S0385 1 IC,SB,652BGA U2100 CRITICAL


TABLE_5_ITEM
(335S0384) 341T0003 1 EFI ROM,M38 U6301 CRITICAL 17_INCH_LCD
TABLE_5_ITEM
D
742-0048 1 BAT,COIN,3V,220MAH,CR2032 BT2600 CRITICAL 337S3241 1 M38/M39 LOW-SPEED CPU (QINY) CPU CRITICAL CPU_M38
TABLE_5_ITEM TABLE_5_ITEM

359S0101 1 IC,CY28445-5,CLK GEN,68PIN QFN U3301 CRITICAL 337S3242 1 M00-SPEED CPU (QINZ) CPU CRITICAL CPU_M00
TABLE_5_ITEM

338S0270 1 IC,88E8053,GIGABIT ENET XCVR,64P QFN,NO U4101 CRITICAL


TABLE_5_ITEM

(335S0382) 341S1797 1 IC,ENET LAN ROM U4102 CRITICAL


TABLE_5_ITEM

338S0279 1 IC,FW32306,1394A LINK,TQFP U4400 CRITICAL


TABLE_5_ITEM

338S0274 1 IC,SMC,HS8/2116,BLANK U5800 CRITICAL


TABLE_5_ITEM

341S1789 1 IC,TPM,TSSOP,28P U6700 CRITICAL LEMENU

353S1235 1 IC,CPU VREG,IMVP,TWO PHASE U7500 CRITICAL


TABLE_5_ITEM

M39 TABLE_5_HEAD

TABLE_5_ITEM

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION


338S0266 1 IC,ATI,M56P,GRAFIX CTLR,880BGA,LF U8400 CRITICAL ATI_B24 TABLE_5_ITEM

TABLE_5_ITEM

051-6950 1 PCB,SCHEM,MLB,M39 SCH1 20_INCH_LCD


338S0305 1 IC,ATI,M56P,GRAFIX CTLR,880BGA,LF U8400 CRITICAL ATI_A24 TABLE_5_ITEM

TABLE_5_ITEM

820-1888 1 PCB,FAB,MLB,M39 MLB1 20_INCH_LCD


128S0078 3 CAP,EL,AL,330UF,20%,16V,10X12.7MM,SMD,LF C7517,C7518,C7910 CRITICAL TABLE_5_ITEM

(335S0384) 341T0004 1 EFI ROM,M39 U6301 CRITICAL 20_INCH_LCD


TABLE_5_ITEM

337S3243 1 M39 HI-SPEED CPU (QHJJ) CPU CRITICAL CPU_M39

C PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:


TABLE_ALT_HEAD
C
PART NUMBER
TABLE_ALT_ITEM
M38 / M39
126S0096 126S0076 C7801 SANYO W16CE680KX 680UF 16V LF
TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION


C699,C940,C1900,C1901,C1968
TABLE_ALT_ITEM

126S0086 126S0078 SANYO W6CE330FS 330UF 6.3V LF


TABLE_5_ITEM

333S0354 4 IC,SGRAM,GDDR3,8MX32,700MHZ,136FBGA U8900,U8950,U9000,U9050 CRITICAL ATI_FB_128M_SAMSUNG


C7517,C7518,C7910
TABLE_ALT_ITEM

128S0080 128S0078 SANYO 16SVP330M 330UF 16V SMD LF TABLE_5_ITEM

TABLE_ALT_ITEM
333S0358 4 IC,SGRAM,GDDR3,8MX32,700MHZ,136FBGA U8900,U8950,U9000,U9050 CRITICAL ATI_FB_128M_HYNIX
197S0177 197S0020 Y4101 XTAL,25MHZ,50PPM,16PF,3.2X2.5 SMD,LF
TABLE_ALT_ITEM

338S0302 338S0266 U8400 IC,ATI,M36D,GRAFIX CTLR,88PBGA,LF

M39 - CTO
TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION


TABLE_5_ITEM

333S0350 4 IC,SGRAM,GDDR3,16MX32,700MHZ,136FBGA U8900,U8950,U9000,U9050 CRITICAL ATI_FB_256M_SAMSUNG


TABLE_5_ITEM

333S0351 4 IC,SGRAM,GDDR3,16MX32,700MHZ,136FBGA U8900,U8950,U9000,U9050 CRITICAL ATI_FB_256M_HYNIX

B B

Table Items
A NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-6949 09
APPLE COMPUTER INC.
SCALE SHT OF
NONE 4 111

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
LAYOUT NOTE: PLACE NEAR J0700 LAYOUT NOTE: PLACE NEAR U1200 LAYOUT NOTE: PLACE NEAR U8400 LAYOUT NOTE: PLACE NEAR U4101 PLACE NEAR R1210 AND R1211 79 77 76 66 65 59 26 6
83 81 80 IN PP3V3_S5 FUNC_TEST=TRUE 60 59 58 IN SMC_TCK FUNC_TEST=TRUE
FSB_A_L<6> PP600 1
SM OMIT FSB_A_L<6> PP631 1
SM OMIT FB_A_DQ<0> PP8700 SM
1 OMIT ENET_CLK100M_PCIE_P PP4100 SM
1 OMIT NB_FSB_VREF PP1200
1 83 81 80 79 59 6 IN PP5V_S5 FUNC_TEST=TRUE 60 59 58 IN SMC_TDI FUNC_TEST=TRUE
12 7 5 PP
P4MM
12 7 5 PP
P4MM
89 87 5 PP
P4MM
41 34 PP
P4MM
12 A 88 83 81 80 79 78 6 PP12V_S5 FUNC_TEST=TRUE 60 59 58 SMC_TDO FUNC_TEST=TRUE
IN IN
12 7 5 FSB_ADSTB_L<0> PP601 1
SM PP OMIT 12 7 5 FSB_ADSTB_L<0> PP632 1
SM PP OMIT 89 87 5 FB_A_DQ<8> PP8701 SM
1
PP OMIT 41 34 ENET_CLK100M_PCIE_N PP4101 SM
1
PP OMIT SM-TP50-TOP
PP1V8_S3 SMC_TMS
P4MM P4MM P4MM P4MM 79 6 FUNC_TEST=TRUE 60 59 58 FUNC_TEST=TRUE
12 7 5 FSB_A_L<27> PP602 1
SM PP OMIT
P4MM
12 7 5 FSB_A_L<27> PP633 1
SM PP OMIT
P4MM
89 87 5 FB_A_DQ<16> PP8702 SM
1
PP OMIT
P4MM =PP1V05_S0_FSB_NB PP1201
1
IN
PPVCORE_CPU FUNC_TEST=TRUE
IN
SMC_TRST_L FUNC_TEST=TRUE
12 7 5 FSB_ADSTB_L<1> PP603 1
SM OMIT 12 7 5 FSB_ADSTB_L<1> PP634 1
SM OMIT 89 87 5 FB_A_DQ<24> PP8703 SM
1 OMIT
19 12 6 A 76 75 6 IN 60 58 IN
PP PP PP SM-TP50-TOP
P4MM P4MM P4MM 26 25 24 21 IN PP3V3_S5_SB_RTC FUNC_TEST=TRUE
12 7 5 FSB_D_L<0> PP604 1
SM OMIT 12 7 5 FSB_D_L<0> PP635 1
SM OMIT 89 87 5 FB_A_DQ<32> PP8704 SM
1 OMIT 60 59 58 IN SMC_TX_L FUNC_TEST=TRUE
FSB_DSTBN_L<0> PP605 1
SM
PP
P4MM
OMIT FSB_DSTBN_L<0> PP636 1
SM
PP
P4MM
OMIT FB_A_DQ<40> PP8705 SM
1
PP
P4MM
OMIT
PP1202
1 8 TESTPOINTS
FUNC_TEST=TRUE SMC_RX_L FUNC_TEST=TRUE
12 7 5 PP
P4MM
12 7 5 PP
P4MM
89 87 5 PP
P4MM A IN 60 59 58 IN
12 7 5 FSB_DSTBP_L<0> PP606 1
SM PP OMIT 12 7 5 FSB_DSTBP_L<0> PP637 1
SM PP OMIT 89 87 5 FB_A_DQ<48> PP8706 SM
1
PP OMIT SM-TP50-TOP
P4MM P4MM P4MM 59 IN SMC_MANUAL_RST_L FUNC_TEST=TRUE
12 7 5 FSB_DINV_L<0> PP607 1
SM PP OMIT 12 7 5 FSB_DINV_L<0> PP638 1
SM PP OMIT 89 87 5 FB_A_DQ<56> PP8707 SM
1
PP OMIT
P4MM P4MM P4MM
12 7 5 FSB_D_L<16> PP608 1
SM PP OMIT 12 7 5 FSB_D_L<16> PP639 1
SM PP OMIT 89 87 5 FB_A_MA<3> PP8708 PP
1
SM OMIT 59 11 7 IN XDP_TCK FUNC_TEST=TRUE
P4MM P4MM P4MM
12 7 5 FSB_DSTBN_L<1> PP609 1
SM OMIT 12 7 5 FSB_DSTBN_L<1> PP640 1
SM OMIT 89 87 FB_A_RDQS<0> PP8709 SM
1 OMIT PLACE NEAR R0705 AND R0706 59 11 7 XDP_TDI FUNC_TEST=TRUE
D 12 7 5 FSB_DSTBP_L<1> PP610 1
SM
PP
PP
P4MM
OMIT
P4MM
12 7 5 FSB_DSTBP_L<1> PP641 1
SM
PP
PP
P4MM
OMIT
P4MM
89 87 FB_A_RDQS<1> PP8710 SM
1
PP
PP
P4MM
OMIT
P4MM 59 11 9 8 7 6 =PP1V05_S0_CPU PP700
1
A
59 11 7
IN
IN XDP_TDO FUNC_TEST=TRUE D
12 7 5 FSB_DINV_L<1> PP611 1
SM
PP OMIT
P4MM
12 7 5 FSB_DINV_L<1> PP642 1
SM
PP OMIT
P4MM
89 87 FB_A_RDQS<2> PP8711 SM
1
PP OMIT
P4MM SM-TP50-TOP
59 11 7 IN XDP_TMS FUNC_TEST=TRUE
12 7 5 FSB_D_L<41> PP612 1
SM OMIT 12 7 5 FSB_D_L<41> PP643 1
SM OMIT 89 87 FB_A_RDQS<3> PP8712 SM
1 OMIT 59 11 7 IN XDP_TRST_L FUNC_TEST=TRUE
FSB_DSTBN_L<2> PP613 1
SM
PP
P4MM
OMIT FSB_DSTBN_L<2> PP644 1
SM
PP
P4MM
OMIT FB_A_RDQS<4> PP8713 SM
1
PP
P4MM
OMIT CPU_GTLREF PP701
1
12 7 5 PP
P4MM
12 7 5 PP
P4MM
89 87 PP
P4MM
7
A 59 IN POWER_BUTTON_L FUNC_TEST=TRUE
12 7 5 FSB_DSTBP_L<2> PP614 1
SM
PP OMIT 12 7 5 FSB_DSTBP_L<2> PP645 1
SM
PP OMIT 89 87 FB_A_RDQS<5> PP8714 SM
1
PP OMIT SM-TP50-TOP
P4MM P4MM P4MM 26 SW_RST_BTN_L FUNC_TEST=TRUE
12 7 5 FSB_DINV_L<2> PP615 1
SM PP OMIT
P4MM
12 7 5 FSB_DINV_L<2> PP646 1
SM PP OMIT
P4MM
89 87 FB_A_RDQS<6> PP8715 PP
1
SM OMIT
P4MM
PP702
1
IN

12 7 5 FSB_D_L<59> PP616 1
SM OMIT 12 7 5 FSB_D_L<59> PP647 1
SM OMIT 89 87 FB_A_RDQS<7> PP8716 SM
1 OMIT A
PP PP PP SM-TP50-TOP
P4MM P4MM P4MM
12 7 5 FSB_DSTBN_L<3> PP617 1
SM PP OMIT 12 7 5 FSB_DSTBN_L<3> PP648 1
SM PP OMIT
P4MM P4MM
12 7 5 FSB_DSTBP_L<3> PP618 1
SM PP OMIT 12 7 5 FSB_DSTBP_L<3> PP649 1
SM PP OMIT 90 87 5 FB_B_DQ<0> PP8720 SM
1
PP OMIT
P4MM P4MM P4MM
12 7 5 FSB_DINV_L<3> PP619 1
SM PP OMIT 12 7 5 FSB_DINV_L<3> PP650 1
SM PP OMIT 90 87 5 FB_B_DQ<8> PP8721 SM
1
PP OMIT
P4MM P4MM P4MM
12 7 5 FSB_LOCK_L PP620 1
SM PP OMIT
P4MM
12 7 5 FSB_LOCK_L PP651 1
SM PP OMIT
P4MM
90 87 5 FB_B_DQ<16> PP8722 SM
1
PP OMIT
P4MM
PLACE NEAR R2800 AND R2801
12 11 7 FSB_CPURST_L PP621 1
SM PP OMIT
P4MM
12 7 FSB_HIT_L PP652 1
SM PP OMIT
P4MM
90 87 5 FB_B_DQ<24> PP8723 SM
1
PP OMIT
P4MM =PP1V8_S3_MEM PP2800
1
12 7 FSB_HITM_L PP653 1
SM OMIT 90 87 5 FB_B_DQ<32> PP8724 PP
1
SM OMIT
29 28 6 A
21 7 CPU_INIT_L PP622 1
SM PP OMIT PP
P4MM P4MM SM-TP50-TOP
P4MM 12 7 FSB_BNR_L PP654 1
SM OMIT 90 87 5 FB_B_DQ<40> PP8725 SM
1 OMIT
21 7 CPU_A20M_L PP623 1
SM
PP OMIT
P4MM FSB_BREQ0_L PP655 1
SM
PP
P4MM
OMIT FB_B_DQ<48> PP8726 SM
1
PP
P4MM
OMIT MEM_VREF
PP2801
1
21 7 CPU_IGNNE_L PP624 1
SM PP OMIT
12 7 PP
P4MM
90 87 5 PP
P4MM
29 28
A
P4MM 12 7 FSB_DBSY_L PP656 1
SM OMIT 90 87 5 FB_B_DQ<56> PP8727 SM
1 OMIT SM-TP50-TOP
21 7 CPU_STPCLK_L PP625 1
SM OMIT PP
P4MM PP
P4MM
CPU_INTR PP626 1
SM
PP
P4MM
OMIT
12 7 FSB_DPWR_L PP657 1
SM PP OMIT
P4MM
90 87 5 FB_B_MA<3> PP8728 SM
1
PP OMIT
P4MM
PP2802
1
21 7 PP
P4MM 12 7 FSB_REQ_L<0> PP658 1
SM OMIT 90 87 FB_B_RDQS<0> PP8729 SM
1 OMIT A MISC GROUND VIAS
21 7 CPU_NMI PP627 1
SM PP OMIT PP
P4MM PP
P4MM SM-TP50-TOP
P4MM 12 7 FSB_REQ_L<1> PP659 1
SM PP OMIT 90 87 FB_B_RDQS<1> PP8730 SM
1
PP OMIT
21 7 CPU_SMI_L PP628 1
SM OMIT P4MM P4MM
PP
P4MM 12 7 FSB_REQ_L<2> PP660 1
SM PP OMIT 90 87 FB_B_RDQS<2> PP8731 SM
1
PP OMIT
P4MM P4MM
34 7 FSB_CLK_CPU_P PP629 1
SM PP OMIT
P4MM
12 7 FSB_REQ_L<3> PP661 1
SM PP OMIT
P4MM
90 87 FB_B_RDQS<3> PP8732 SM
1
PP OMIT
P4MM
ZH500 ZH510 ZH520
34 7 FSB_CLK_CPU_N PP630 1
SM PP OMIT 12 7 FSB_REQ_L<4> PP662 1
SM PP OMIT 90 87 FB_B_RDQS<4> PP8733 SM
1
PP OMIT HOLE-VIA HOLE-VIA HOLE-VIA
P4MM P4MM P4MM 1 1 1
90 87 FB_B_RDQS<5> PP8734 SM
1
PP OMIT
34 12 FSB_CLK_NB_P PP663 1
SM PP OMIT
P4MM FB_B_RDQS<6> PP8735 SM
1
P4MM
90 87 OMIT
34 12 FSB_CLK_NB_N PP664 1
SM OMIT PP
P4MM
PP
P4MM 90 87 FB_B_RDQS<7> PP8736 SM
1
PP OMIT
P4MM ZH501 ZH511 ZH521
VR_PWRGOOD_DELAY PP665 1
SM OMIT HOLE-VIA HOLE-VIA
75 26 14 PP
P4MM HOLE-VIA 1 1
PP666 1 PP8400 PP
1
C 34 21
LAYOUT NOTE: PLACE NEAR U2100
SB_CLK100M_SATA_P PP6C4 1
SM OMIT
14

34 14
NB_RST_IN_L_R

NB_CLK100M_GCLKIN_P PP667
SM

1
SM
PP OMIT
P4MM
OMIT
84 34

84 34
GPU_CLK100M_PCIE_P
GPU_CLK100M_PCIE_N
SM
PP8401 SM
1
PP
OMIT
P4MM
OMIT
P4MM
1
C
PP PP
P4MM P4MM
34 21 SB_CLK100M_SATA_N PP6C5 1
SM PP OMIT
P4MM
34 14 NB_CLK100M_GCLKIN_N PP668 1
SM PP OMIT
P4MM ZH502 ZH512 ZH522
HOLE-VIA HOLE-VIA
38 21 IDE_PDIOR_L PP6C6 1
SM PP OMIT HOLE-VIA 1 1
P4MM 1
38 21 IDE_PDIORDY PP6C7 1
SM PP OMIT
P4MM
38 21 IDE_PDD<9> PP6C8 1
SM PP OMIT
P4MM
ZH503 ZH513 ZH523
DMI_S2N_N<0> PP673 1
SM OMIT HOLE-VIA HOLE-VIA
22 14 PP
P4MM HOLE-VIA 1 1
34 22 PCI_CLK_SB PP6D0 1
SM PP OMIT 22 14 DMI_S2N_P<0> PP674 1
SM PP OMIT 1
P4MM P4MM
41 22 PCIE_A_D2R_P PP6D1 1
SM PP OMIT
P4MM 19 14 MEM_VREF_NB_0 PP6E1 1
SM OMIT
41 22 PCIE_A_D2R_N PP6D2 1
SM PP OMIT
P4MM MEM_VREF_NB_1 PP675 1
SM
PP
P4MM
OMIT ZH504 ZH514 ZH524
19 14 PP
P4MM HOLE-VIA HOLE-VIA
53 22 PCIE_B_D2R_P PP5E1 1
SM PP OMIT 28 15 MEM_A_DQ<7> PP676 1
SM PP OMIT HOLE-VIA 1 1
P4MM P4MM 1
53 22 PCIE_B_D2R_N PP5E2 1
SM PP OMIT 28 15 MEM_A_DQ<14> PP677 1
SM PP OMIT
P4MM P4MM
28 15 MEM_A_DQ<16> PP678 1
SM PP OMIT
22 14 DMI_N2S_P<0> PP6D3 1
SM OMIT P4MM
DMI_N2S_N<0> PP6D4 1
SM
PP
P4MM
OMIT
28 15 MEM_A_DQ<25> PP679 1
SM PP OMIT
P4MM ZH505 ZH515 ZH525
22 14 PP
P4MM MEM_A_DQ<39> PP680 1
SM OMIT HOLE-VIA HOLE-VIA
28 15 PP
P4MM HOLE-VIA 1 1
34 22 SB_CLK100M_DMI_P PP6D5 1
SM PP OMIT 28 15 MEM_A_DQ<47> PP681 1
SM PP OMIT 1
P4MM P4MM
34 22 SB_CLK100M_DMI_N PP6D6 1
SM
PP OMIT
P4MM
28 15 MEM_A_DQ<54> PP682 1
SM
PP OMIT
P4MM
PM_SYSRST_L PP6D7 1 28 15 MEM_A_DQ<59> PP683 1
SM PP OMIT
P4MM
58 26 23 SM OMIT
PM_CLKRUN_L PP6D8 1
SM
PP
P4MM
OMIT
28 15 MEM_A_DQS_P<0> PP684 1
SM PP OMIT
P4MM PLACE NEAR U8900 PLACE NEAR U9000 ZH506 ZH516 ZH526
58 44 23
67 60 PP
P4MM MEM_A_DQS_N<0> PP685 1
SM OMIT HOLE-VIA HOLE-VIA
28 15 PP
P4MM HOLE-VIA 1 1
34 23 SB_CLK14P3M_TIMER PP6D9 1
SM PP OMIT 28 15 MEM_A_DQS_P<1> PP686 1
SM PP OMIT 89 87 FB_A_CKE<0> PP8900 SM
1
PP OMIT 90 87 FB_B_CKE<0> PP9000 SM
1
PP OMIT 1
P4MM P4MM P4MM P4MM
34 23 SB_CLK48M_USBCTLR PP6E0 1
SM PP OMIT 28 15 MEM_A_DQS_N<1> PP687 1
SM PP OMIT 89 87 FB_A_CLK_P<0> PP8901 SM
1
PP OMIT 90 87 FB_B_CLK_P<0> PP9001 SM
1
PP OMIT
P4MM P4MM P4MM P4MM NO_TEST=TRUE
28 15 MEM_A_DQS_P<2> PP688 1
SM OMIT 89 87 FB_A_CLK_N<0> PP8902 PP
1
SM OMIT 90 87 FB_B_CLK_N<0> PP9002 PP
1
SM OMIT 34 IN TP_PCI_CLK_SPARE
MEM_A_DQS_N<2> PP689 1
SM
PP
P4MM
OMIT FB_A_CS_L<0> PP8903 SM
1
P4MM
OMIT FB_B_CS_L<0> PP9003 SM
1
P4MM
OMIT TP_MEM_B_A<14>
NO_TEST=TRUE
ZH507 ZH517 ZH527
28 15 89 87 90 87 29
HOLE-VIA HOLE-VIA
B 28 15 MEM_A_DQS_P<3> PP690 1
SM
PP
PP
P4MM
OMIT
P4MM
89 87 FB_A_WE_L<0> PP8904 SM
1
PP
PP
P4MM
OMIT
P4MM
90 87 FB_B_WE_L<0> PP9004 SM
1
PP
PP
P4MM
OMIT
P4MM
29
IN
IN TP_MEM_B_A<15>
NO_TEST=TRUE
HOLE-VIA
1
1 1 B
28 15 MEM_A_DQS_N<3> PP691 1
SM PP OMIT 89 87 FB_A_CAS_L<0> PP8905 SM
1
PP OMIT 90 87 FB_B_CAS_L<0> PP9005 SM
1
PP OMIT
P4MM P4MM P4MM
28 15 MEM_A_DQS_P<4> PP692 1
SM PP OMIT 89 87 5 FB_A_MA<3> PP8906 SM
1
PP OMIT 90 87 FB_B_RAS_L<0> PP9006 SM
1
PP OMIT
P4MM P4MM P4MM
28 15 MEM_A_DQS_N<4> PP693 1
SM
PP OMIT
P4MM
89 87 FB_A_RAS_L<0> PP8907 SM
1
PP OMIT
P4MM
90 87 5 FB_B_MA<3> PP9007 SM
1
PP OMIT
P4MM ZH508 ZH518 ZH528
MEM_A_DQS_P<5> PP694 1
SM OMIT DRAM_RST PP8908 SM
1 OMIT DRAM_RST PP9008 SM
1 OMIT HOLE-VIA HOLE-VIA
28 15 PP
P4MM
90 89 88 5 PP
P4MM
90 89 88 5 PP
P4MM HOLE-VIA 1 1
28 15 MEM_A_DQS_N<5> PP695 1
SM PP OMIT 89 87 FB_A_WDQS<0> PP8909 SM
1
PP OMIT 90 87 FB_B_WDQS<0> PP9009 SM
1
PP OMIT 1
P4MM P4MM P4MM
28 15 MEM_A_DQS_P<6> PP696 1
SM
PP OMIT 89 87 FB_A_WDQS<1> PP8910 SM
1
PP OMIT 90 87 FB_B_WDQS<1> PP9010 SM
1
PP OMIT
P4MM P4MM P4MM
28 15 MEM_A_DQS_N<6> PP697 1
SM OMIT 89 87 FB_A_WDQS<3> PP8911 SM
1 OMIT 90 87 FB_B_WDQS<3> PP9011 SM
1 OMIT
MEM_A_DQS_P<7> PP698 1
SM
PP
P4MM
OMIT FB_A_WDQS<2> PP8912 SM
1
PP
P4MM
OMIT FB_B_WDQS<2> PP9012 SM
1
PP
P4MM
OMIT ZH509 ZH519 ZH529
28 15 PP
P4MM
89 87 PP
P4MM
90 87 PP
P4MM HOLE-VIA HOLE-VIA
28 15 MEM_A_DQS_N<7> PP699 1
SM PP OMIT 89 87 5 FB_A_DQ<0> PP8913 SM
1
PP OMIT 90 87 5 FB_B_DQ<0> PP9013 SM
1
PP OMIT HOLE-VIA 1 1
P4MM P4MM P4MM 1
89 87 5 FB_A_DQ<8> PP8914 SM
1
PP OMIT 90 87 5 FB_B_DQ<8> PP9014 SM
1
PP OMIT
29 15 MEM_B_DQ<6> PP6A0 1
SM PP OMIT P4MM P4MM
P4MM 89 87 5 FB_A_DQ<16> PP8915 SM
1 OMIT 90 87 5 FB_B_DQ<16> PP9015 SM
1 OMIT
29 15 MEM_B_DQ<8> PP6A1 1
SM PP OMIT
PP
P4MM PP
P4MM
P4MM 89 87 5 FB_A_DQ<24> PP8916 SM
1
PP OMIT 90 87 5 FB_B_DQ<24> PP9016 SM
1
PP OMIT
29 15 MEM_B_DQ<23> PP6A2 1
SM
PP OMIT P4MM P4MM
P4MM
29 15 MEM_B_DQ<25> PP6A3 1
SM PP OMIT
P4MM
29 15 MEM_B_DQ<38> PP6A4 1
SM PP OMIT
P4MM
29 15 MEM_B_DQ<44> PP6A5 1
SM OMIT
29 15 MEM_B_DQ<48> PP6A6 1
SM
PP
P4MM
OMIT
PLACE NEAR U8950 PLACE NEAR U9050
PP
P4MM
29 15 MEM_B_DQ<62> PP6A7 1
SM PP OMIT 89 87 FB_A_CKE<1> PP8920 SM
1
PP OMIT 90 87 FB_B_CKE<1> PP9020 SM
1
PP OMIT
P4MM P4MM P4MM
29 15 MEM_B_DQS_P<0> PP6A8 1
SM PP OMIT
P4MM
89 87 FB_A_CLK_P<1> PP8921 SM
1
PP OMIT
P4MM
90 87 FB_B_CLK_P<1> PP9021 SM
1
PP OMIT
P4MM
29 15 MEM_B_DQS_N<0> PP6A9 1
SM PP OMIT 89 87 FB_A_CLK_N<1> PP8922 SM
1
PP OMIT 90 87 FB_B_CLK_N<1> PP9022 SM
1
PP OMIT
P4MM P4MM P4MM
29 15 MEM_B_DQS_P<1> PP6B0 1
SM PP OMIT 89 87 FB_A_CS_L<1> PP8923 SM
1
PP OMIT 90 87 FB_B_CS_L<1> PP9023 SM
1
PP OMIT
P4MM P4MM P4MM
29 15 MEM_B_DQS_N<1> PP6B1 1
SM PP OMIT 89 87 FB_A_WE_L<1> PP8924 SM
1
PP OMIT 90 87 FB_B_WE_L<1> PP9024 SM
1
PP OMIT
P4MM P4MM P4MM
29 15 MEM_B_DQS_P<2> PP6B2 1
SM PP OMIT 89 87 FB_A_CAS_L<1> PP8925 SM
1
PP OMIT 90 87 FB_B_CAS_L<1> PP9025 SM
1
PP OMIT
29 15 MEM_B_DQS_N<2> PP6B3 1
SM
PP
P4MM
OMIT
P4MM
89 87 FB_A_RAS_L<1> PP8926 SM
1
PP
P4MM
OMIT
P4MM
90 87 FB_B_RAS_L<1> PP9026 SM
1
PP
P4MM
OMIT
P4MM
FUNC TEST 1 OF 2
29 15 MEM_B_DQS_P<3> PP6B4 1
SM PP OMIT 89 87 5 FB_A_MA<3> PP8927 SM
1
PP OMIT 90 87 5 FB_B_MA<3> PP9027 SM
1
PP OMIT
A 29 15

29 15
MEM_B_DQS_N<3>
MEM_B_DQS_P<4>
PP6B5
PP6B6
1
SM
1
SM
PP
P4MM
OMIT
P4MM
OMIT
90 89 88 5

89 87
DRAM_RST
FB_A_WDQS<5>
PP8928 SM
1
PP8929 PP
1
SM
PP
P4MM
OMIT
P4MM
OMIT
90 89 88 5

90 87
DRAM_RST
FB_B_WDQS<5>
PP9028 SM
1
PP9029 PP
1
SM
PP
P4MM
OMIT
P4MM
OMIT NOTICE OF PROPRIETARY PROPERTY
A
PP
P4MM P4MM P4MM
29 15 MEM_B_DQS_N<4> PP6B7 1
SM PP OMIT 89 87 FB_A_WDQS<6> PP8930 SM
1
PP OMIT 90 87 FB_B_WDQS<6> PP9030 SM
1
PP OMIT
P4MM P4MM P4MM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
29 15 MEM_B_DQS_P<5> PP6B8 1
SM PP OMIT 89 87 FB_A_WDQS<4> PP8931 SM
1
PP OMIT 90 87 FB_B_WDQS<7> PP9031 SM
1
PP OMIT PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
P4MM P4MM P4MM AGREES TO THE FOLLOWING
29 15 MEM_B_DQS_N<5> PP6B9 1
SM PP OMIT 89 87 FB_A_WDQS<7> PP8932 SM
1
PP OMIT 90 87 FB_B_WDQS<4> PP9032 SM
1
PP OMIT
P4MM P4MM P4MM I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
29 15 MEM_B_DQS_P<6> PP6C0 1
SM PP OMIT 89 87 5 FB_A_DQ<32> PP8933 SM
1
PP OMIT 90 87 5 FB_B_DQ<32> PP9033 SM
1
PP OMIT
P4MM P4MM P4MM II NOT TO REPRODUCE OR COPY IT
29 15 MEM_B_DQS_N<6> PP6C1 1
SM PP OMIT 89 87 5 FB_A_DQ<40> PP8934 SM
1
PP OMIT 90 87 5 FB_B_DQ<40> PP9034 SM
1
PP OMIT
P4MM P4MM P4MM III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
29 15 MEM_B_DQS_P<7> PP6C2 1
SM PP OMIT
P4MM
89 87 5 FB_A_DQ<48> PP8935 SM
1
PP OMIT
P4MM
90 87 5 FB_B_DQ<48> PP9035 SM
1
PP OMIT
P4MM
29 15 MEM_B_DQS_N<7> PP6C3 1
SM PP OMIT 89 87 5 FB_A_DQ<56> PP8936 PP
1
SM OMIT 90 87 5 FB_B_DQ<56> PP9036 PP
1
SM OMIT SIZE DRAWING NUMBER REV.
P4MM P4MM P4MM
D 051-6949 09
APPLE COMPUTER INC.
SCALE SHT OF
NONE 5 111
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP3V3_S0
88 76 61 59 41 26 10 6

PP12V_S5
"S0" RAILS
97 88 75 6 PP5V_S0
88 83 81 80 79 78 6 5

ONLY ON IN RUN
"S3" RAILS "S5" RAILS
83 81 80 79 59 6 5 PP5V_S5 ON IN RUN AND SLEEP
88 76 6 PP12V_S0 ALWAYS ON WHEN UNIT HAS AC POWER (TRICKLE)

79 77 76 66 65 59 26 6 5 PP3V3_S5
83 81 80
CRITICAL 79 PP0V9_S0 =PP0V9_S0_MEMVTT_LDO 31 80 79 77 76 66 65 59 26 6 5 PP3V3_S5 =PP3V3_S5_SB 23 25 26
1 MAKE_BASE=TRUE 77 PP1V2_S3 =PP1V2_S3_LAN 42 83 81 MAKE_BASE=TRUE
CRITICAL
C699 VOLTAGE=0.9V
MIN_LINE_WIDTH=0.3MM
=PP0V9_S0_MEM_TERM 30 MAKE_BASE=TRUE
VOLTAGE=1.8V
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM
=PP3V3_S5_SB_USB 22

330UF MIN_NECK_WIDTH=0.15MM MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM =PP3V3_S5_SB_PM


J600 20%
2 6.3V
MIN_NECK_WIDTH=0.2MM
=PP3V3_S5_SB_VCCSUS3_3
11 23

NOSTUFF HM9607E-P2 ELEC


24 25
M-RT-TH1 CASE-C1 =PP3V3_S5_SB_VCCSUS3_3_USB 24 25
1
R601 1 2 76 75 5 PPVCORE_CPU =PPVCORE_S0_CPU 8 9 76 =PP3V3_S5_SB_3V3_1V5_VCCSUSHDA 24

D PU ON PAGE 76 IS USED 5%
10K
1/16W
3
5
4
6
MAKE_BASE=TRUE
VOLTAGE=1.25V
MIN_LINE_WIDTH=0.6MM 79 5 PP1V8_S3 =PP1V8_S3_MEM_NB 6 14 16 19
=PP3V3_S5_SB_IO 22 27 D
MF-LF MIN_NECK_WIDTH=0.15MM MAKE_BASE=TRUE =PP3V3_S5_FW 44 45 46
2 402 VOLTAGE=1.8V =PP1V8_S3_MEM_NB 6 14 16 19
7 8 MIN_LINE_WIDTH=0.6MM =PP3V3_S5_SMC 58 59
MIN_NECK_WIDTH=0.2MM =PP1V8_S3_MEM 5 28 29
9 10
=PP1V8_S0_MEMVTT 31
76 SYS_POWERFAIL_L 11 12 81 34 PP1V05_S0 =PPVCORE_S0_NB 16 19 =PP3V3_S5_DEBUG 60
MAKE_BASE=TRUE
94 LCD_PWM 13 14 PANEL_ID 94 VOLTAGE=1.05V =PP1V05_S0_CPU 5 7 8 9 11 59 =PP3V3_S5_ROM 63
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.15MM =PP1V05_S0_FSB_NB 5 12 19
83 59 53 6 PP3V3_S3
=PP1V05_S0_NB_VTT 17 19 MAKE_BASE=TRUE
VOLTAGE=3.3V =PP3V3_S3_ENET 41 42 43 83 81 80 79 59 6 5 PP5V_S5 =PP5V_S5_SB 25
=PP1V05_S0_NB 19 MIN_LINE_WIDTH=0.6MM MAKE_BASE=TRUE
VOLTAGE=0 MIN_NECK_WIDTH=0.25MM =PP3V3_S3_TPM 67 VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM =PP1V05_S0_SB_CPU_IO 21 24 25 MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM =PP3V3_S3_1V2REG 77 MIN_NECK_WIDTH=0.2MM
=PPVCORE_S0_SB 24 25
=PP3V3_S3_BT 47
0
=PP3V3_S3_USB 49

80 79 77 76 66 65 59 26 6 5 PP3V3_S5 =PP3V3_S3_VGASYNC 97
83 81
88 83 81 80 79 78 6 5 PP12V_S5 =PP12V_S5_FW 46
80 PP1V5_S0 =PP1V5_S0_CPU 8 MAKE_BASE=TRUE
MAKE_BASE=TRUE VOLTAGE=12V =PP12V_S5_CPU
1 C610 VOLTAGE=1.5V
MIN_LINE_WIDTH=0.6MM
=PP1V5_S0_NB_PCIE 13 19
PP5V_S3 =PP5V_S3_USB
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
76

0.1UF MIN_NECK_WIDTH=0.15MM =PP1V5_S0_NB_VCCAUX 6 16 17 19


83 59
MAKE_BASE=TRUE
47
20% 10V VOLTAGE=5V =PP5V_S3_BNDI 47
5 U601
74LVC1G04DBVG4
2 CERM 402 =PP1V5_S0_NB_VCCD_HMPLL 17 19 MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM =PP5V_S0_MEMVTT 31

88 79 77 58 23 PM_SLP_S3_L 2 4 SYS_PWRUP_L
IN
SOT23-5
3
=PP1V5_S0_NB_VCCAUX 6 16 17 19

=PP1V5_S0_NB_PLL 19

=PP1V5_S0_NB 19

=PP1V5_S0_NB_TVDAC 19

=PP1V5_S0_NB_3GPLL 19

C 80 79 77 76 66 65 59 26 6 5
83 81
PP3V3_S5 =PP1V5_S0_SB_VCC1_5_A_ARX
=PP1V5_S0_SB_VCCSATAPLL
24 25

24 25
GND RAILS C
=PP1V5_S0_SB_VCC1_5_A_ATX
1 C600 =PP1V5_S0_SB_VCCUSBPLL
24 25
XW601
SM NOSTUFF
0.1UF 24 25
20% =PP1V5_S0_SB_VCC1_5_A_USB_CORE 24 25 74 GND_AUDIO 1 2
10V
2 CERM
R618 =PP1V5_S0_SB_VCC1_5_A
CRITICAL
402
68 =PP1V5_S0_SB
24 25

25
XW602
SM NOSTUFF
1 2 94 GPU_PWM_RST_L
U600 5% 1/16W
OUT
=PP1V5_S0_AIRPORT 53 74 72 GND_AUDIO_SPKRAMP 1 2
14 74LC125 402 MF-LF
22 PLT_RST_L 2 3 U600_3
IN
125 R619
7 1 TSSOP 68
1 2 58 SMC_LRESET_L OUT
5% 1/16W
402 MF-LF
88 77 PP2V5_S0
MAKE_BASE=TRUE
VOLTAGE=3.3V
R611 MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.15MM
CRITICAL
1
68 2 NB_RST_IN_L
U600 5% 1/16W
14
OUT
CHASSIS GND
14 74LC125 402 MF-LF =PP2V5_S0_NB_VCCA_3GBG 17 19 NOSTUFF
5 6 U600_6 R603
125 R612 0
GND_CHASSIS_IO_LEFT 1 2
7 4 TSSOP
1
68 2
MAKE_BASE=TRUE
84 PEG_RESET_L OUT VOLTAGE=0 5%
MIN_LINE_WIDTH=0.6MM 1/16W
5% 1/16W MIN_NECK_WIDTH=0.2MM MF-LF
402 MF-LF 402
74 73 GND_CHASSIS_AUDIO_EXTERNAL
88 76 61 59 41 26 10 6 PP3V3_S0 =PP3V3_S0_NB_PM
MAKE_BASE=TRUE
VOLTAGE=3.3V =PP3V3_S0_NB_VCC_HV 17 19 47 GND_CHASSIS_USB
CRITICAL R614 MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.15MM =PP3V3_S0_NB_TVDAC 19

B U600 1
68 2 42 ENET_RST_L OUT
=PP3V3_S0_SB 22 25 B
14 74LC125 5% 1/16W =PP3V3_S0_SB_GPIO 21 23
402 MF-LF
9 8 U600_8 =PP3V3_S0_SB_VCC3_3 24 25
125 R615 =PP3V3_S0_SB_VCC3_3_PCI 24 25
7 10 TSSOP 68 46 GND_CHASSIS_FIREWIRE GND_CHASSIS_IO_RIGHT
1 2 67 TPM_LRESET_L OUT
=PP3V3_S0_SB_VCC3_3_IDE 24 25 MAKE_BASE=TRUE
97 GND_CHASSIS_VGA VOLTAGE=0
5% 1/16W =PP3V3_S0_SB_PCI 26 MIN_LINE_WIDTH=0.6MM
402 MF-LF 43 GND_CHASSIS_RJ45 MIN_NECK_WIDTH=0.2MM
=PP3V3_S0_SB_PM 26

=PP3V3_S0_PATA 38

=PP3V3_S0_FAN 59 65 66

CRITICAL R616 =PP3V3_S0_HD_TSENS 66


68
U600 1 2 53 AIRPORT_RST_L OUT =PP3V3_S0_ODD_TSENS 66
OMIT
14 74LC125 5% 1/16W =PP3V3_S0_SB_3V3_1V5_VCCHDA OMIT GND_CHASSIS_AUDIO_INTERNAL
12 11 U600_11
402 MF-LF
=PP3V3_S0_TPM
24 25

ZH601
73
ZH606
67 160R138
125 R617 =PPSPD_S0_MEM 28 29
4P25R3P5 47 GND_CHASSIS_BNDI 1
7 13 TSSOP
1
68 2 DEBUG_RST_L =PP3V3_S0_CK410
ZH701P1 1 MIN_NECK_WIDTH=0.2MM
60
OUT 33 34 MIN_LINE_WIDTH=0.6MM
VOLTAGE=0
5% 1/16W =PP3V3_S0_IMVP 75 MAKE_BASE=TRUE
402 MF-LF OMIT
=PP3V3_S0_AUDIO NOSTUFF
68 72 73 74
ZH602
=PP3V3_S0_PCI 44
1 C601 4P25R3P5
=PP3V3_S0_SB_VCCLAN3_3 24 25
0.01UF ZH702P1 1
20%
=PP3V3_S0_AIRPORT 53 2 16V
CERM
402 OMIT
=PP3V3_S0_2V5REG
PP5V_S5 PP3V3_S3 PP3V3_S0 =PP3V3_S0_NB
77
NOSTUFF ZH603
83 81 80 79 59 6 5 83 59 53 6 88 76 61 59 41 26 10 6 14 19 20
1 4P25R3P5
C602 ZH703P1 1
1DEVELOPMENT 1DEVELOPMENT 1DEVELOPMENT 0.01UF
R602 R600 R605 20%

5%
330
5%
330 330
5%
97 88 75 6 PP5V_S0
MAKE_BASE=TRUE
VOLTAGE=5V
=PP5V_S0_SB
=PP5V_S0_PATA
25
2 16V
CERM NOSTUFF Power Conn / Alias
1/10W 1/10W 1/10W MIN_LINE_WIDTH=0.6MM
XW604
38 402 1 C603
A MF-LF
2 603
ITS_PLUGGED_IN
MF-LF
2 603
ITS_ALIVE
MF-LF
2 603
ITS_RUNNING
MIN_NECK_WIDTH=0.15MM

1
SM OMIT
2 PP5V_S0_AUDIO =PP5V_S0_AUDIO 68
0.01UF
20%
2 16V NOTICE OF PROPRIETARY PROPERTY
A
CERM
MAKE_BASE=TRUE 402
1 1 1
=PP5V_S0_DEBUG 60
DEVELOPMENT DEVELOPMENT DEVELOPMENT THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
LED601 LED602 LED600 AGREES TO THE FOLLOWING
GREEN-3.6MCD GREEN-3.6MCD GREEN-3.6MCD
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
2
2.0X1.25MM-SM
2 2.0X1.25MM-SM
2 2.0X1.25MM-SM
88 76 6 PP12V_S0 =PP12V_S0_FAN 65 66
SILKSCREEN:1 SILKSCREEN:2 SILKSCREEN:RUN MAKE_BASE=TRUE II NOT TO REPRODUCE OR COPY IT
VOLTAGE=12V
MIN_LINE_WIDTH=0.6MM
XW605
SM OMIT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
MIN_NECK_WIDTH=0.15MM
1 2 PP12V_S0_AUDIO_SPKRAMP =PP12V_S0_AUDIO_SPKRAMP 72
MAKE_BASE=TRUE SIZE DRAWING NUMBER REV.

D 051-6950 06
APPLE COMPUTER INC.
SCALE SHT OF
NONE 6 111

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT

J0700 =PP1V05_S0_CPU
5 6 7 8 9 11 59
12
IO FSB_A_L<3> J4 A3* YONAH-SKT ADS* H1 12 FSB_ADS_L IO
CPU SCH AND PCB
12 FSB_A_L<4> L4 A4* BNR* E2 12 5 FSB_BNR_L
IO CPU IO 1
R0702 SYMBOL NEED TO CHECK
12 FSB_A_L<5> M3 A5* BPRI* G5 12 FSB_BPRI_L
IO BGA IO
54.9
12 5 FSB_A_L<6> K5 A6* 1%
IO (1 OF 4) DEFER* H5 12 FSB_DEFER_L 1/16W
FSB_A_L<7> IO
12
IO M1 A7* MF-LF
DRDY* F21 12 FSB_DRDY_L IO 2 402
12
IO
FSB_A_L<8> N2 A8*
DBSY* E1 12 5 FSB_DBSY_L IO
12 IO FSB_A_L<9> J1 A9*

ADDR GROUP0
12
IO FSB_A_L<10> N3 A10* BR0* F1 12 5 FSB_BREQ0_L IO
PLACE TESTPOINT ON
12
IO FSB_A_L<11> P5 A11*
IERR* D20 FSB_IERR_L FSB_IERR# WITH A GND
D

CONTROL
12 FSB_A_L<12> P2 A12*
D 12
IO

IO
FSB_A_L<13> L1 A13*
INIT* B3 21 5 CPU_INIT_L IN 0.1" AWAY

12
IO FSB_A_L<14> P4 A14* LOCK* H4 12 5 FSB_LOCK_L IO
12
IO
FSB_A_L<15> P1 A15*
RESET* B1 12 11 5 FSB_CPURST_L IN
12
IO
FSB_A_L<16> R1 A16*
RS0* F3 12 FSB_RS_L<0> IN
12 5
IO
FSB_ADSTB_L<0> L2 ADSTB0*
RS1* F4 12 FSB_RS_L<1> IN
RS2* G3 12 FSB_RS_L<2> =PP1V05_S0_CPU
IN
12 5
IO FSB_REQ_L<0> K3 REQ0*
TRDY* G2 12 FSB_TRDY_L 5 6 7 8 9 11 59
IN
12 5 IO FSB_REQ_L<1> H2 REQ1*
12 5
IO
FSB_REQ_L<2> K2 REQ2* HIT* G6 12 5 FSB_HIT_L IO
12 5
IO FSB_REQ_L<3> J3 REQ3* HITM* E4 12 5 FSB_HITM_L IO
12 5
IO FSB_REQ_L<4> L5 REQ4* NOSTUFF
BPM0* AD4 11 XDP_BPM_L<0> 1
IO R0703

XDP/ITP SIGNALS
12
IO
FSB_A_L<17> Y2 A17* OMIT
BPM1* AD3 11 XDP_BPM_L<1> 54.9
IO
12
IO FSB_A_L<18> U5 A18* 1%
BPM2* AD1 11 XDP_BPM_L<2> 1/16W
12
IO FSB_A_L<19> R3 A19*
BPM3* AC4 11 XDP_BPM_L<3>
IO

IO
MF-LF
402
J0700
12 FSB_A_L<20> W6 A20* 2
YONAH-SKT

ADDR GROUP1
IO
PRDY* AC2 11 XDP_BPM_L<4> 12 5 FSB_D_L<0> E22 D0* D32* AA23 12 FSB_D_L<32>
IO IO IO
12
IO
FSB_A_L<21> U4 A21*
PREQ* AC1 11 XDP_BPM_L<5> 12 FSB_D_L<1> F24 D1*
CPU D33* AB24 12 FSB_D_L<33>
12
IO
FSB_A_L<22> Y5 A22* IO IO BGA IO
59 11 7 5 XDP_TCK
FSB_A_L<23>
TCK AC5 IN 12
IO FSB_D_L<2> E26 D2* (2 OF 4) D34* V24 12 FSB_D_L<34> IO
12
IO U2 A23* NO SPACE FOR ITP
TDI AA6 59 11 7 5 XDP_TDI IN 12 IO FSB_D_L<3> H22 D3* D35* V26 12 FSB_D_L<35> IO
FSB_A_L<24> R4 A24* 1
12
IO 59 11 5 XDP_TDO R0704 CONNECTOR, NEED TERM
TDO AB3 IO FSB_D_L<4> F23 D4* D36* W25 12 FSB_D_L<36>
12
OUT IO
12
IO FSB_A_L<25> T5 A25* 68 ON ITP SIGNALS?
59 11 7 5 XDP_TMS
TMS AB5 IO FSB_D_L<5> G25 D5* D37* U23 12 FSB_D_L<37>
5% 12
IN IO
12
IO FSB_A_L<26> T3 A26* 1/16W
59 11 5 XDP_TRST_L
TRST* AB6 IN MF-LF 12
IO FSB_D_L<6> E25 D6* D38* U25 12 FSB_D_L<38>
IO
FSB_A_L<27> W3 A27*

DATA GRP0

DATA GRP2
12 5 402
IO 2
11 XDP_DBRESET_L
IO FSB_D_L<7>
DBR* C20 26 12 E23 D7* D39* U22 12 FSB_D_L<39>
OUT IO
12
IO
FSB_A_L<28> W5 A28* NOTE: DUMMY PIN
PIN ACTUALLY DRIVEN BY ITP 12
IO
FSB_D_L<8> K24 D8* D40* AB25 12 FSB_D_L<40>
IO
12
IO FSB_A_L<29> Y4 A29* CPU_PROCHOT_L TO SMC
THERM PROCHOT* D21 59 CPU_PROCHOT_L IN
12
IO
FSB_D_L<9> G24 D9* D41* W22 12 5 FSB_D_L<41>
IO
12
IO
FSB_A_L<30> W2 A30* AND CPU VR TO INFORM
THERMDA A24 10 CPU_THERMD_P OUT
12
IO FSB_D_L<10> J24 D10* D42* Y23 12 FSB_D_L<42>
IO

C 12

12 5
IO

IO
FSB_A_L<31>
FSB_ADSTB_L<1>
Y1 A31*
V4 ADSTB1*
THERMDC A25 10 CPU_THERMD_N OUT
CPU IS HOT
12

12
IO FSB_D_L<11>
FSB_D_L<12>
J23 D11*
H26 D12*
D43*
D44*
AA26
Y26
12 FSB_D_L<43>

12 FSB_D_L<44>
IO C
IO IO
THERMTRIP* C7 59 21 14 PM_THRMTRIP_L OUT
21 5
IN CPU_A20M_L A6 A20M* 12
IO
FSB_D_L<13> F26 D13* D45* Y22 12 FSB_D_L<45>
IO
21
OUT CPU_FERR_L A5 FERR* 12
IO FSB_D_L<14> K22 D14* D46* AC26 12 FSB_D_L<46>
IO
PM_THRMTRIP#
21 5
IN
CPU_IGNNE_L C4 IGNNE* 12
IO
FSB_D_L<15> H25 D15* D47* AA24 12 FSB_D_L<47>
IO
HCLK

SHOULD CONNECT TO
BCLK0 A22 34 5 FSB_CLK_CPU_P IN
12 5
IO
FSB_DSTBN_L<0> H23 DSTBN0* DSTBN2* W24 12 5 FSB_DSTBN_L<2>
IO
21 5
IN CPU_STPCLK_L D5 STPCLK* ICH6-M AND GMCH
BCLK1 A21 34 5 FSB_CLK_CPU_N IN 12 5
IO
FSB_DSTBP_L<0> G22 DSTBP0* DSTBP2* Y25 12 5 FSB_DSTBP_L<2>
IO
21 5
IN
CPU_INTR C6 LINT0 WITHOUT T-ING (NO
12 5
IO
FSB_DINV_L<0> J26 DINV0* DINV2* V23 12 5 FSB_DINV_L<2>
IO
21 5
IN
CPU_NMI B4 LINT1 STUB)
21 5
IN
CPU_SMI_L A3 SMI* 12 5
IO FSB_D_L<16> N22 D16* D48* AC22 12 FSB_D_L<48> IO

IO FSB_D_L<17>
12 K25 D17* D49* AC23 12 FSB_D_L<49>
IO
TP_CPU_A32_L AA1 RSVD1
IO FSB_D_L<18>
12 P26 D18* D50* AB22 12 FSB_D_L<50>
IO
TP_CPU_A33_L AA4 RSVD2 RSVD12 T22 TP_CPU_EXTBREF
RESERVED

IO FSB_D_L<19>
12 R23 D19* D51* AA21 12 FSB_D_L<51>
IO
TP_CPU_A34_L AB2 RSVD3
IO FSB_D_L<20>
12 L25 D20* D52* AB21 12 FSB_D_L<52>
TP_CPU_A35_L IO
AA3 RSVD4
RSVD13 D2 TP_CPU_SPARE0 12
IO FSB_D_L<21> L22 D21* D53* AC25 12 FSB_D_L<53>
IO
TP_CPU_A36_L M4 RSVD5

DATA GRP1

DATA GRP3
LAYOUT NOTE:
RSVD14 F6 TP_CPU_SPARE1 12
IO FSB_D_L<22> L23 D22* D54* AD20 12 FSB_D_L<54>
IO
TP_CPU_A37_L N5 RSVD6 SPARE[7-0],HFPLL: COMP0,2 CONNECT WITH ZO=27.4OHM, MAKE
RSVD15 D3 TP_CPU_SPARE2 12 IO FSB_D_L<23> M23 D23* D55* AE22 12 FSB_D_L<55> IO
TP_CPU_A38_L T2 RSVD7 ROUTE TO TP VIA AND TRACE LENGTH SHORTER THAN 0.5".
RSVD16 C1 TP_CPU_SPARE3 12
IO FSB_D_L<24> P25 D24* D56* AF23 12 FSB_D_L<56>
IO
TP_CPU_A39_L V3 RSVD8 PLACE GND VIA W/IN 1000 MILS COMP1,3 CONNECT WITH ZO=55OHM, MAKE
RSVD17 AF1 TP_CPU_SPARE4 12
IO FSB_D_L<25> P22 D25* D57* AD24 12 FSB_D_L<57>
IO
TP_CPU_APM0_L B2 RSVD9 TRACE LENGTH SHORTER THAN 0.5".
RSVD18 D22 TP_CPU_SPARE5 12
IO FSB_D_L<26> P23 D26* D58* AE21 12 FSB_D_L<58>
IO
TP_CPU_APM1_L C3 RSVD10
RSVD19 C23 TP_CPU_SPARE6 12
IO FSB_D_L<27> T24 D27* D59* AD21 12 5 FSB_D_L<59>
IO
TP_CPU_HFPLL B25 RSVD11 RSVD20 C24 TP_CPU_SPARE7 12
IO FSB_D_L<28> R24 D28* D60* AE25 12 FSB_D_L<60>
IO

IO FSB_D_L<29>
12 L26 D29* D61* AF25 12 FSB_D_L<61>
IO
59 11 9 8 7 6 5 =PP1V05_S0_CPU
12
IO FSB_D_L<30> T25 D30* D62* AF22 12 FSB_D_L<62>
IO

1
12
IO FSB_D_L<31> N24 D31* D63* AF26 12 FSB_D_L<63>
IO R0716
R0705 1 2 27.4
=PP1V05_S0_CPU 12 5
IO
FSB_DSTBN_L<1> M24 DSTBN1* DSTBN3* AD23 12 5 FSB_DSTBN_L<3>
IO
1K 402
1% 12 5 FSB_DSTBP_L<1> N25 DSTBP1* DSTBP3* AE24 12 5 FSB_DSTBP_L<3>

B 5 6 7 8 9 11 59

2
1/16W
MF-LF
402
12 5
IO
IO FSB_DINV_L<1> M26 DINV1* DINV3* AC20 12 5 FSB_DINV_L<3>
IO
IO
R0717 1 2 54.9 B
5 CPU_GTLREF 1% 402
AD26 GTLREF COMP0 R26 CPU_COMP<0>
R0720 A2 NC MISC COMP1 U26 CPU_COMP<1> R0718 1 2 27.4
54.9 1
59 11 7 5 XDP_TMS 1 2 R0706 LAYOUT NOTE: 0.5" MAX LENGTH
COMP2 U1 CPU_COMP<2>
2.0K CPU_TEST1 C26 TEST1 R0719
1% 1% COMP3 V1 CPU_COMP<3> 1 2 54.9
1/16W 1/16W
MF-LF MF-LF CPU_TEST2 D25 TEST2 1% 402
402 402 DPRSTP* E5 75 21 CPU_DPRSTP_L IN
2
34
OUT CPU_BSEL<0> B22 BSEL0 DPSLP* B5 21 CPU_DPSLP_L
IN
R0721 34
OUT CPU_BSEL<1> B23 BSEL1 DPWR* D24 12 5 FSB_DPWR_L
IN
54.9
59 11 7 5 XDP_TDI 1 2 34
OUT
CPU_BSEL<2> C21 BSEL2 PWRGOOD D6 21 CPU_PWRGD
IN
1% SLP* D7 12 FSB_SLPCPU_L
IN
1/16W
MF-LF NOSTUFF PSI* AE6 75 CPU_PSI_L IN
402
R0730
0
1 2
R0722
54.9
59 11 7 5 XDP_TCK 1 2 402
1% 1 1NOSTUFF
1/16W R0707 R0712
MF-LF 51 1K
402 5% 5%
1/16W 1/16W
MF-LF MF-LF
2 402 2 402

CPU 1 OF 2-FSB
A SYNC_MASTER=MASTER

NOTICE OF PROPRIETARY PROPERTY


SYNC_DATE=05/03/2005
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

APPLE COMPUTER INC.


D 051-6949 09

SCALE SHT OF
7 111
NONE

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT

A4 VSS_1 P6
A8 VSS_2
J0700 VSS_82
VSS_83 P21
YONAH-SKT
A11 VSS_3 VSS_84 P24
=PPVCORE_S0_CPU
6 8 9 76 A14 VSS_4
CPU VSS_85 R2
=PPVCORE_S0_CPU 6 8 9 76 BGA
OMIT A16 VSS_5 VSS_86 R5
(4 OF 4)
A19 VSS_6 VSS_87 R22
A7 VCC_1 VCC_68 AB20
A9 VCC_2
J0700 VCC_69 AB7
A23 VSS_7 VSS_88 R25
YONAH-SKT A26 VSS_8 VSS_89 T1
A10 VCC_3 VCC_70 AC7
A12 VCC_4 CPU VCC_71 AC9
B6 VSS_9 VSS_90 T4
BGA B8 VSS_10 VSS_91 T23

D
A13 VCC_5
A15 VCC_6
(3 OF 4)
VCC_72 AC12
VCC_73 AC13
B11 VSS_11 VSS_92 T26 D
B13 VSS_12 VSS_93 U3
A17 VCC_7 VCC_74 AC15
B16 VSS_13 VSS_94 U6
A18 VCC_8 VCC_75 AC17
B19 VSS_14 VSS_95 U21
A20 VCC_9 VCC_76 AC18
B21 VSS_15 VSS_96 U24
B7 VCC_10 VCC_77 AD7
B24 VSS_16 VSS_97 V2
B9 VCC_11 VCC_78 AD9
C5 VSS_17 VSS_98 V5
B10 VCC_12 VCC_79 AD10
C8 VSS_18 VSS_99 V22
B12 VCC_13 VCC_80 AD12
C11 VSS_19 VSS_100 V25
B14 VCC_14 VCC_81 AD14
C14 VSS_20 VSS_101 W1
B15 VCC_15 VCC_82 AD15
C16 VSS_21 VSS_102 W4
B17 VCC_16 VCC_83 AD17
C19 VSS_22 VSS_103 W23
B18 VCC_17 VCC_84 AD18
C2 VSS_23 VSS_104 W26
B20 VCC_18 VCC_85 AE9
C22 VSS_24 VSS_105 Y3
C9 VCC_19 VCC_86 AE10
C25 VSS_25 VSS_106 Y6
C10 VCC_20 VCC_87 AE12
D1 VSS_26 VSS_107 Y21
C12 VCC_21 VCC_88 AE13
D4 VSS_27 VSS_108 Y24
C13 VCC_22 VCC_89 AE15
D8 VSS_28 VSS_109 AA2
C15 VCC_23 VCC_90 AE17
D11 VSS_29 VSS_110 AA5
C17 VCC_24 VCC_91 AE18
D13 VSS_30 VSS_111 AA8
C18 VCC_25 VCC_92 AE20
D16 VSS_31 VSS_112 AA11
D9 VCC_26 VCC_93 AF9
D19 VSS_32 VSS_113 AA14
D10 VCC_27 VCC_94 AF10
D23 VSS_33 VSS_114 AA16
D12 VCC_28 VCC_95 AF12
D26 VSS_34 VSS_115 AA19
D14 VCC_29 VCC_96 AF14
E3 VSS_35 VSS_116 AA22
D15 VCC_30 VCC_97 AF15
E6 VSS_36 VSS_117 AA25
D17 VCC_31 VCC_98 AF17
C D18 VCC_32
E7 VCC_33
VCC_99 AF18
VCC_100 AF20
E8 VSS_37
E11 VSS_38
VSS_118 AB1
VSS_119 AB4
C
E14 VSS_39 VSS_120 AB8
E9 VCC_34
E16 VSS_40 VSS_121 AB11
E10 VCC_35 VCCP_1 V6 =PP1V05_S0_CPU 5 6 7 9 11 59
E19 VSS_41 VSS_122 AB13
E12 VCC_36 VCCP_2 G21
E21 VSS_42 VSS_123 AB16
E13 VCC_37 VCCP_3 J6
E24 VSS_43 VSS_124 AB19
E15 VCC_38 VCCP_4 K6
F5 VSS_44 VSS_125 AB23
E17 VCC_39 VCCP_5 M6
F8 VSS_45 VSS_126 AB26
E18 VCC_40 VCCP_6 J21
F11 VSS_46 VSS_127 AC3
E20 VCC_41 VCCP_7 K21 =PP1V5_S0_CPU 6 8
F13 VSS_47 VSS_128 AC6
F7 VCC_42 VCCP_8 M21
F16 VSS_48 VSS_129 AC8
F9 VCC_43 VCCP_9 N21
F19 VSS_49 VSS_130 AC11
F10 VCC_44 VCCP_10 N6
F2 VSS_50 VSS_131 AC14
F12 VCC_45 VCCP_11 R21
F22 VSS_51 VSS_132 AC16
F14 VCC_46 VCCP_12 R6 C0800 1 1
C0801
0.01UF 10UF F25 VSS_52 VSS_133 AC19
F15 VCC_47 VCCP_13 T21 20% 20% G4 VSS_53 VSS_134 AC21
F17 VCC_48 VCCP_14 T6 16V
2 2
6.3V
CERM X5R
G1 VSS_54 VSS_135 AC24
F18 VCC_49 VCCP_15 V21 =PP1V5_S0_CPU 6 8
402 603
G23 VSS_55 VSS_136 AD2
F20 VCC_50 VCCP_16 W21
G26 VSS_56 VSS_137 AD5
AA7 VCC_51 VCCA=1.5 ONLY
H3 VSS_57 VSS_138 AD8
AA9 VCC_52
AA10 VCC_53 VCCA B26 H6 VSS_58 VSS_139 AD11
H21 VSS_59 VSS_140 AD13
AA12 VCC_54
H24 VSS_60 VSS_141 AD16
AA13 VCC_55 VID0 AD6 75 CPU_VID<0> OUT
J2 VSS_61 VSS_142 AD19
AA15 VCC_56 VID1 AF5 75 CPU_VID<1> OUT
J5 VSS_62 VSS_143 AD22
AA17 VCC_57 VID2 AE5 75 CPU_VID<2> =PPVCORE_S0_CPU 6 8 9 76
OUT
J22 VSS_63 VSS_144 AD25
B AA18 VCC_58
AA20 VCC_59
VID3 AF4
VID4 AE3
75

75
CPU_VID<3>
CPU_VID<4>
OUT
OUT 1
J25 VSS_64 VSS_145 AE1 B
R0802 K1 VSS_65 VSS_146 AE4
AB9 VCC_60 VID5 AF2 75 CPU_VID<5> OUT
AC10 VCC_61
100 K4 VSS_66 VSS_147 AE8
VID6 AE2 75 CPU_VID<6> OUT 1%
1/16W K23 VSS_67 VSS_148 AE11
AB10 VCC_62 MF-LF
402 K26 VSS_68 VSS_149 AE14
AB12 VCC_63 2
LAYOUT NOTE: L3 VSS_69 VSS_150 AE16
AB14 VCC_64
PROVIDE A TEST POINT (WITH NO STUB) L6 VSS_70 VSS_151 AE19
AB15 VCC_65 VCCSENSE AF7 75 CPU_VCCSENSE_P OUT
TO CONNECT A DIFFERENCTIAL PROBE L21 VSS_71 VSS_152 AE23
AB17 VCC_66
BETWEEN VCCSENSE AND VSSSENSE AT THE L24 VSS_72 VSS_153 AE26
AB18 VCC_67 VSSSENSE AE7 75 CPU_VCCSENSE_N OUT
LOCATION WHERE THE TWO 54.9 OHM M2 VSS_73 VSS_154 AF3
RESISTORS TERMINATE THE 55 OHM M5 VSS_74 VSS_155 AF6
1 M22 VSS_75 VSS_156 AF8
LAYOUT NOTE: CONNECT R0802-03
R0803 TRANSMISSION LINE
100 M25 VSS_76 VSS_157 AF11
TO VCCSENSE_P/N WITH NO STUB 1%
1/16W N1 VSS_77 VSS_158 AF13
MF-LF
2 402
N4 VSS_78 VSS_159 AF16
N23 VSS_79 VSS_160 AF19
N26 VSS_80 VSS_161 AF21
P3 VSS_81 VSS_162 AF24

CPU 2 OF 2-PWR/GND
A SYNC_MASTER=MASTER

NOTICE OF PROPRIETARY PROPERTY


SYNC_DATE=05/03/2005
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

APPLE COMPUTER INC.


D 051-6949 09

SCALE SHT OF
8 111
NONE

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

CPU HEATSINK MOUNTING HOLES


D D
OMIT OMIT OMIT OMIT
ZH607 ZH608 ZH609 ZH610
4P75R4 4P75R4 4P75R4 4P75R4
CPU_HS_ZH607 1 66 CPU_HS_ZH608 1 CPU_HS_ZH609 1 CPU_HS_ZH610 1

C950 1 C951 1 C952 1 C953 1


0.01UF 0.01UF 0.01UF 0.01UF
20% 20% 20% 20%
16V 16V 16V 16V
CERM 2 CERM 2 CERM 2 CERM 2
402 402 402 402

59 11 9 8 7 6 5 =PP1V05_S0_CPU

CRITICAL
1
C940
330UF
20%
2 6.3V
ELEC
CASE-C1

C C

VCCP CORE DECOUPLING


59 11 9 8 7 6 5 =PP1V05_S0_CPU

PLACE INSIDE SOCKET CAVITY 1 C926 1 C934 1 C935 1 C936 1 C937 1 C938
ON L8 (NORTH SIDE SECONDARY) 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% 20%
10V
2 CERM 2 10V 2 10V 2 10V 2 10V 2 10V
CERM CERM CERM CERM CERM
402 402 402 402 402 402

B B
76 8 6 =PPVCORE_S0_CPU
VCC CORE DECOUPLING

PLACE 8 INSIDE SOCKET 1 C923 1 C911 1 C910 1 C908 1 C901 1 C928 1 C900 1 C909 1 C907 1 C929
CAVITY ON L8 (NORTH SIDE 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
SECONDARY) 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
805 805 805 805 805 805 805 805 805 805

PLACE 8 INSIDE SOCKET 1 C924 1 C918 1 C913 1 C912 1 C904 1 C930 1 C902 1 C931 1 C939 1 C920
CAVITY ON L8 (SOUTH SIDE 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
SECONDARY) 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
805 805 805 805 805 805 805 805 805 805

NOSTUFF NOSTUFF NOSTUFF


PLACE 6 INSIDE SOCKET 1 C925 1 C919 1 C916 1 C914 1 C932 1 C905
CAVITY ON L1 (NORTH SIDE 22UF 22UF 22UF 22UF 22UF 22UF
20% 20% 20% 20% 20% 20%
PRIMARY) 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R
805 805 805 805 805 805

NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF


PLACE 6 INSIDE SOCKET 1 C922 1 C921 1 C917 1 C915 1 C906 1 C903 CPU DECAPS & VID<>
CAVITY ON L1 (SOUTH SIDE 22UF 22UF 22UF 22UF 22UF 22UF
20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
A PRIMARY) 2 X5R
805
2 X5R
805
2 X5R
805
2 X5R
805
2 X5R
805
2 X5R
805
NOTICE OF PROPRIETARY PROPERTY
A
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1
C941 1
C942 1
C943 1
C944 1
C945 1
C946 AGREES TO THE FOLLOWING
SOUTH SIDE SECONDARY 470UF 470UF 470UF 470UF 470UF 470UF I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
20% 20% 20% 20% 20% 20%
3 2 2.5V 3 2 2.5V 3 2 2.5V 3 2 2.5V 3 2 2.5V 3 2 2.5V II NOT TO REPRODUCE OR COPY IT
TANT TANT TANT TANT TANT TANT
D2T D2T D2T D2T D2T D2T III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

APPLE COMPUTER INC.


D 051-6949 09
SCALE SHT OF
NONE 9 111

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

NOTE:
IF CPU T DIODE TO BE READ IN OFF STATE,
CPU THERMAL SENSOR THEN THIS SHOULD BE S5

PP3V3_S0 6 26 41 59 61 76 88

D 1
C1001
0.1UF
D
10%
16V 1 1
2 X5R R1000 R1001
402 10K 10K
LAYOUT NOTE:
5% 5%
ADD GND GUARD TRACES FOR CPU_THERMD_P/N 1/16W 1/16W
MF-LF MF-LF
ROUTE ON SAME LAYER WITH 0.254MM TRACE WIDTH & SPACING. 402 402
2 2

1 NOSTUFF
VDD R1005
CPU_TSENS_INT ALERT*/ 6 0
CRITICAL THM2* THRM_ALERT_L 1 2 58 23 PM_THRM_L
R1002 IO

CPU_THERMD_P 1
499
2 THERM_DX_P 2 U1000 4 THRM_THM
5%
OUT 7 10 D+ THM* 1/16W
MF-LF
1% NOSTUFF 10 THERM_DX_N 3
D- ADT7461 402
8 =SMB_THRM_CLK
1/16W SCLK 59
IO
MF-LF 1
C1000 MSOP
7 =SMB_THRM_DATA
402
0.001UF SDATA 59
IO
CPU_TSENS_INT 20%
50V
R1017 2 CERM GND
402
499 5
IN 7 CPU_THERMD_N 1 2

1%
1/16W
MF-LF
402

NOTE: SYMBOL SHOULD BE SHOWN ADT7461A

C C

LAYOUT NOTE:
PLACE R1002 AND R1018 SUCH THAT THEY SHARE ONE PAD
PLACE R1017 AND R1019 SUCH THAT THEY SHARE ONE PAD

CPU_TSENS_EXT
CRITICAL
J1000 R1018
0
SM-2MT-BLK-LF 1 2
3 5%
1/16W
MF-LF
402
1 CPU_THERMD_EXT_P THERM_DX_P 10
2 CPU_THERMD_EXT_N THERM_DX_N 10
CPU_TSENS_EXT
4
R1019
0
1 2
TEMPORARILY REMOVED BOMOPTION=CPU_TSENS_EXT 5%
1/16W
MF-LF
402

B B

CPU TEMP SENSOR


A NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

APPLE COMPUTER INC.


D 051-6949 09

SCALE SHT OF
10 111
NONE

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

CPU ITP700FLEX DEBUG SUPPORT

C C

ITP
59 11 9 8 7 6 5 =PP1V05_S0_CPU
ITP J1101
1 52435-2872
R1101 1R1103 F-RT-SM
29
54.9 54.9
1% 1%
1/16W 1/16W
MF-LF MF-LF
2 402 2 402
59 7
OUT
5 XDP_TDI 1

OUT
XDP_TMS 2

OUT XDP_TRST_L 3

NC 4
ITP (TCK)
59 11 7
5
OUT
XDP_TCK 5
R1102 NC 6
XDP_TDO 22.6 2
59 7 5
IN
1 ITP_TDO 7
1%
1/16W
34
IN
CPU_XDP_CLK_N 8
(FROM CK410M HOST 133/167MHZ)
MF-LF
402
34
IN
CPU_XDP_CLK_P 9
ITP 10
R1100 59 11 7
5
OUT XDP_TCK (FBO) 11
12 7 5 FSB_CPURST_L 1
22.6 2 ITPRESET_L 12
IN
1%
1/16W IO 7 XDP_BPM_L<5> 13
MF-LF 14
402
IO
7 XDP_BPM_L<4> 15
16
B 23 6 =PP3V3_S5_SB_PM
ITP
IO 7 XDP_BPM_L<3> 17
18
B
1
R1104 IO
7 XDP_BPM_L<2> 19
240 20
5%
1/16W
MF-LF IO 7 XDP_BPM_L<1> 21
2 402 22

IO
7 XDP_BPM_L<0> 23
24 (DBA#) INDICATE THAT ITP IS USING TAP I/F, NC IN 945GM CHIPSET SYSTEM.
NC (DEBUG PORT ACTIVE)
(AND WITH RESET BUTTON) OUT 26 7 XDP_DBRESET_L 25 (DBR#) TO ICH7M SYS_RST*, AND WITH SYSTEM RESET LOGIC
(DEBUG PORT RESET)
59 11 9 8 7 6 5 =PP1V05_S0_CPU 26

ITP 27
1 C1100 28
0.1UF
10%
2 16V
X5R
30
402
518S0320
1
R1106
680
ITP TCK SIGNAL LAYOUT NOTE: 5%
1/16W
ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTORS TCK PIN TO CPUS MF-LF
TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEX 2 402

CONNECTORS FBO PIN.

CPU ITP700FLEX DEBUG


SYNC_MASTER=MASTER SYNC_DATE=5/23/05
A NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

APPLE COMPUTER INC.


D 051-6949 09

SCALE SHT OF
NONE 11 111

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

7 5
IO
FSB_D_L<0> F1 HD0* HA3* H9 7 FSB_A_L<3> IO

D
7

7
IO

IO
FSB_D_L<1>
FSB_D_L<2>
J1

H1
HD1*
HD2*
HA4*
HA5*
C9

E11
7

7
FSB_A_L<4>
FSB_A_L<5>
IO

IO
D
7
IO
FSB_D_L<3> J6 HD3* OMIT HA6* G11 7 5 FSB_A_L<6> IO
7
IO
FSB_D_L<4> H3 HD4* HA7* F11 7 FSB_A_L<7> IO
7 FSB_D_L<5> K2
U1200 G12 7 FSB_A_L<8>
IO HD5* HA8* IO
7
IO
FSB_D_L<6> G1 HD6* 945GM HA9* F9 7 FSB_A_L<9> IO
7 FSB_D_L<7> G2 HD7* HA10* H11 7 FSB_A_L<10>
IO NB IO
7
IO
FSB_D_L<8> K9 HD8* HA11* J12 7 FSB_A_L<11> IO
BGA
7 IO FSB_D_L<9> K1 HD9* HA12* G14 7 FSB_A_L<12> IO
(1 OF 10)
7
IO
FSB_D_L<10> K7 HD10* HA13* D9 7 FSB_A_L<13> IO
7
IO FSB_D_L<11> J8 HD11* HA14* J14 7 FSB_A_L<14> IO
7
IO FSB_D_L<12> H4 HD12* HA15* H13 7 FSB_A_L<15> IO
7
IO FSB_D_L<13> J3 HD13* HA16* J15 7 FSB_A_L<16> IO
7
IO
FSB_D_L<14> K11 HD14* HA17* F14 7 FSB_A_L<17> IO
7
IO FSB_D_L<15> G4 HD15* HA18* D12 7 FSB_A_L<18> IO
7 5
IO FSB_D_L<16> T10 HD16* HA19* A11 7 FSB_A_L<19> IO
7
IO
FSB_D_L<17> W11 HD17* HA20* C11 7 FSB_A_L<20> IO
7
IO FSB_D_L<18> T3 HD18* HA21* A12 7 FSB_A_L<21> IO
7
IO FSB_D_L<19> U7 HD19* HA22* A13 7 FSB_A_L<22> IO
7 IO FSB_D_L<20> U9 HD20* HA23* E13 7 FSB_A_L<23> IO
7
IO FSB_D_L<21> U11 HD21* HA24* G13 7 FSB_A_L<24> IO
7
IO FSB_D_L<22> T11 HD22* HA25* F12 7 FSB_A_L<25> IO
7
IO FSB_D_L<23> W9 HD23* HA26* B12 7 FSB_A_L<26> IO
7
IO FSB_D_L<24> T1 HD24* HA27* B14 7 5 FSB_A_L<27> IO
7
IO FSB_D_L<25> T8 HD25* HA28* C12 7 FSB_A_L<28> IO
7
IO FSB_D_L<26> T4 HD26* HA29* A14 7 FSB_A_L<29> IO
7
IO FSB_D_L<27> W7 HD27* HA30* C14 7 FSB_A_L<30> IO
=PP1V05_S0_FSB_NB 5 6 12 19

C 7

7
IO FSB_D_L<28>
FSB_D_L<29>
U5 HD28* HA31* D14 7 FSB_A_L<31> IO
1
C
IO T9 HD29* R1210
7
IO FSB_D_L<30> W6 HD30* 100
HADS* E8 7 FSB_ADS_L IO 1%
7 IO FSB_D_L<31> T5 HD31* 1/16W
HADSTB0* B9 7 5 FSB_ADSTB_L<0> IO MF-LF
7 FSB_D_L<32> AB7 HD32*

HOST
IO 402
C13 FSB_ADSTB_L<1> 2
7 FSB_D_L<33> AA9
HADSTB1* 7 5 IO
IO HD33* J13 5 NB_FSB_VREF
7 FSB_D_L<34> HAVREF
IO W4 HD34* 7
HBNR* C6 5 FSB_BNR_L IO
7
IO FSB_D_L<35> W3 HD35*
HBPRI* F6 7 FSB_BPRI_L OUT
1
R1211
7
IO FSB_D_L<36> Y3 HD36*
C7
7
5 FSB_BREQ0_L
C1211 1
200
7 FSB_D_L<37> HBREQ0* IO 0.1uF
IO Y7 HD37* 1%
B7 11 7 5 FSB_CPURST_L 10%
7 FSB_D_L<38> W5
HCPURST* OUT 16V 1/16W
IO HD38* A7
7
5 FSB_DBSY_L X5R 2 MF-LF

7 FSB_D_L<39> Y10
HDBSY* IO 402 2
402
IO HD39* C3 7 FSB_DEFER_L
7 FSB_D_L<40> AB8
HDEFER* OUT
IO HD40* J9
7
FSB_DPWR_L
7 5 FSB_D_L<41> W2
HDPWR* 5
IO
IO HD41* H8 7 FSB_DRDY_L
FSB_D_L<42> HDRDY* IO
7 IO AA4 HD42*
HDVREF K13
7
IO FSB_D_L<43> AA7 HD43*
7
IO FSB_D_L<44> AA2 HD44*
HDINV0* J7 7 5 FSB_DINV_L<0> IO
7
IO FSB_D_L<45> AA6 HD45*
HDINV1* W8 7 5 FSB_DINV_L<1> IO
7
IO
FSB_D_L<46> AA10 HD46*
HDINV2* U3 7 5 FSB_DINV_L<2> IO
7
IO FSB_D_L<47> Y8 HD47*
HDINV3* AB10 7 5 FSB_DINV_L<3> IO
7
IO FSB_D_L<48> AA1 HD48*
19 12 6 5 =PP1V05_S0_FSB_NB 7
IO FSB_D_L<49> AB4 HD49* HDSTBN0* K4 7 5 FSB_DSTBN_L<0> IO
7
IO
FSB_D_L<50> AC9 HD50* HDSTBN1* T7 7 5 FSB_DSTBN_L<1> IO
7
IO
FSB_D_L<51> AB11 HD51* HDSTBN2* Y5 7 5 FSB_DSTBN_L<2> IO

R1220 1 1
R1225 7
IO FSB_D_L<52> AC11 HD52* HDSTBN3* AC4 7 5 FSB_DSTBN_L<3> IO
54.9 221 7 IO FSB_D_L<53> AB3 HD53*
1% 1% HDSTBP0* K3 7 5 FSB_DSTBP_L<0>
B 1/16W
MF-LF
402
1/16W
MF-LF
402
7

7
IO

IO
FSB_D_L<54>
FSB_D_L<55>
AC2
AD1
HD54*
HD55*
HDSTBP1* T6 7 5 FSB_DSTBP_L<1>
IO
IO B
2 2
HDSTBP2* AA5 7 5 FSB_DSTBP_L<2> IO
7
IO FSB_D_L<56> AD9 HD56*
HDTSBP3* AC5 7 5 FSB_DSTBP_L<3> IO
7
IO
FSB_D_L<57> AC1 HD57*
7
IO FSB_D_L<58> AD7 HD58*
HHIT* D3 7 5 FSB_HIT_L IO
7 5
IO FSB_D_L<59> AC6 HD59*
HHITM* D4 7 5 FSB_HITM_L IO
7
IO
FSB_D_L<60> AB5 HD60*
R1221
1 1
R1226 HLOCK* B3 7 5 FSB_LOCK_L IO
24.9 100
1
C1226 7
IO FSB_D_L<61> AD10 HD61*
0.1uF 7 FSB_D_L<62> AD4
1% 1%
10% IO HD62* D8 FSB_REQ_L<0>
1/16W 1/16W 16V 7 FSB_D_L<63> AC8
HREQ0* 7 5
IO
MF-LF MF-LF 2 X5R IO HD63* G8 7 5 FSB_REQ_L<1>
402
2 2
402 402 HREQ1* IO

HREQ2* B8 7 5 FSB_REQ_L<2> IO
NB_FSB_XRCOMP E1 HXRCOMP
HREQ3* F8 7 5 FSB_REQ_L<3> IO
NB_FSB_XSCOMP E2 HXSCOMP
HREQ4* A8 7 5 FSB_REQ_L<4> IO
NB_FSB_XSWING E4 HXSWING

HRS0* B4 7 FSB_RS_L<0> OUT


NB_FSB_YRCOMP Y1 HYRCOMP
HRS1* E6 7 FSB_RS_L<1> OUT
19 12 6 5 =PP1V05_S0_FSB_NB NB_FSB_YSCOMP U1 HYSCOMP
HRS2* D6 7 FSB_RS_L<2> OUT
NB_FSB_YSWING W1 HYSWING
34 5
IN
FSB_CLK_NB_P AG2 HCLKIN HSLPCPU* E3 7 FSB_SLPCPU_L OUT
1 1
R1230 R1235 34 5 FSB_CLK_NB_N AG1 HCLKIN* HTRDY* E7 7 FSB_TRDY_L
IN OUT
54.9 221
1% 1%
1/16W 1/16W
MF-LF MF-LF
402 402
2 2

NB CPU Interface
A SYNC_MASTER=(MASTER)

NOTICE OF PROPRIETARY PROPERTY


SYNC_DATE=(MASTER)
A
1 1
R1231 R1236 1
C1236
24.9 100 0.1uF THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1% 1%
10%
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1/16W 1/16W 16V AGREES TO THE FOLLOWING
MF-LF MF-LF 2 X5R
402
2 2
402 402 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

APPLE COMPUTER INC.


D 051-6949 09
SCALE SHT OF
NONE 12 111

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

=PP1V5_S0_NB_PCIE 6 19

1
R1310
OMIT 24.9
1%
1/16W
U1200 MF-LF
402
2
LVDS Disable 945GM
19 LVDS_BKLTCTL D32 L_BKLTCTL EXP_A_COMPI D40 PEG_COMP

D Can leave all signals NC if LVDS is not implemented 19


OUT

OUT LVDS_BKLTEN J30 L_BKLTEN


NB
BGA EXP_A_COMPO D38 SDVO Alternate Function D
Tie VCC_TXLVDS and VCCA_LVDS to GND. If SDVO is used 19
OUT
LVDS_CLKCTLA H30 L_CLKCTLA (3 OF 10)
EXP_A_RXN0 F34 84 PEG_D2R_N<0> IN SDVO_TVCLKIN#
VCCD_LVDS must remain powered with proper decoupling. 19
OUT
LVDS_CLKCTLB H29 L_CLKCTLB
EXP_A_RXN1 G38 84 PEG_D2R_N<1> IN SDVO_INT#
Otherwise, tie VCCD_LVDS to GND also. 19
IO LVDS_DDC_CLK G26 L_DDC_CLK
EXP_A_RXN2 H34 84 PEG_D2R_N<2> IN SDVO_FLDSTALL#
19
IO
LVDS_DDC_DATA G25 L_DDC_DATA
EXP_A_RXN3 J38 84 PEG_D2R_N<3> IN
19
IO
LVDS_IBG B38 L_IBG
EXP_A_RXN4 L34 84 PEG_D2R_N<4> IN
TP_LVDS_VBG C35 L_VBG
EXP_A_RXN5 M38 84 PEG_D2R_N<5> IN
19
OUT
LVDS_VDDEN F32 L_VDDEN
EXP_A_RXN6 N34 84 PEG_D2R_N<6> IN
19
IN
LVDS_VREFH C33 L_VREFH
EXP_A_RXN7 P38 84 PEG_D2R_N<7> IN
19 IN LVDS_VREFL C32 L_VREFL
EXP_A_RXN8 R34 84 PEG_D2R_N<8> IN
19
OUT
LVDS_A_CLK_N A33 LA_CLK* EXP_A_RXN9 T38 84 PEG_D2R_N<9> IN
19
OUT
LVDS_A_CLK_P A32 LA_CLK EXP_A_RXN10 V34 84 PEG_D2R_N<10> IN
19
OUT LVDS_B_CLK_N E27 LB_CLK* EXP_A_RXN11 W38 84 PEG_D2R_N<11> IN

LVDS
19
OUT
LVDS_B_CLK_P E26 LB_CLK EXP_A_RXN12 Y34 84 PEG_D2R_N<12> IN
EXP_A_RXN13 AA38 84 PEG_D2R_N<13> IN
19
OUT
LVDS_A_DATA_N<0> C37 LA_DATA0*
EXP_A_RXN14 AB34 84 PEG_D2R_N<14> IN
19
OUT LVDS_A_DATA_N<1> B35 LA_DATA1*
EXP_A_RXN15 AC38 84 PEG_D2R_N<15> IN
19
OUT LVDS_A_DATA_N<2> A37 LA_DATA2*
EXP_A_RXP0 D34 84 PEG_D2R_P<0> IN SDVO_TVCLKIN
19
OUT LVDS_A_DATA_P<0> B37 LA_DATA0
EXP_A_RXP1 F38 84 PEG_D2R_P<1> IN SDVO_INT
19
OUT
LVDS_A_DATA_P<1> B34 LA_DATA1
EXP_A_RXP2 G34 84 PEG_D2R_P<2> IN SDVO_FLDSTALL
19
OUT
LVDS_A_DATA_P<2> A36 LA_DATA2
EXP_A_RXP3 H38 84 PEG_D2R_P<3> IN
19
OUT
LVDS_B_DATA_N<0> G30 LB_DATA0* EXP_A_RXP4 J34 84 PEG_D2R_P<4> IN
LVDS_B_DATA_N<1> PEG_D2R_P<5>

PCI-EXPRESS GRAPHICS
19
OUT D30 LB_DATA1* EXP_A_RXP5 L38 84
IN
19
OUT
LVDS_B_DATA_N<2> F29 LB_DATA2* EXP_A_RXP6 M34 84 PEG_D2R_P<6> IN
EXP_A_RXP7 N38 84 PEG_D2R_P<7> IN
19
OUT
LVDS_B_DATA_P<0> F30 LB_DATA0
C 19

19
OUT
LVDS_B_DATA_P<1>
LVDS_B_DATA_P<2>
D29

F28
LB_DATA1
LB_DATA2
EXP_A_RXP8
EXP_A_RXP9
P34

R38
84

84
PEG_D2R_P<8>
PEG_D2R_P<9>
IN

IN
C
OUT
EXP_A_RXP10 T34 84 PEG_D2R_P<10> IN
EXP_A_RXP11 V38 84 PEG_D2R_P<11> IN
TV-Out Signal Usage:
19
OUT
TV_DACA_OUT A16 TV_DACA_OUT EXP_A_RXP12 W34 84 PEG_D2R_P<12> IN
Composite: DACA only 19
OUT
TV_DACB_OUT C18 TV_DACB_OUT EXP_A_RXP13 Y38 84 PEG_D2R_P<13> IN
S-Video: DACB & DACC only 19
OUT
TV_DACC_OUT A19 TV_DACC_OUT EXP_A_RXP14 AA34 84 PEG_D2R_P<14> IN

TV
Component: DACA, DACB & DACC EXP_A_RXP15 AB38 84 PEG_D2R_P<15> IN
19
OUT
TV_IREF J20 TV_IREF
Unused DAC outputs must remain powered, but can omit 19
OUT
TV_IRTNA B16 TV_IRTNA EXP_A_TXN0 F36 84 PEG_R2D_C_N<0> OUT SDVOB_RED#
filtering components. Unused DAC outputs should 19
OUT
TV_IRTNB B18 TV_IRTNB EXP_A_TXN1 G40 84 PEG_R2D_C_N<1> OUT SDVOB_GREEN#
connect to GND through 75-ohm resistors. 19
OUT TV_IRTNC B19 TV_IRTNC EXP_A_TXN2 H36 84 PEG_R2D_C_N<2> OUT SDVOB_BLUE#
EXP_A_TXN3 J40 84 PEG_R2D_C_N<3> OUT SDVOB_CLKN
TV-Out Disable
EXP_A_TXN4 L36 84 PEG_R2D_C_N<4> OUT SDVOC_RED#
19
OUT CRT_BLUE E23 CRT_BLUE
Tie DACx_OUT, IRTNx, and IREF to 1.5V power rail. EXP_A_TXN5 M40 84 PEG_R2D_C_N<5> OUT SDVOC_GREEN#
19
OUT
CRT_BLUE_L D23 CRT_BLUE*
Tie VCCD_TVDAC, VCCD_QTVDAC, VCCA_TVDACx, and EXP_A_TXN6 N36 84 PEG_R2D_C_N<6> OUT SDVOC_BLUE#
19
OUT
CRT_GREEN C22 CRT_GREEN
VCCA_TVBG to 1.5V power rail. Tie VSSA_TVBG to GND. EXP_A_TXN7 P40 84 PEG_R2D_C_N<7> OUT SDVOC_CLKN
19
OUT
CRT_GREEN_L B22 CRT_GREEN*
EXP_A_TXN8 PEG_R2D_C_N<8>

VGA
R36 84
OUT
19
OUT
CRT_RED A21 CRT_RED
CRT Disable EXP_A_TXN9 T40 84 PEG_R2D_C_N<9> OUT
19
OUT
CRT_RED_L B21 CRT_RED*
EXP_A_TXN10 V36 84 PEG_R2D_C_N<10> OUT
Tie R/R#/G/G#/B/B# and IREF to VCC Core rail, tie
19
IO
CRT_DDC_CLK C26 CRT_DDC_CLK EXP_A_TXN11 W40 84 PEG_R2D_C_N<11> OUT
HSYNC and VSYNC to GND. Tie VCCA_CRTDAC to VCC Core
19
IO
CRT_DDC_DATA C25 CRT_DDC_DATA EXP_A_TXN12 Y36 84 PEG_R2D_C_N<12> OUT
rail, and tie VSSA_CRTDAC and VCC_SYNC to GND.
19
OUT
CRT_HSYNC_R G23 HSYNC EXP_A_TXN13 AA40 84 PEG_R2D_C_N<13> OUT
19
OUT CRT_IREF J22 CRT_IREF EXP_A_TXN14 AB36 84 PEG_R2D_C_N<14> OUT
19
OUT
CRT_VSYNC_R H23 CRT_VSYNC EXP_A_TXN15 AC40 84 PEG_R2D_C_N<15> OUT

EXP_A_TXP0 D36 84 PEG_R2D_C_P<0> OUT SDVOB_RED


EXP_A_TXP1 F40 84 PEG_R2D_C_P<1> SDVOB_GREEN
B EXP_A_TXP2 G36 84 PEG_R2D_C_P<2>
OUT

OUT SDVOB_BLUE B
EXP_A_TXP3 H40 84 PEG_R2D_C_P<3> OUT SDVOB_CLKP
EXP_A_TXP4 J36 84 PEG_R2D_C_P<4> OUT SDVOC_RED
EXP_A_TXP5 L40 84 PEG_R2D_C_P<5> OUT SDVOC_GREEN
EXP_A_TXP6 M36 84 PEG_R2D_C_P<6> OUT SDVOC_BLUE
EXP_A_TXP7 N40 84 PEG_R2D_C_P<7> OUT SDVOC_CLKP
EXP_A_TXP8 P36 84 PEG_R2D_C_P<8> OUT
EXP_A_TXP9 R40 84 PEG_R2D_C_P<9> OUT
EXP_A_TXP10 T36 84 PEG_R2D_C_P<10> OUT
EXP_A_TXP11 V40 84 PEG_R2D_C_P<11> OUT
EXP_A_TXP12 W36 84 PEG_R2D_C_P<12> OUT
EXP_A_TXP13 Y40 84 PEG_R2D_C_P<13> OUT
EXP_A_TXP14 AA36 84 PEG_R2D_C_P<14> OUT
EXP_A_TXP15 AB40 84 PEG_R2D_C_P<15> OUT

NB PEG / Video Interfaces


A SYNC_MASTER=(MASTER)

NOTICE OF PROPRIETARY PROPERTY


SYNC_DATE=(MASTER)
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

APPLE COMPUTER INC.


D 051-6949 09
SCALE SHT OF
NONE 13 111

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

20 19 14 6 =PP3V3_S0_NB

R1440 1 1
R1441
10K 10K
5% 5% OMIT
1/16W 1/16W

D MF-LF
402
2 2
MF-LF
402 U1200 D
945GM
(D_PLLMON1#) NC T32 RSVD1 SM_CK0 AY35 28 MEM_CLK_P<0>
NB OUT
(D_PLLMON1) NC R32 RSVD2 BGA SM_CK1 AR1 28 MEM_CLK_P<1> OUT
(H_EDRDY#) NC F3 RSVD3 (2 OF 10) SM_CK2 AW7 29 MEM_CLK_P<2> OUT
(H_PCREQ#) NC F7 RSVD4 SM_CK3 AW40 29 MEM_CLK_P<3> OUT
(H_PLLMON1#) NC AG11 RSVD5
SM_CK0* AW35 28 MEM_CLK_N<0> OUT
(H_PLLMON1) NC AF11 RSVD6
SM_CK1* AT1 28 MEM_CLK_N<1> OUT
(H_PROCHOT#) TP_NB_XOR_FSB2_H7 H7 RSVD7

RSVD
SM_CK2* AY7 29 MEM_CLK_N<2> OUT
(TESTIN#) TP_NB_TESTIN_L J19 RSVD8
SM_CK3* AY40 29 MEM_CLK_N<3> OUT
(TV_DCONSEL0) NB_TV_DCONSEL0 K30 RSVD9
(TV_DCONSEL1) NB_TV_DCONSEL1 J29 RSVD10 SM_CKE0 AU20 30 28 MEM_CKE<0> OUT
(VSS_MCHDETECT) NC A41 RSVD11 SM_CKE1 AT20 30 28 MEM_CKE<1> OUT

DDR MUXING
(LA_DATAN3) TP_NB_XOR_LVDS_A35 A35 RSVD12 SM_CKE2 BA29 30 29 MEM_CKE<2> OUT
(LA_DATAP3) TP_NB_XOR_LVDS_A34 A34 RSVD13 SM_CKE3 AY29 30 29 MEM_CKE<3> OUT
(LB_DATAN3) TP_NB_XOR_LVDS_D28 D28 RSVD14
SM_CS0* AW13 30 28 MEM_CS_L<0> OUT
(LB_DATAP3) TP_NB_XOR_LVDS_D27 D27 RSVD15
SM_CS1* AW12 30 28 MEM_CS_L<1> OUT
34
IN NB_BSEL<0> K16 CFG0 SM_CS2* AY21 30 29 MEM_CS_L<2> OUT
34
IN NB_BSEL<1> K18 CFG1 SM_CS3* AW21 30 29 MEM_CS_L<3> OUT
34
IN
NB_BSEL<2> J18 CFG2
SMOCDCOMP0 AL20 NC
IN
NB_CFG<3> F18 CFG3 IPU =PP1V8_S3_MEM_NB 6 16 19
SMOCDCOMP1 AF10 NC
IN
NB_CFG<4> E15 CFG4 IPU
NB_CFG<5> IPU MEM_ODT<0> 1
20
IN F15 CFG5 SM_ODT0 BA13 30 28
OUT R1410
IN
NB_CFG<6> E18 CFG6 IPU SM_ODT1 BA12 30 28 MEM_ODT<1> OUT 80.6
1%
20
IN
NB_CFG<7> D19 CFG7 IPU SM_ODT2 AY20 30 29 MEM_ODT<2> OUT 1/16W

CFG
MF-LF
IN
NB_CFG<8> D16 CFG8 IPU SM_ODT3 AU21 30 29 MEM_ODT<3> OUT 402

C 20
IN
NB_CFG<9>
NB_CFG<10>
G16

E16
CFG9
CFG10
IPU
IPU
SMRCOMP* AV9 MEM_RCOMP_L
2
C
IN
SMRCOMP AT9 MEM_RCOMP
IN NB_CFG<11> D15 CFG11 IPU
IN NB_CFG<12> G15 CFG12 IPU SMVREF0 AK1 19 5 MEM_VREF_NB_0 IN 1
IN NB_CFG<13> K15 CFG13 IPU SMVREF1 AK41 19 5 MEM_VREF_NB_1 IN
R1411
80.6
IN NB_CFG<14> C15 CFG14 IPU 1%
G_CLKIN* AF33 34 5 NB_CLK100M_GCLKIN_N IN 1/16W
20 19 14 6 =PP3V3_S0_NB IN NB_CFG<15> H16 CFG15 IPU MF-LF
G_CLKIN AG33 34 5 NB_CLK100M_GCLKIN_P IN 2 402
NB_CFG<16> CFG16 IPU

CLK
20 G18
IN NB_CLK_DREFCLKIN_N
D_REFCLKIN* A27 19
IN
IN NB_CFG<17> H15 CFG17 IPU
D_REFCLKIN A26 19 NB_CLK_DREFCLKIN_P IN
R1420 1 20
IN
NB_CFG<18> J25 CFG18 IPD
D_REFSSCLKIN* C40 19 NB_CLK_DREFSSCLKIN_N IN
10K 20
IN NB_CFG<19> K27 CFG19 IPD
5% D_REFSSCLKIN D41 19 NB_CLK_DREFSSCLKIN_P IN
1/16W 20
IN
NB_CFG<20> J26 CFG20 IPD
MF-LF
402 2 DMI_RXN0 AE35 22 5 DMI_S2N_N<0> IN
23
OUT PM_BMBUSY_L G28 PM_BM_BUSY*
DMI_RXN1 AF39 22 DMI_S2N_N<1> IN
59 58
IN
PM_EXTTS_L<0> F25 PM_EXTTS0*
DMI_RXN2 AG35 22 DMI_S2N_N<2> IN

PM
75 23
IN
PM_DPRSLPVR H26 PM_EXTTS1*
DMI_RXN3 AH39 22 DMI_S2N_N<3> IN
OUT
PM_THRMTRIP_L G6 PW_THRMTRIP*
R1430 75 26 5
IN
VR_PWRGOOD_DELAY AH33 PWROK DMI_RXP0 AC35 22 5 DMI_S2N_P<0> IN
100
6
IN
NB_RST_IN_L 1 2 5 NB_RST_IN_L_R AH34 RSTIN* DMI_RXP1 AE39 22 DMI_S2N_P<1> IN
5% DMI_RXP2 AF35 22 DMI_S2N_P<2> IN
1/16W 19 SDVO_CTRLCLK H28 SDVO_CTRLCLK

MISC
IO
DMI_RXP3 DMI_S2N_P<3>

DMI
MF-LF AG39 22
IN
402 19
IO
SDVO_CTRLDATA H27 SDVO_CTRLDATA
22
OUT
NB_SB_SYNC_L K28 ICH_SYNC* DMI_TXN0 AE37 22 5 DMI_N2S_N<0> OUT
33
OUT
CLK_NB_OE_L H32 CLK_REQ* DMI_TXN1 AF41 22 DMI_N2S_N<1> OUT
DMI_TXN2 AG37 22 DMI_N2S_N<2> OUT
NC D1 NC0
DMI_TXN3 AH41 22 DMI_N2S_N<3> OUT
NC C41 NC1
NC C1 NC2 DMI_TXP0 AC37 22 5 DMI_N2S_P<0>
B NC BA41 NC3 DMI_TXP1 AE41 22 DMI_N2S_P<1>
OUT

OUT
B
NC BA40 NC4 DMI_TXP2 AF37 22 DMI_N2S_P<2> OUT
NC BA39 NC5 DMI_TXP3 AG41 22 DMI_N2S_P<3> OUT
NC BA3 NC6
NC BA2 NC7
NC BA1 NC8
NC

NC
B41 NC9
NC B2 NC10
NC AY41 NC11
NC AY1 NC12
NC AW41 NC13
NC AW1 NC14
NC A40 NC15
NC A4 NC16
NC A39 NC17
NC A3 NC18

NB Misc Interfaces
A SYNC_MASTER=(MASTER)

NOTICE OF PROPRIETARY PROPERTY


SYNC_DATE=(MASTER)
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

APPLE COMPUTER INC.


D 051-6949 09
SCALE SHT OF
NONE 14 111

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D OMIT OMIT
D
U1200 U1200
28
IO MEM_A_DQ<0> AJ35 SA_DQ0 945GM SA_BS0 AU12 30 28 MEM_A_BS<0> OUT
29
IO MEM_B_DQ<0> AK39 SB_DQ0 945GM SB_BS0 AT24 30 29 MEM_B_BS<0> OUT
28
IO
MEM_A_DQ<1> AJ34 SA_DQ1 NB SA_BS1 AV14 30 28 MEM_A_BS<1> OUT
29
IO
MEM_B_DQ<1> AJ37 SB_DQ1 NB SB_BS1 AV23 30 29 MEM_B_BS<1> OUT
28
IO MEM_A_DQ<2> AM31 SA_DQ2 BGA SA_BS2 BA20 30 28 MEM_A_BS<2> 29
IO MEM_B_DQ<2> AP39 SB_DQ2 BGA SB_BS2 AY28 30 29 MEM_B_BS<2>
OUT OUT
28 MEM_A_DQ<3> AM33 SA_DQ3
(4 OF 10) 29 MEM_B_DQ<3> AR41 SB_DQ3
(5 OF 10)
IO MEM_A_CAS_L IO MEM_B_CAS_L
SA_CAS* AY13 30 28
OUT SB_CAS* AR24 30 29
OUT
28 IO MEM_A_DQ<4> AJ36 SA_DQ4 29
IO MEM_B_DQ<4> AJ38 SB_DQ4
SA_DM0 AJ33 28 MEM_A_DM<0> OUT SB_DM0 AK36 29 MEM_B_DM<0> OUT
28
IO MEM_A_DQ<5> AK35 SA_DQ5 29
IO MEM_B_DQ<5> AK38 SB_DQ5
SA_DM1 AM35 28 MEM_A_DM<1> OUT SB_DM1 AR38 29 MEM_B_DM<1> OUT
28
IO MEM_A_DQ<6> AJ32 SA_DQ6 29 5
IO MEM_B_DQ<6> AN41 SB_DQ6
SA_DM2 AL26 28 MEM_A_DM<2> OUT SB_DM2 AT36 29 MEM_B_DM<2> OUT
28 5
IO MEM_A_DQ<7> AH31 SA_DQ7 29
IO MEM_B_DQ<7> AP41 SB_DQ7
SA_DM3 AN22 28 MEM_A_DM<3> OUT SB_DM3 BA31 29 MEM_B_DM<3> OUT
28
IO
MEM_A_DQ<8> AN35 SA_DQ8 29 5
IO
MEM_B_DQ<8> AT40 SB_DQ8
SA_DM4 AM14 28 MEM_A_DM<4> OUT SB_DM4 AL17 29 MEM_B_DM<4> OUT
28
IO
MEM_A_DQ<9> AP33 SA_DQ9 29
IO
MEM_B_DQ<9> AV41 SB_DQ9
SA_DM5 AL9 28 MEM_A_DM<5> OUT SB_DM5 AH8 29 MEM_B_DM<5> OUT
28
IO
MEM_A_DQ<10> AR31 SA_DQ10 29
IO
MEM_B_DQ<10> AU38 SB_DQ10
SA_DM6 AR3 28 MEM_A_DM<6> OUT SB_DM6 BA5 29 MEM_B_DM<6> OUT
28
IO
MEM_A_DQ<11> AP31 SA_DQ11 29
IO
MEM_B_DQ<11> AV38 SB_DQ11
SA_DM7 AH4 28 MEM_A_DM<7> OUT SB_DM7 AN4 29 MEM_B_DM<7> OUT
28
IO
MEM_A_DQ<12> AN38 SA_DQ12 29
IO
MEM_B_DQ<12> AP38 SB_DQ12
28
IO
MEM_A_DQ<13> AM36 SA_DQ13 29
IO
MEM_B_DQ<13> AR40 SB_DQ13
SA_DQS0 AK33 28 5 MEM_A_DQS_P<0> IO SB_DQS0 AM39 29 5 MEM_B_DQS_P<0> IO
28 5
IO
MEM_A_DQ<14> AM34 SA_DQ14 29
IO
MEM_B_DQ<14> AW38 SB_DQ14
SA_DQS1 AT33 28 5 MEM_A_DQS_P<1> IO SB_DQS1 AT39 29 5 MEM_B_DQS_P<1> IO
28 IO MEM_A_DQ<15> AN33 SA_DQ15 29
IO MEM_B_DQ<15> AY38 SB_DQ15
SA_DQS2 AN28 28 5 MEM_A_DQS_P<2> IO SB_DQS2 AU35 29 5 MEM_B_DQS_P<2> IO
28 5
IO
MEM_A_DQ<16> AK26 SA_DQ16 29
IO
MEM_B_DQ<16> BA38 SB_DQ16
SA_DQS3 AM22 28 5 MEM_A_DQS_P<3> IO SB_DQS3 AR29 29 5 MEM_B_DQS_P<3> IO
28
IO
MEM_A_DQ<17> AL27 SA_DQ17 29
IO
MEM_B_DQ<17> AV36 SB_DQ17
SA_DQS4 AN12 28 5 MEM_A_DQS_P<4> IO SB_DQS4 AR16 29 5 MEM_B_DQS_P<4> IO
MEM_A_DQ<18> MEM_B_DQ<18>

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY B


28
IO AM26 SA_DQ18 29
IO AR36 SB_DQ18
SA_DQS5 AN8 28 5 MEM_A_DQS_P<5> IO SB_DQS5 AR10 29 5 MEM_B_DQS_P<5> IO
28
IO
MEM_A_DQ<19> AN24 SA_DQ19 29
IO
MEM_B_DQ<19> AP36 SB_DQ19
SA_DQS6 AP3 28 5 MEM_A_DQS_P<6> IO SB_DQS6 AR7 29 5 MEM_B_DQS_P<6> IO
28
IO
MEM_A_DQ<20> AK28 SA_DQ20 29
IO
MEM_B_DQ<20> BA36 SB_DQ20
SA_DQS7 AG5 28 5 MEM_A_DQS_P<7> IO SB_DQS7 AN5 29 5 MEM_B_DQS_P<7> IO
28
IO
MEM_A_DQ<21> AL28 SA_DQ21 29
IO
MEM_B_DQ<21> AU36 SB_DQ21
SA_DQS0* AK32 28 5 MEM_A_DQS_N<0> IO SB_DQS0* AM40 29 5 MEM_B_DQS_N<0> IO
28
IO
MEM_A_DQ<22> AM24 SA_DQ22 29
IO
MEM_B_DQ<22> AP35 SB_DQ22
C 28

28
IO MEM_A_DQ<23>
MEM_A_DQ<24>
AP26

AP23
SA_DQ23
SA_DQ24
SA_DQS1*
SA_DQS2*
AU33

AN27
28 5

28 5
MEM_A_DQS_N<1>
MEM_A_DQS_N<2>
IO

IO
29 5

29
IO MEM_B_DQ<23>
MEM_B_DQ<24>
AP34

AY33
SB_DQ23
SB_DQ24
SB_DQS1*
SB_DQS2*
AU39

AT35
29 5

29 5
MEM_B_DQS_N<1>
MEM_B_DQS_N<2>
IO

IO
C
IO IO
SA_DQS3* AM21 28 5 MEM_A_DQS_N<3> IO SB_DQS3* AP29 29 5 MEM_B_DQS_N<3> IO
28 5
IO
MEM_A_DQ<25> AL22 SA_DQ25 29 5
IO
MEM_B_DQ<25> BA33 SB_DQ25
SA_DQS4* AM12 28 5 MEM_A_DQS_N<4> IO SB_DQS4* AP16 29 5 MEM_B_DQS_N<4> IO
28 IO MEM_A_DQ<26> AP21 SA_DQ26 29 IO MEM_B_DQ<26> AT31 SB_DQ26
SA_DQS5* AL8 28 5 MEM_A_DQS_N<5> IO SB_DQS5* AT10 29 5 MEM_B_DQS_N<5> IO
28
IO
MEM_A_DQ<27> AN20 SA_DQ27 29
IO
MEM_B_DQ<27> AU29 SB_DQ27
SA_DQS6* AN3 28 5 MEM_A_DQS_N<6> IO SB_DQS6* AT7 29 5 MEM_B_DQS_N<6> IO
28
IO
MEM_A_DQ<28> AL23 SA_DQ28 29
IO
MEM_B_DQ<28> AU31 SB_DQ28
SA_DQS7* AH5 28 5 MEM_A_DQS_N<7> IO SB_DQS7* AP5 29 5 MEM_B_DQS_N<7> IO
28
IO
MEM_A_DQ<29> AP24 SA_DQ29 29
IO
MEM_B_DQ<29> AW31 SB_DQ29
28
IO
MEM_A_DQ<30> AP20 SA_DQ30 29
IO
MEM_B_DQ<30> AV29 SB_DQ30
SA_MA0 AY16 30 28 MEM_A_A<0> OUT SB_MA0 AY23 30 29 MEM_B_A<0> OUT
28
IO
MEM_A_DQ<31> AT21 SA_DQ31 29
IO
MEM_B_DQ<31> AW29 SB_DQ31
SA_MA1 AU14 30 28 MEM_A_A<1> OUT SB_MA1 AW24 30 29 MEM_B_A<1> OUT
28
IO
MEM_A_DQ<32> AR12 SA_DQ32 29
IO
MEM_B_DQ<32> AM19 SB_DQ32
SA_MA2 AW16 30 28 MEM_A_A<2> OUT SB_MA2 AY24 30 29 MEM_B_A<2> OUT
28
IO
MEM_A_DQ<33> AR14 SA_DQ33 29
IO
MEM_B_DQ<33> AL19 SB_DQ33
SA_MA3 BA16 30 28 MEM_A_A<3> OUT SB_MA3 AR28 30 29 MEM_B_A<3> OUT
28
IO
MEM_A_DQ<34> AP13 SA_DQ34 29
IO
MEM_B_DQ<34> AP14 SB_DQ34
SA_MA4 BA17 30 28 MEM_A_A<4> OUT SB_MA4 AT27 30 29 MEM_B_A<4> OUT
28
IO
MEM_A_DQ<35> AP12 SA_DQ35 29
IO
MEM_B_DQ<35> AN14 SB_DQ35
SA_MA5 AU16 30 28 MEM_A_A<5> OUT SB_MA5 AT28 30 29 MEM_B_A<5> OUT
28
IO
MEM_A_DQ<36> AT13 SA_DQ36 29
IO
MEM_B_DQ<36> AN17 SB_DQ36
SA_MA6 AV17 30 28 MEM_A_A<6> OUT SB_MA6 AU27 30 29 MEM_B_A<6> OUT
28 IO MEM_A_DQ<37> AT12 SA_DQ37 29
IO MEM_B_DQ<37> AM16 SB_DQ37
SA_MA7 AU17 30 28 MEM_A_A<7> OUT SB_MA7 AV28 30 29 MEM_B_A<7> OUT
28
IO
MEM_A_DQ<38> AL14 SA_DQ38 29 5
IO
MEM_B_DQ<38> AP15 SB_DQ38
SA_MA8 AW17 30 28 MEM_A_A<8> OUT SB_MA8 AV27 30 29 MEM_B_A<8> OUT
28 5
IO
MEM_A_DQ<39> AL12 SA_DQ39 29
IO
MEM_B_DQ<39> AL15 SB_DQ39
SA_MA9 AT16 30 28 MEM_A_A<9> OUT SB_MA9 AW27 30 29 MEM_B_A<9> OUT
28
IO
MEM_A_DQ<40> AK9 SA_DQ40 29
IO
MEM_B_DQ<40> AJ11 SB_DQ40
SA_MA10 AU13 30 28 MEM_A_A<10> OUT SB_MA10 AV24 30 29 MEM_B_A<10> OUT
28
IO
MEM_A_DQ<41> AN7 SA_DQ41 29
IO
MEM_B_DQ<41> AH10 SB_DQ41
SA_MA11 AT17 30 28 MEM_A_A<11> OUT SB_MA11 BA27 30 29 MEM_B_A<11> OUT
28
IO
MEM_A_DQ<42> AK8 SA_DQ42 29
IO
MEM_B_DQ<42> AJ9 SB_DQ42
SA_MA12 AV20 30 28 MEM_A_A<12> OUT SB_MA12 AY27 30 29 MEM_B_A<12> OUT
28
IO
MEM_A_DQ<43> AK7 SA_DQ43 29
IO
MEM_B_DQ<43> AN10 SB_DQ43
SA_MA13 AV12 30 28 MEM_A_A<13> OUT SB_MA13 AR23 30 29 MEM_B_A<13> OUT
28
IO
MEM_A_DQ<44> AP9 SA_DQ44 29 5
IO
MEM_B_DQ<44> AK13 SB_DQ44
28
IO
MEM_A_DQ<45> AN9 SA_DQ45 29
IO
MEM_B_DQ<45> AH11 SB_DQ45
SA_RAS* AW14 30 28 MEM_A_RAS_L OUT SB_RAS* AU23 30 29 MEM_B_RAS_L OUT
28
IO
MEM_A_DQ<46> AT5 SA_DQ46 29
IO
MEM_B_DQ<46> AK10 SB_DQ46
SA_RCVENIN* AK23 NC SB_RCVENIN* AK16 NC
28 5
IO
MEM_A_DQ<47> AL5 SA_DQ47 29
IO
MEM_B_DQ<47> AJ8 SB_DQ47
SA_RCVENOUT* AK24 NC SB_RCVENOUT* AK18 NC
28 IO MEM_A_DQ<48> AY2 SA_DQ48 29 5 IO MEM_B_DQ<48> BA10 SB_DQ48
SA_WE* AY14 30 28 MEM_A_WE_L SB_WE* AR27 30 29 MEM_B_WE_L
B 28

28
IO

IO
MEM_A_DQ<49>
MEM_A_DQ<50>
AW2

AP1
SA_DQ49
SA_DQ50
OUT
29

29
IO

IO
MEM_B_DQ<49>
MEM_B_DQ<50>
AW10

BA4
SB_DQ49
SB_DQ50
OUT
B
28
IO MEM_A_DQ<51> AN2 SA_DQ51 29
IO MEM_B_DQ<51> AW4 SB_DQ51
28
IO
MEM_A_DQ<52> AV2 SA_DQ52 29
IO
MEM_B_DQ<52> AY10 SB_DQ52
28
IO MEM_A_DQ<53> AT3 SA_DQ53 29
IO MEM_B_DQ<53> AY9 SB_DQ53
28 5
IO
MEM_A_DQ<54> AN1 SA_DQ54 29
IO
MEM_B_DQ<54> AW5 SB_DQ54
28
IO
MEM_A_DQ<55> AL2 SA_DQ55 29
IO
MEM_B_DQ<55> AY5 SB_DQ55
28
IO MEM_A_DQ<56> AG7 SA_DQ56 29
IO MEM_B_DQ<56> AV4 SB_DQ56
28
IO
MEM_A_DQ<57> AF9 SA_DQ57 29
IO
MEM_B_DQ<57> AR5 SB_DQ57
28
IO
MEM_A_DQ<58> AG4 SA_DQ58 29
IO
MEM_B_DQ<58> AK4 SB_DQ58
28 5 IO MEM_A_DQ<59> AF6 SA_DQ59 29
IO MEM_B_DQ<59> AK3 SB_DQ59
28
IO
MEM_A_DQ<60> AG9 SA_DQ60 29
IO
MEM_B_DQ<60> AT4 SB_DQ60
28
IO MEM_A_DQ<61> AH6 SA_DQ61 29
IO MEM_B_DQ<61> AK5 SB_DQ61
28
IO
MEM_A_DQ<62> AF4 SA_DQ62 29 5
IO
MEM_B_DQ<62> AJ5 SB_DQ62
28
IO MEM_A_DQ<63> AF8 SA_DQ63 29
IO MEM_B_DQ<63> AJ3 SB_DQ63

NB DDR2 Interfaces
A SYNC_MASTER=(MASTER)

NOTICE OF PROPRIETARY PROPERTY


SYNC_DATE=(MASTER)
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

APPLE COMPUTER INC.


D 051-6949 09
SCALE SHT OF
NONE 15 111

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NCTF balls are Not Critical To Function
These connections can break without
impacting part performance.
OMIT
19 16 6 =PPVCORE_S0_NB
AD27 VCC_NCTF0 VSS_NCTF0 AE27
AC27 VCC_NCTF1
U1200 VSS_NCTF1 AE26

AB27 945GM AE25


VCC_NCTF2 VSS_NCTF2
AA27 VCC_NCTF3
NB VSS_NCTF3 AE24
Y27 BGA AE23
VCC_NCTF4 VSS_NCTF4
W27
(7 OF 10) AE22
VCC_NCTF5 VSS_NCTF5

D
V27 VCC_NCTF6 VSS_NCTF6 AE21
D

NCTF
U27 VCC_NCTF7 VSS_NCTF7 AE20

T27 VCC_NCTF8 VSS_NCTF8 AE19

R27 VCC_NCTF9 VSS_NCTF9 AE18


AD26 VCC_NCTF10 VSS_NCTF10 AC17

AC26 VCC_NCTF11 VSS_NCTF11 Y17


AB26 VCC_NCTF12 VSS_NCTF12 U17

AA26 VCC_NCTF13
Y26 VCC_NCTF14
W26 VCC_NCTF15
=PP1V5_S0_NB_VCCAUX 6 17 19
V26 VCC_NCTF16
VCCAUX_NCTF0 AG27
U26 VCC_NCTF17
VCCAUX_NCTF1 AF27
T26 VCC_NCTF18
VCCAUX_NCTF2 AG26
R26 VCC_NCTF19
VCCAUX_NCTF3 AF26
AD25 VCC_NCTF20
VCCAUX_NCTF4 AG25
AC25 VCC_NCTF21
VCCAUX_NCTF5 AF25
AB25 VCC_NCTF22
VCCAUX_NCTF6 AG24
AA25 VCC_NCTF23
=PPVCORE_S0_NB 6 16 19 VCCAUX_NCTF7 AF24
Y25 VCC_NCTF24
1.05V or 1.5V VCCAUX_NCTF8 AG23
W25 VCC_NCTF25
VCCAUX_NCTF9 AF23
V25 VCC_NCTF26
AA33

AA32

AA31

AA30

AA29

AB28

AA28

AB23

AA23

AC22
AB22

AC21

AA21

AC20

AB20

AB19
AA19
VCCAUX_NCTF10 AG22
W33

P33
N33

L33

J33

Y32

W32
V32

P32
N32

M32

L32
J32

W31
V31

T31

R31
P31

N31
M31

Y30

W30

V30

U30

T30

R30

P30
N30

M30

L30

Y29
W29

V29

U29
R29

P29

M29

L29

Y28

V28

U28

T28

R28

P28

N28

M28

L28

P27
N27

M27

L27

P26

N26

L26

N25

M25

L25

P24

N24
M24

Y23

P23

N23

M23

L23

Y22
W22

P22

N22

M22

L22

W21

N21
M21

L21

Y20

W20

P20

N20
M20

L20

Y19

N19

M19

L19

N18

M18

L18
P17

N17

M17

N16

M16
L16
U25 VCC_NCTF27
VCCAUX_NCTF11 AF22
T25 VCC_NCTF28
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79
VCC_80
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_86
VCC_87
VCC_88
VCC_89
VCC_90
VCC_91
VCC_92
VCC_93
VCC_94
VCC_95
VCC_96
VCC_97
VCC_98
VCC_99
VCC_100
VCC_101
VCC_102
VCC_103
VCC_104
VCC_105
VCC_106
VCC_107
VCC_108