UNIT-V

MEMORY DEVICES

INTRODUCTION

In digital systems memories are used for the storage of binary information or data. It is well known that a flip-
flop can be used to store the binary bit (0 or 1). So the flip-flops can be organized to form storage registers.

These registers are combined to form a memory unit which is capable of storing large data. So the information
to be stored in the digital system is transferred to these registers, where this information is retained and can be
retrieved whenever required for processing in the digital systems.

The Read Only Memory (ROM) and the Random Access Memory (RAM) are the two basic types of
semiconductor memories. ROMs are those in which information or the data is permanently stored. The information
can be read but fresh information cannot be written into it. These are non-volatile memories. The other
semiconductor memory RAM has both read write facilities. So the RAMs are also called as read write (R/W)
memories. These are volatile memories.

GENERAL MEMORY OPERATIONS

The memory unit can be used to store a large number of binary words. A binary word is a combination of
binary bits. A binary memory cell is used to store a binary bit. If the length of the word in a system is of 8 bits then
eight binary memory cells are combined to store a byte. Each byte stored in the memory unit will have different
memory locations. The location of the memory unit where a word is to be stored or written is called the address of
the word.

The word to be stored in the memory unit is first entered in the memory buffer register (MBR) also called as
memory data register (MDR). The address where the word is to be stored is given in the Memory Address Register
(MAR).

A WRITE signal is initiated by the control unit and the particular byte will be written or stored in the specified
memory location or the address. The length of MAR will, however, depend on the capacity of the memory locations. If
a memory unit has the capacity to store m bytes , the length of MAR will be of n bits such that 2n = m i.e. the length of
MAR will be of 12 bits if the memory unit has the capacity to store 4096 bytes as 212 = 4096.

Similarly a READ signal is initiated by the control unit and the particular byte will be read from the specified memory
location or the address.

There are some important terms related to memory unit which will now be discussed.

Access Time of Memory: The time interval between the initiation of the READ signal and the availability of the
stored content from the required memory location is known as the access time of memory.

Write Time of Memory and Memory Cycle Time: The time interval between the initiation of the WRITE signal
and the storing of the content in the specified memory location is known as the write time of memory.

Volatile and Non-volatile Memories: The memory unit in which the stored content is lost when the power is turned
off is known as volatile memory. The memory unit consisting of binary cells made with magnetic cores is known as
non-volatile as the stored data is not lost when the power is turned off.
Figure 1 shows the block diagram of a memory system.

Fig 1: Memory operations block diagram

READ ONLY MEMORIES

As discussed the read only memory is used to read the stored information or data but the fresh information
cannot be written into it. A block diagram of a read only memory is shown in figure 1, in which 8 words are stored
and each word is of five bit long.

Fig 2: Read Only Memory

At each intersection point in the grid, diode is either present or absent. If a diode is present at the intersecting point
then that bit of the word is a 1 else it is a 0. This grid connected with diodes at some intersecting points is known as
diode matrix ROM.
Most ROMs available in the market are made with bipolar transistors or MOS transistors instead of diodes. At the
intersecting points bipolar transistors or MOS transistors are connected.

A bipolar cell for storing a 1 is shown in figure 2(a) in which the base of the transistor is connected to the row wire
while the emitter is connected to the column line. A bipolar cell for storing a 0 is shown in figure 2(b) in which base
connection is left open which result no current to flow through column wire.

Fig 2: Transistor ROM Cell

PROGRAMMABLE READ ONLY MEMORY (PROM)

In PROMs bipolar or MOS transistors are connected to each joint and fusible links are provided to these
transistors. Figure 1 illustrates a bipolar PROM array with fusible links provided at the emitter of each transistor
connected at the joints. The fusible links may be burnt to store a bit 0; and a bit 1 is stored to keep the link intact. The
user can burn the necessary links to store the desired data.

Fig 1: PROM Cell

ERASABLE PROGRAMMABLE READ ONLY MEMORY (EPROM)

The information or data once stored in ROM or in PROM can not be altered but in EPROMs the data can be
erased and reprogrammed. Each binary cell in EPROM is formed with MOS transistor having a floating gate known as
Isolated Gate MOSFET.
 If a sufficiently high voltage programming pulse is applied to the transistor, the high energy electrons are
injected into the floating gate. Even after the termination of the programming pulse the electrons are trapped into the
gate. Because the gate is completely isolated the charges cannot leak very rapidly. Fig 1 shows EPROM cell

Fig 1: EPROM Cell

The data can be erased if EPROM chip is exposed to the ultraviolet (UV) light. A quartz window on the chip
is provided for the exposure of ultraviolet light. The ultraviolet light removes the stored charges on the floating gates
of the MOS transistors. The erasing process usually takes 25 to 30 minutes. Erased chip may further be programmed
with fresh data.

ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY (EEPROM )

Electrically erasable Programmable Read Only Memories (EEPROMs) are also available as an improvement
over EPROM. In EEPROMs also known as E2PROMs, individual word in the memory can be electrically erased and
reprogrammed. In EPROMs complete memory contents are to be erased and reprogramming of the complete
memory chip is to be required even if one or two words of the memory are to be altered.

The memory cells of E2PROMs utilize MOS transistors with floating gate structure similar to EPROMs, with the
addition of very thin oxide region above the drain. This modification allows the cell to be electrically erased by
applying a high voltage (21 V) between the gate and drain of MOS transistors. E2PROMs can be erased in negligibly
small time of 10 msec.

APPLICATIONS OF ROMs:
Read Only Memories are used in variety of tasks in the digital systems. Following are the common
applications of ROMs:

Implementation of Logic Functions: ROMs can be used to implement circuit for any logic function.

Look-up tables: It is a usual practice to use ROMs as look-up tables for routine calculations in a computer.
Trigonometric functions, logarithms, exponentials and square root etc are programmed as look-up tables in
ROMs and used in lengthy calculations.

Code Converters: The ROMs can be used as code converter circuits. The data expressed in one type of
code can be produced in other type of code.
Electrically alterable read-only memory(EAROM)

It is a type of EEPROM that can be modified one bit at a time. Writing is a very slow process and again
needs higher voltage (usually around 12 V) than is used for read access. EAROMs are intended for applications
that require infrequent and only partial rewriting. EAROM may be used as non-volatile storage for critical system
setup information; in many applications, EAROM has been supplanted by CMOS RAM supplied by mains power
and backed-up with a lithium battery.

RANDOM ACCESS MEMORIES:

Random Access Memory (RAM) is also known as Read/write memory. The Data can be written in to the
memory location and can be read /retrieved from the memory locations. Basically RAMs are of three types
Bipolar RAM and Static RAM and Dynamic MOS RAM.

Bipolar RAM

The cells of RAM make use of flip-flops which are designed using bipolar transistors.It is made using
two dual emitter transistors. These types of RAM cells are used for linear selection.

Fig 1 : Bi-polar RAM cell

In this type, one emitter of each of transistors Q1 and Q2 are connected together to signal S. The second emitter of
transistor Q1 serves to sense (read) or writes a logic 0 (Q1 ON). Similarly the second emitter of transistor Q2 serves to
sense or write logic 1 (Q2 conducting).

Static RAM

In Static RAM or SRAM, the data stored into a memory cell is lasting until the power supply to the RAM
IC is ON. The memory cell of static RAM is designed with a S-R flip-flop as shown in fig 2.

Fig 2: Static RAM Cell

 As shown in fig 2, the memory cell of a static RAM consisting a S-R flip-flop is being operated in SET
(i.e., S=1 and R=0) mode and in RESET (i.e., S=0 and R=1) mode with a NOT gate, to write logic 1 and logic 0
respectively.
Though the read/write signal is given as single input, in this figure, they are two separate signals. Write
Enable is controlling the input AND gates to enable the input to flip-flop. While the Read Enable is controlling
output AND gate to draw output from the cell.

Dynamic MOS RAM Cell

Figure 3 illustrates a dynamic MOS RAM cell also called DRAM cell. It consists of a MOS transistor and
a capacitor. The charging of the capacitor is controlled by the MOS transistor. The capacitor can hold a very small
charge when it is charged.

To write a bit 1 on the cell the address line is kept high, a high voltage is applied to the bit/sense line. The
transistor is switched ON and the capacitor is charged. The logic 1 is stored in the cell. However to write a bit 0,
0 volt is applied to the sense lin e and the capacitor is discharged and 0 is stored.

Fig 3 : DRAM Cell

To read the stored data in the cell high voltage is again applied to the address line. This switches ON the
transistor and the capacitor voltage appears on the bit/sense line.

PROGRAMMABLE LOGIC DEVICES

The programmable logic devices (PLDs) are medium scale integrated circuits and these devices can replace a
number of standard ICs. Thus PLDs help in designing larger circuit on small space with ease.

A PLD is a programmable IC which contains large number of interconnected gates, flip flops and registers
etc. Many of the interconnections are fusible. The connections which are not required by the designers are fused or
broken. Programming of fuse blowing as per the required circuit pattern is done by the manufacturer or by the
customer.
 PLDs fall into three categories. They are known as:

(i) Programmable Read Only Memory (PROM)

(ii) Programmable Array logic (PAL)
(iii) Programmable Logic Array (PLA)

PROGRAMMABLE READ ONLY MEMORY (PROM)

In PROM, the structure is build of an AND array followed by OR array. The AND array is not
programmable while OR array is programmable. So connections from input lines to the AND gates are hard
wired, while the connections to the OR gates from the outputs of the AND array are programmable (each joint is
marked with circled cross mark ).

If there are N input variables, then 2N product terms are generated. One AND gate will be used for each
product term, so there will be 2N AND gates or rows. The OR array will be of any number. Figure 1 shows 16 X 4
PROM. Since 16 = 24, so it will have 4 address or inputs lines and 4 data outputs.

Fig 1: PROM as PLD

PROMs find many applications like the implementation of Boolean functions, code converters and data
storage tables.

Example 6.9: Using 16 X 4 PROM, implement the following functions of 4 variables.

Y 0 ( A , B , C , D ) m ( 0 ,1, 4 ,5 ,8 ,9 ,10 ,14 ,15 )

Y 1 ( A , B , C , D ) m ( 2 , 3 , 4 , 9 ,10 ,11 ,13 ,15 )

Y3 ( A , B , C , D ) =m (5,6 ,7 ,10 ,13 )

Solution: By making the suitable programming of OR array, the given Boolean functions are realized using
16 X 4 PROM as shown in figure 2.

Fig 2: PROM as PLD

PROGRAMMABLE ARRAY LOGIC (PAL)

Another class of Programmable logic devices is the programmable array logic (PAL) which is widely used and
easily programmable. The PAL has an AND array followed by OR array similar to FPLA, with the difference that
the inputs to AND array are programmable while the inputs to OR gates are hard wired (fixed OR array). Figure 1
shows the architecture of a PAL device having 16 AND gates and four OR gates. In this case the product terms of
each expression should not exceed 4 terms.

Fig 1: PAL as PLD

The PAL structure is the most generic one for the implementation of arbitrary logic functions.

Example 6.8: Using the PAL shown in figure 6.47, implement the following SOP functions of 4 variables.

Solution: Figure 6.48 shows the implementation of the given functions using the PAL.

Fig 2: PAL as PLD

PROGRAMMABLE LOGIC ARRAY (PLA):

Figure 1 demonstrates the basic structure of Programmable Logic array (PLA). In this logic device, both AND
array and OR array are programmable. The circled cross marks to the input lines of AND and OR gates indicate that
these connections are fusible or programmable.

Now if the circled cross mark of some inputs of AND gate are burnt (or remove fuse), then min-term of
the remaining input variables (fused variables) will be obtained. Similarly by burning the unused circled cross
marks of OR array will give the required outputs in SOP.

It is very versatile since both AND and OR arrays are programmable. However, it has some
disadvantages; it is more difficult to manufacture, program or test than other PLDs.
 Fig 1 PLA as PLD

Example: Implement a BCD to seven segment decoder circuit using a PLA of proper specification.

Solution: There are 15 independent min-terms in these expressions. So for their realization the FPLA should
have 4 input variables, 15 AND gates and 6 OR gate. The realization of 7 outputs of BCD to seven segment
display is shown in figure 2.
Fig 2 : 7 segment display driver using PLA