PLCs and Other Logic Devices

5.1 5.3
BINARY LOGIC DIAGRAMS FOR PROCESS OPTIMIZATION OF LOGIC CIRCUITS 898
OPERATIONS 880 Optimization Building Blocks 898
1. Purpose 880 Graphic Logic Functions 900
2. Scope 880 Ladder Diagrams from Logic Diagrams 901
3. Use of Symbols 880 Optimized Logic Circuit Construction 901
4. Symbols 881 Logic Circuit Synthesis 902
Appendix A: General Application Example 888 Logic Simplification with Boolean Algebra 903
A1. Introduction 888 Logic Simplification through Logic Maps 903
A2. Simplified Flow Diagram 888 Negative vs. Positive Logic Usage 904
A3. Word Description 888 Summary 904
A4. Logic Diagram 890 Bibliography 905
Appendix B: Complex Time-Element Example 891
B.1 Word Description 891 5.4
Appendix C: Loss of Power Supply PLCs: PROGRAMMABLE LOGIC CONTROLLERS 906
for Memory 891
Bibliography 892 Introduction 907
History 907
PLC Sizes 909
5.2
Nano PLCs 909
LADDER DIAGRAMS 893
Basic PLC Components 909
Introduction 893 Central Processor Unit (Real Time) 910
Ladder Diagram Symbols 893 Memory Unit 910
Developing a Ladder Diagram 894 I/O Systems 912
Automatic Mode of Operation 895 PLC Power Supply 915
Summary 895 Additional PLC Components 915
Ladder Diagram Analysis 895 Communications Modules 915
Start-Up and Shutdown 896 Remote I/O 915
Dynamic Breaking of a Motor 896 Peer-to-Peer Communications 916
Fail-Safe Design 897 Peripheral Devices 917
Documentation 897 Local Operator Interface 917
Conclusions 897 Human-Machine Interface 918
Bibliography 897 Printers 919

877

2006 by Bla Liptk

878 PLCs and Other Logic Devices

Programmers and Workstations 919 Ladder Logic Advances 968

Justification for the Use of PLCs 920 Program Flow Modification 968
PLCs vs. Relays and Stand-Alone Indirect Addressing 969
Controllers 920 Assembly Language-Like Extensions 971
PLC vs. DCS 921 Communication with Intelligent Devices 971
PLC vs. Personal Computers 922 Fast I/O Updating Methods 972
Summary 922 Graphic, Flowchart-Like Languages 972
Project Execution 923 IEC 61131-3 PLC Language Standard 973
Systems Analysis 923 Conclusion 974
Open Systems 925 References 974
PLC Hardware, System Sizing, Bibliography 975
and Selection 926
PLC Installation and Panel Design 928
Software (Program) Development 932 5.7
Software/Hardware Integration 938 PRACTICAL LOGIC DESIGN 976
System Checkout and Start-Up 939 Design Philosophy 976
After Start-Up 939 Open/Close Valves 976
Conclusion 940 Definitions 976
References 940 Auto Mode 978
Bibliography 941 Motor-Operated Valves 979
Failure Logic 979
5.5 Solenoid Valves 981
PLC PROGRAMMING 944 Pumps 981
Definitions 981
Introduction 944
Auto Mode 983
What Is a PLC? 944
Pump Fail 984
System Hardware and Operation 944
Other Common Problems with Pump Logic
Programming Languages 946
Design 984
Instruction List 946
Pumps with Two Outputs 984
Structured Text 946
Controlling Two Pumps Together 984
Sequential Function Charts 946
Breakers 986
Function Block Diagrams 947
Analog Controls 986
Ladder Logic Programming 947
Switchover 986
Ladder Logic Structure 947
Pop Open/Clamp Closed 986
Ladder Logic Programming Basic
Override Open and Close 988
Instructions 948
Feedforward 988
Memory Structure 952
Cascade 989
Ladder Logic Programming Devices 953
Three-Transmitter Select 989
Programming Considerations 953
Switch to Manual Mode 990
Program Documentation 954
Changing the Set Point with Changes in
PLC Hardware Configuration 954
the Number of Pumps Running 990
Ladder Program Structure 955
Start-Up and Shutdown Sequences 990
Typical GE Fanuc PLC 955
Operation and Customization 992
Typical Allen-Bradley PLCs 956
A Note on Safety 992
Typical Modicon PLC 984 958
Bibliography 992
Access and Programming Modes 958
Developing the PLC Program Logic 960
Testing and Simulation 962 5.8
Advances in Programming 964 PROGRAMMABLE SAFETY SYSTEMS 993
Reference 965
Bibliography 965 Introduction 993
Risk Reduction 994
History 994
5.6 Safety Standards 996
PLC SOFTWARE ADVANCES 966 IEC 61508: General Safety Standard 996
Introduction 966 IEC 61511: Safety Standard for Process
Graphic Description of Control Requirements 966 Industries 996

2006 by Bla Liptk

 Contents of Chapter 5 879

ANSI/ISA-84.01 Standard 997 Implementation Options 1021

Management Considerations 999 Solid-State Logic Options 1021
Hazard and Risk Analysis 999 Bibliography 1022
As Low as Reasonably Practicable
(ALARP) 999
5.11
Required Safety Integrity Level 999
Semi-Quantitative Risk Analysis Techniques 1001 SYSTEM INTEGRATION: COMPUTERS
Risk Graphs 1001 WITH PLCS 1023
Safety System Certification 1001 Introduction 1023
Major Trends 1003 PCs for Programming the PLC 1024
Overall Safety 1003 PCs for Monitoring and Supervising
Separation from the Control System 1003 the PLC 1024
Flexibility and Scalability 1003 SCADA System 1024
Function Blocks 1004 Handling of Tasks 1025
Safety System Selection 1004 Implementation 1025
Acknowledgments 1004 Serial Link 1025
Acronyms 1004 Communication Networks 1025
References 1005 Performance 1027
Bibliography 1005 Generation Time (Tg) 1027
Transmission Time (Tt ) 1027
5.9 Te, Tr, and Trd 1028
RELAYS 1006 Conclusions 1028
References 1028
Introduction 1007
Bibliography 1028
Relay Types and Features 1007
Special Relays 1007
Relay Characteristics 1008 5.12
Rating, Size, and Other Selection Criteria 1008 TIME DELAY RELAYS 1030
Contact Configurations 1008
General Characteristics 1031
Mechanical Structures 1009
Timer Modes and Characteristics 1031
Contact Materials 1010
Types of Time Delays 1032
Contact Shape and Mounting 1011
Types of Designs 1033
Selection and Application 1011
Bibliography 1035
Selection 1011
Relative Costs 1012
Relays vs. Solid-State Devices 1012 5.13
Electromechanical Advantages 1012 TIMERS AND PROGRAMMING TIMERS 1036
Solid-State Advantages 1013
Introduction 1036
Conclusions 1013
Mechanical Timers and Sequencers 1036
Bibliography 1013
Cam Timers 1036
Band or Drum Programmers 1037
5.10 Punched-Card Programmers 1037
SOLID-STATE LOGIC ELEMENTS 1015 Timers 1037
Introduction 1015 One-Shot Timers 1037
Analog Circuit Elements 1016 Monostable and Astable Designs 1037
Transistor Switch 1016 Delay on Break 1038
Diodes and Their Switching 1017 555 Devices 1039
Transistors 1017 Hybrid Timing Circuits 1039
Integrated Circuit Elements 1018 Digital Sequencers 1040
Families of IC Switching 1018 Asynchronous Sequencers 1041
Applications 1020 Electronic Sequencers 1042
Merging Human and Instrument Inputs 1020 Conclusions 1042
Time Synchronization 1020 Bibliography 1042

2006 by Bla Liptk

5.1 Binary Logic Diagrams for Process Operations
Standard formatted for publication in this handbook by:
J. E. JAMISON (2005)
Reprinted by permission. Copyright 1976, Instrument Society of America. From ANSI/ISA-S5.2-1976 (R 1992),
Binary Logic Diagrams for Process Operations, reaffirmed July 13, 1992. Also, permission was granted by
ISA for inclusion of the latest thinking on binary logic, memory, and time functions from Draft 4 of ISA Draft
5.01.01 Instrumentation Symbols and Identification, Copyright 2000 ISA, which now includes the previous S5.2.
1. PURPOSE
1.1 The purpose of this Standard is to provide a method of
logic diagramming of binary interlock and sequencing sys-
tems for the start-up, operation, alarm, and shutdown of
equipment and processes in the chemical, petroleum, power
generation, air conditioning, metal refining, and numerous
other industries.
1.2 The Standard is intended to facilitate the understand-
ing of the operation of binary systems and to improve com-
munications among technical, management, design, operat-
ing, and maintenance personnel concerned with the systems.
2. SCOPE
2.1 The Standard provides symbols, both basic and nonbasic,
for binary operating functions. The use of symbols in typical
systems is illustrated in the appendices.
2.2 The Standard is intended to symbolize the binary
operating functions of a system in a manner that can be
applied to any class of hardware, whether it be electronic,
electrical, fluidic, pneumatic, hydraulic, mechanical, manual,
optical, or other.
3. USE OF SYMBOLS
3.1 By using the symbols designated as basic, logic systems
may be described with the use of only the most fundamental
logic building blocks. The remaining symbols, not basic, are
more comprehensive and enable logic systems to be diagrammed
more concisely. Use of the nonbasic symbols is optional.
3.2 A logic diagram may be more or less detailed depending
on its intended use. The amount of detail in a logic diagram
depends on the degree of refinement of the logic and on whether
auxiliary, essentially nonlogic, information is included.
1
A disclaimer to any future ISA Standards documents is hereby stated. The
reader is cautioned that the Draft ISA Document that provided Table 5.1a
has not been approved as of the time of this writing. Therefore, it cannot
be presumed to reflect the position of ISA or any other committee, society,
or group.
880
2006 by Bla Liptk
1
As an example of refinement of detail: A logic system may
have two opposing inputs, e.g., a command to open and a
command to close, which do not normally exist simulta-
neously; the logic diagram may or may not go so far as to
specify the outcome if both the commands were to exist at the
same time. In addition, explanatory notes may be added to the
diagram to record the logic rationale.
Nonlogic information may also be added, if desired, e.g.,
reference document identification, tag numbers, terminal
markings, and so on.
In these ways, the diagram may provide the level of detail
appropriate, for example, for communication between a
designer of pneumatic circuits and a designer of electric circuits,
or may provide a broad-view system description for a plant
manager.
3.3 The existence of a logic signal may correspond phys-
ically to either the existence or the nonexistence of an instru-
ment signal, depending on the particular type of hardware
2
system and the circuit design philosophy that are selected.
For example, a high-flow alarm may be chosen to be actuated
by an electric switch whose contacts open on high flow; on
the other hand, the high-flow alarm may be designed to be
actuated by an electric switch whose contacts close on high
flow. Thus, the high-flow condition may be represented phys-
ically by the absence of an electric signal or by the presence
of the electric signal. The Standard does not attempt to relate
the logic signal to an instrument signal of any specific kind.
3.4 A logic symbol that is shown in Section 4 with three
inputsA, B, and C is typical for the logic function having
any number of two or more inputs.
3.5 The flow of intelligence is represented by lines that
interconnect logic statements. The normal direction of flow
is from left to right, or top to bottom. Arrowheads may be
added to the flow lines wherever needed for clarity and shall
be added to lines whose flow is not in a normal direction.
2
In process operations, binary instrument signals are commonly either ON
or OFF. However, as a more general case, logic systems exist that make use
of binary hardware having signals with two alternate real values, e.g., +5 V
and 3 V. In positive logic, the more positive signal, +5 V, represents the
existence of a logic condition, e.g., pump stopped. In negative logic, the less
positive signal, 3 V, represents the existence of a logic condition of pump
stopped.

3.6 A summary of the status of an operating system may
be put in the diagram wherever it is deemed useful as a
reference point or landmark in the sequence.
3.7 There may be misunderstanding of binary logic
statements involving devices that are not recognizable as
inherently having only two specific alternative states. For
example, if it is stated that a valve is not closed, this could
mean either (a) that the valve is open fully, or (b) that the
valve is simply not closed, namely, that it may be in any
position from almost closed to wide open. To aid accurate
communication between writer and reader of the logic dia-
gram, the diagram should be interpreted literally. Therefore,
possibility (b) is the correct one.
If a valve is an open-close valve, then, to avoid misun-
derstanding, it is necessary to do one of the following:
1. Develop the logic diagram in such a way that it says
exactly what is intended. If the valve is intended to be
open, then it should be so stated and not be stated as
being not closed.
2. Have a separate note specifying that the valve always
assumes either the closed or the open position.
By contrast, a device such as a motor-driven pump is
either operating or stopped, barring some special situations.
To say that the pump is not operating usually clearly denotes
that it has stopped.
The following definitions apply to devices that have open,
closed, or intermediate positions. The positions stated are
nominal to the extent that there are differential-gap and dead
band in the instrument that senses the position of the device.
Open position: a position that is 100% open.
Not-open position: a position that is less than 100% open.
A device that is not open may or may not be closed.
Closed position: a position that is 0% open.
Not-closed position: a position that is more than 0%
open. A device that is not closed may or may not
be open.
Intermediate position: a SPECIFIED position that is
greater than 0% and less than 100% open.
Not-at-intermediate position: a position that is either
above or below the SPECIFIED intermediate position.
For a logic system having an input statement that is
derived inferentially or indirectly, a condition may arise that
will lead to an erroneous conclusion. For example, an
assumption that flow exists because a pump motor is ener-
gized may be false because of a closed valve, a broken shaft,
or other mishap. Factual statements, that is, statements based
on positive measurements that a certain condition specifically
exists or does not exist, are generally more reliable.
3.8 A process operation may be affected by loss of the
3 timing functions. Application information and examples on
power supply to memories and to other logic elements. In
order to take such operating eventualities into account, it may
therefore be necessary to consider the effect of loss of power
to any logic component or to the entire logic system. In such
2006 by Bla Liptk
5.1 Binary Logic Diagrams for Process Operations 881
cases, it may be necessary to enter power supply or loss of
power supply as logic inputs to a system or to individual
logic elements. For memories, the consideration of power
supply may be handled in this manner or as shown in sections
1012 in Table 5.1a.
By the same token, it may be necessary to consider the
effect of restoration of power supply.
Logic diagrams do not necessarily have to cover the effect
of logic power supplies on process systems but may do so
for thoroughness.
3.9 It is recommended, for clarity, that a single time-
function symbol, as appropriate, be used to represent each
time function in its entirety. Though not incorrect, the repre-
sentation of a complex or uncommon time function by using
a time-function symbol in immediate sequence with a second
time-function symbol or with a NOT symbol should be
avoided (see Table 5.1a).
3.10 Process instrument symbols and designations follow
ANSI/ISA Standard S5.1-1984 (formerly American National
Standards Institute Standard Y32.20-1975), Instrumentation
Symbols and Designations. However, these symbols are
included for illustrative purposes only, and are not part of
Standard S5.2.
3.11 If a drawing, or set of drawings, uses graphic sym-
bols that are similar or identical to one another in shape or
configuration and that have different meanings because they
are taken from different standards, then adequate steps shall
be taken to avoid misinterpretation of the symbols used.
These steps may be to use caution notes or reference notes,
comparison charts that illustrate and define the conflicting
symbols, or other suitable means. This requirement is espe-
cially critical if the graphic symbols used, being from differ-
ent disciplines, represent devices, conductors, flow lines, or
signals whose symbols, if misinterpreted, may result in dan-
ger to personnel or damage to equipment.
4. SYMBOLS
The symbols for diagramming binary logic are defined in
Table 5.1a and are the latest thinking of the ISA SP5.1 sub-
committee:
The symbols in Table 5.1a are never used in piping and
instrument diagrams (P&IDs) and are used to help document
and diagram logic control designs and narratives. The present
Standard ISA S5.2 (ANSI/ISA-S5.2-1976(R1992) is now
being revised and rolled into the new ANSI/ISA-5.01.01 stan-
dard as proposed in the current (as of this writing) Draft 4.
Symbols, Truth Tables, Definitions, and Graphs used here in
Section 5.1 are in accordance with Draft 4 and are very
different from S5.2. These are given here to illustrate to the
reader the latest thinking in this area, including expanded
3
The term power supply covers the energizing medium, whether it be
electric, pneumatic, or other.
882 PLCs and Other Logic Devices

TABLE 5.1a
Instrument and Control System Functional Diagramming Symbols-Binary Logic, Memory, and Time Functions (Proposed for the next
revision of ISA S5.1 (now ANSI/ISA-5.01.01) at the time of this writing)
Symbol Definition

No Truth Table Graph

01 1. AND gate.
A 2. Output true only if all inputs are true.
B A
C N O
D
x

A B C x O 1
1 0 0 0 0 0 A 0
2 1 0 0 0 0
3 0 1 0 0 0 B
4 0 0 1 0 0 C
5 0 0 0 1 0
6 1 1 0 0 0 X
7 1 0 1 0 0
8 1 0 0 1 0
9 0 1 1 0 0 O
10 0 1 0 1 0 t
11 0 0 1 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
12 1 1 1 0 0
13 1 1 0 1 0
14 1 0 1 1 0
15 0 1 1 1 0
16 1 1 1 1 1

02 1. OR gate.
A 2. Output true if any input is true.
B
C OR O
x

A B C x O 1
1 0 0 0 0 0 A 0
2 1 0 0 0 1
3 0 1 0 0 1 B
4 0 0 1 0 1 C
5 0 0 0 1 1
6 1 1 0 0 1 X
7 1 0 1 0 1
8 1 0 0 1 1
9 0 1 1 0 1 O
10 0 1 0 1 1 t
11 0 0 1 1 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
12 1 1 1 0 1
13 1 1 0 1 1
14 1 0 1 1 1
15 0 1 1 1 1
16 1 1 1 1 1

2006 by Bla Liptk

 5.1 Binary Logic Diagrams for Process Operations 883

TABLE 5.1a (continued)

Instrument and Control System Functional Diagramming Symbols-Binary Logic, Memory, and Time Functions (Proposed for the next
revision of ISA S5.1 (now ANSI/ISA-5.01.01) at the time of this writing)
Symbol Definition

No Truth Table Graph

03 1. Qualified OR gate with greater than or equal to qualifications.

A
B 2. Output equals 1 if number of inputs equal to 1 are greater than or equal to n inputs.
C n O 3. Truth table and graph are for n equals 2.

A B C x O 1
1 0 0 0 0 0 A 0
2 1 0 0 0 0
3 0 1 0 0 0 B
4 0 0 1 0 0 C
5 0 0 0 1 0
6 1 1 0 0 1 X
7 1 0 1 0 1
8 1 0 0 1 1
9 0 1 1 0 1 O
10 0 1 0 1 1 t
11 0 0 1 1 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
12 1 1 1 0 1
13 1 1 0 1 1
14 1 0 1 1 1
15 0 1 1 1 1
16 1 1 1 1 1

04 1. Qualified OR gate with greater than qualifications.

A
B 2. Output equals 1 if number of inputs equal to 1 are greater than but not equal to n inputs.
C >n O 3. Truth table and graph are for n equals 2.

A B C x O 1
1 0 0 0 0 0 A 0
2 1 0 0 0 0
3 0 1 0 0 0 B
4 0 0 1 0 0 C
5 0 0 0 1 0
6 1 1 0 0 0 X
7 1 0 1 0 0
8 1 0 0 1 0
9 0 1 1 0 0 O
10 0 1 0 1 0 t
11 0 0 1 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
12 1 1 1 0 1
13 1 1 0 1 1
14 1 0 1 1 1
15 0 1 1 1 1
16 1 1 1 1 1

2006 by Bla Liptk

884 PLCs and Other Logic Devices

TABLE 5.1a (continued)

Instrument and Control System Functional Diagramming Symbols-Binary Logic, Memory, and Time Functions (Proposed for the next
revision of ISA S5.1 (now ANSI/ISA-5.01.01) at the time of this writing)
Symbol Definition

No Truth Table Graph

05 1. Qualified OR gate with less than or equal to qualifications.

A
B 2. Output equals 1 if number of inputs equal to 1 are less than or equal to n inputs.
C n O 3. Truth table and graph are for n equals 2.

A B C x O 1
1 0 0 0 0 0 A 0
2 1 0 0 0 1
3 0 1 0 0 1 B
4 0 0 1 0 1 C
5 0 0 0 1 1
6 1 1 0 0 1 X
7 1 0 1 0 1
8 1 0 0 1 1
9 0 1 1 0 1 O
10 0 1 0 1 1 t
11 0 0 1 1 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
12 1 1 1 0 0
13 1 1 0 1 0
14 1 0 1 1 0
15 0 1 1 1 0
16 1 1 1 1 0

06 1. Qualified OR gate with less than qualifications.

A
B 2. Output equals 1 if number of inputs equal to 1 are less than but not equal to n inputs.
C <n O 3. Truth table and graph are for n equals 2.

A B C x O 1
1 0 0 0 0 0 A 0
2 1 0 0 0 1
3 0 1 0 0 1 B
4 0 0 1 0 1 C
5 0 0 0 1 1
6 1 1 0 0 0 X
7 1 0 1 0 0
8 1 0 0 1 0
9 0 1 1 0 0 O
10 0 1 0 1 0 t
11 0 0 1 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
12 1 1 1 0 0
13 1 1 0 1 0
14 1 0 1 1 0
15 0 1 1 1 0
16 1 1 1 1 0

2006 by Bla Liptk

 5.1 Binary Logic Diagrams for Process Operations 885

TABLE 5.1a (continued)

Instrument and Control System Functional Diagramming Symbols-Binary Logic, Memory, and Time Functions (Proposed for the next
revision of ISA S5.1 (now ANSI/ISA-5.01.01) at the time of this writing)
Symbol Definition

No Truth Table Graph

07 1. Qualified OR gate with equal to qualifications.

A
B 2. Output equals 1 if inputs equal to 1 are equal to n inputs.
C =n O 3. Truth table and graph are for n equals 2.

A B C x O 1
1 0 0 0 0 0 A 0
2 1 0 0 0 0
3 0 1 0 0 0 B
4 0 0 1 0 0 C
5 0 0 0 1 0
6 1 1 0 0 1 X
7 1 0 1 0 1
8 1 0 0 1 1
9 0 1 1 0 1 O
10 0 1 0 1 1 t
11 0 0 1 1 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
12 1 1 1 0 0
13 1 1 0 1 0
14 1 0 1 1 0
15 0 1 1 1 0
16 1 1 1 1 0

08 1. Qualified OR gate with not equal to qualifications.

A
B 2. Output equals 1 if inputs equal to 1 are not equal to n inputs.
C n O 3. Truth table and graph are for n equals 2.

A B C x O 1
1 0 0 0 0 0 A 0
2 1 0 0 0 1
3 0 1 0 0 1 B
4 0 0 1 0 1 C
5 0 0 0 1 1
6 1 1 0 0 0 X
7 1 0 1 0 0
8 1 0 0 1 0
9 0 1 1 0 0 O
10 0 1 0 1 0 t
11 0 0 1 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
12 1 1 1 0 1
13 1 1 0 1 1
14 1 0 1 1 1
15 0 1 1 1 1
16 1 1 1 1 1

2006 by Bla Liptk

886 PLCs and Other Logic Devices

TABLE 5.1a (continued)

Instrument and Control System Functional Diagramming Symbols-Binary Logic, Memory, and Time Functions (Proposed for the next
revision of ISA S5.1 (now ANSI/ISA-5.01.01) at the time of this writing)
Symbol Definition

No Truth Table Graph

09 1. NOT gate.
A NOT O 2. Output false if input true.
3. Output true if input false.

A O 1
1 0 A 0
0 1
1
O 0

t
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

10 1. Basic memory.
A S C 2. Outputs C and D are always opposite.
B R D 3. If input A equals 1 then output C equals 1 and D equals 0.
4. If input A changes to 0 output C remains 1 until input B equals 1, then C equals 1 and D equals 0.
5. If input B equals 1 then output D equals 1 and C equals 0.
6. If input B changes to 0 output D remains 1 until input A equals 1, then D equals 1 and C equals
0.
7. If inputs A and B are simultaneously equal to 1 then outputs C and D change state.

A B C D 1
1 0 0 0 1 A 0
2 1 0 1 0
3 0 0 1 0 B
4 0 1 0 1
C
5 0 0 0 1
6 1 1 1 0 D
7 0 0 1 0
8 1 1 0 1 t
1 2 3 4 5 6 7 8

11 1. Set dominant memory (So Dominant).

A S0 C 2. Outputs C and D are always opposite.
B R D 3. If input A equals 1 then output C equals 1 and D equals 0.
4. If input A changes to 0 output C remains 1 until input B equals 1, then output C equals 1 and
D equals 0.
5. If input B equals 1 then output D equals 1 and C equals 0.
6. If input B changes to 0 output D remains 1 until input A equals 1, then output D equals 1 and
C equals 0.
7. If inputs A and B are simultaneously equal to 1 then output C equals 1 and D equals 0.

A B C D 1
1 0 0 0 1 A 0
2 1 0 1 0
3 0 0 1 0 B
4 0 1 0 1
C
5 0 0 0 1
6 1 1 1 0 D
7 0 0 1 0
8 1 1 1 0 t
1 2 3 4 5 6 7 8

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 5.1 Binary Logic Diagrams for Process Operations 887

TABLE 5.1a (continued)

Instrument and Control System Functional Diagramming Symbols-Binary Logic, Memory, and Time Functions (Proposed for the next
revision of ISA S5.1 (now ANSI/ISA-5.01.01) at the time of this writing)
Symbol Definition

No Truth Table Graph

12 1. Reset dominant memory (Ro Dominant).

A S C 2. Output C and D are always opposite.
B R0 D 3. If input A equals 1 then output C equals 1 and D equals 0.
4. If input A changes to 0 output C remains 1 until input B equals 1, then output C equals 1 and
D equals 0.
5. If input B equals 1 then output D equals 1 and C equals 0.
6. If input B changes to 0 output D remains 1 until input A equals 1, then output D equals 1 and
C equals 0.
7. If inputs A and B are simultaneously equal to 1 then C equals 0 and D equals 1.

A B C D 1
1 0 0 0 1 A 0
2 1 0 1 0
3 0 0 1 0 B
4 0 1 0 1
C
5 0 0 0 1
6 1 1 0 1 D
7 0 0 0 1
8 1 1 0 1 t
1 2 3 4 5 6 7 8

13 1. Pulse duration, fixed.

2. Output O changes from 0 to 1 and remains 1 for prescribed time duration t when input I
I t PD O
changes from 0 to 1.

NONE 1
I 0

O
t t

14 1. Off time delay.

2. Output O changes from 0 to 1 when input I changes from 0 to 1.
I t DT O
3. Output O changes from 1 to 0 after input I changes from 1 to 0 and has been equal to 0 for
time duration t.

NONE
1
I 0

O
t t

2006 by Bla Liptk

888 PLCs and Other Logic Devices

TABLE 5.1a (continued)

Instrument and Control System Functional Diagramming Symbols-Binary Logic, Memory, and Time Functions (Proposed for the next
revision of ISA S5.1 (now ANSI/ISA-5.01.01) at the time of this writing)
Symbol Definition

No Truth Table Graph

15 1. On time delay.
2. Output O changes from 0 to 1 after input I changes from 0 to 1 and I remains 1 for
I t GT O
prescribed time duration t.
3. Output O remains 1 until:
R
a. Input I changes to 0.
b. Reset R changes to 1.

NONE 1
I 0

O
t t t

R
t

16 1. Pulse duration, variable.

2. Output O changes from 0 to 1 when input I changes from 0 to 1.
I t LT O
3. Output O changes from 1 to 0 when:
a. Input I has equaled 1 for time duration t.
R
b. Input I changes from 1 to 0.
c. Reset R changes to 1.
NONE
1
I 0

O
t t t

R
t

the use of the binary symbols given in Appendices A, B, and
C are direct extracts from and utilize the current Standard
ANSI/ISA-S5.2-1976(R1992).
Binary logic switching and memory functions are used
in analog or sequential control schemes. In truth tables and
graphs, Logic One (1) is true and Logic Zero (0) is
false.
APPENDIX A: GENERAL APPLICATION EXAMPLE
A1. Introduction
This example uses a representative process whose instru-
ments are denoted by the symbols of ANSI/ISA-S5.1-1984
(R 1992) (ANSI Y32.20-1975). The process equipment
symbols are included only to illustrate applications of
instrumentation symbol. The example is not a part of
Standard S5.2.
A2. Simplified Flow Diagram
Figure 5.1b provides the flow sheet representation of the logic
involved in a tank filling operation. A written explanation of
the various symbols follows:
A3. Word Description
A3.1 Pump Start Feed is pumped into either tank A or tank
B. The pump may be operated manually or automatically,
selected manually on a local maintained output select switch,
HS-7, which has three positions: ON, OFF, and AUTO. When
the pump is operating, red pilot light L-8A is on; when not
operating, green pilot light L-8B is on. Once started, the pump
continues to operate until a stopping command exists or until
the control power supply is lost.
The pump may be operated manually at any time provided
that no trouble condition exists: The suction pressure must not
be low; the seal water pressure must not be low; and the pump
motor must not be overloaded and its starter must be reset.

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 5.1 Binary Logic Diagrams for Process Operations 889

I I
1 1

LSH LLH LSH LLH

3 3 4 4

I I
Tank A 1 Tank B 1

ZSL ZSH ZSL ZSH

1 1 2 2

Air supply I HS Air supply HY

1 1 2
FO S FO S
FO FO
HV HY HV I
Vent Vent
1 1 2 1

HS
HS I 2
7 1

Seal water Feed pump

PT PSL I
6 5 1
Feed
PSL PI
6 6

PAL
6

FIG. 5.1b
Tank filling operation-simplified flow diagram.

In order to operate the pump automatically, all the fol-
lowing conditions must be met:
A3.1.1 Board-mounted electric momentary-contact hand
switches, HS-1 and HS-2, start the filling operation for tanks
A and B, respectively. Each switch has two positions, START
and STOP. START de-energizes the associated solenoid valves,
HY-1 and HY-2. De-energizing a solenoid valve causes it to
go to the fail-safe position, i.e., to vent. This depressurizes the
pneumatic actuator of the associated control valves, HV-1 and
HV-2. Depressurizing a control valve causes it to go to the
fail-safe position, i.e., to open. The control valves have asso-
ciated open-position switches, ZSH-1 and ZSH2, and closed-
position switches, ZSL-1 and ZSL-2.
The STOP position of switches HS-1 and HS-2 causes
the opposite actions to occur so that the solenoid valves are
energized, the control valve actuators are pressurized, and
the control valves close.
If starting circuit power is lost, the starting memory is
lost and the filling operation stops. The command to stop
filling can override the command to start filling.
To start the pump automatically, either control valve HV-1
or HV-2 must be open and the other control valve must be
closed, depending on whether tank A or tank B is to be filled.
A.3.1.2 The pump suction pressure must be above a
given value, as signaled by pressure switch PSL-5.
A.3.1.3 If valve HV-1 is open to permit pumping into
tank A, the tank level must be below a given value, as signaled
by level switch LSH-3, which also actuates a board-mounted
high-level pilot light, LLH-3. Similarly, high-level switch,
LSH-4, permits pumping into tank B, if not actuated, and
actuates pilot light LLH-4, if actuated.
A.3.1.4 Pump seal water pressure must be adequate, as
indicated on board-mounted receiver gage, PI-6. This is a non-
interlocked requirement that depends on the operators attention
before the operation starts. Pressure switch, PSL-6, behind the
board, actuates the board-mounted low-pressure alarm, PAL-6.
A.3.1.5 The pump drive motor must not be overloaded
and its starter must be reset.
A.3.2 Pump Stop The pump stops if any of the following
conditions exists:

2006 by Bla Liptk

890 PLCs and Other Logic Devices

A.3.2.1 While pumping into a tank, its control valve
leaves the fully open position, or the valve of the other tank
leaves its fully closed position, provided that the pump is on
automatic control.
A.3.2.2 The tank selected for filling becomes full, pro-
vided that the pump is on automatic control.
A.3.2.3 The pump suction pressure is continuously low
for 5 seconds.
A.3.2.4 The pump drive motor is overloaded. It is imma-
terial to the process logic whether or not the memory of the
pump motor overload is retained on loss of power in this
system because the maintained memory that operates the pump
is defined as losing memory on loss of power, and this by itself
will cause the pump to stop. However, an existing motor-
overload condition prevents the motor starter from being reset.
A.3.2.5 The sequence is stopped manually through HS-1
or HS-2. If stop and start commands for pump operation exist
simultaneously, then the stop command overrides the operate
command.
A.3.2.6 The pump is stopped manually by HS-7.
A.3.2.7 The pump seal water pressure is low. This con-
dition is not interlocked and requires manual intervention to
stop the pump.
A4. Logic Diagram
The equivalent of the flow sheet representation shown in
Figure 5.1b is the logic diagram provided in Figure 5.1c.
Comments on the logic diagram for Interlock 1 described
in Figure 5.1c:
1. The diagram may be simplified by using general notes
(GN) for a project, especially for repetitive items. For
example, the operating light for the pump may be
omitted from the diagram by using a general note that
states: All pumps have red and green pilot lights to
denote that the pump motors are operating or not oper-
ating, respectively.

HS Pump on
LLH 7
3

LSH Tank A
3 Level high Pump on OR
HS
7 auto

HS Start lling Open valve HV A A

LS 1 Red
1 Tank A (Routine 1)
**
L
ZSH Valve 8A
1 open Filling permissive
OR
Exists* LS Operate pump
HS Stop lling
1 Tank A Close valve HV
(Routine 1) 2
Stop pump
**
ZSL
Valve
2 Green
closed L
8B
HS
HS Start lling Open valve HV Pump o
LS 7
2 Tank B (Routine 1) 2
**
ZSH OR
Valve
2 open
PSL Pump suct. DI
HS Stop lling press. low 5s
5
2 Tank B Close valve HV
A
(Routine 1) 1
**
ZSL Valve Pump motor overloaded NS
1 closed R

Reset pump motor starter *The words Filling permissive exists only exemplify the use
LSH Tank B of a status summary statement. The statement is not
4 Level high mandatory but may be added if it is helpful. (See section 3.6)
LLH Pump **This information Solenoid
4 PSL steal water PAL describing solenoid, Control valve
valve
6 press. low 6 actuator and port HY-1 HV-1
design is required
for detailed design HY-2 HV-2
work Actuator Port
Open valve De-Energized Vented Open
Operation
Close valve Energized Pressurized Closed

FIG. 5.1c
Tank filling operation-interlock 1 logic diagram.

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 5.1 Binary Logic Diagrams for Process Operations 891

Operate A A
pump OR C A C
(GN-1) B
OR

As another example, the motor lockout detail

FIG. 5.1e
This symbology is not recommended to be used for depicting mem-
Pump motor Stop ory loss due to power supply failure.
overloaded S pump
R
Reset motor 3. The logic diagram emphasizes the operating logic of
starter the process by not detailing the system mechanism for
opening and closing the control valves. Thus, this
information is provided by means of Routine 1, which
will commonly be simplified by referring to a general may apply to similar hardware of an entire project as
note that states: The motor starter locks out when well as to Interlock 1. However, if it is desired to make
tripped, the diagram more self-contained by including hard-
Thus: ware functions, this can be done as follows, using an
excerpt from the diagram as an example:
Stop
pump Open valve HV
(GN-2) (routine 1) 1

2. The memory function that keeps the pumps in operation Alternative:

may be, but is not necessarily, provided by a circuit (Deenergize HY-1)
breaker for the pump motor. The other maintained- (Vent HV-1)
HV
memory function in the diagram may be provided by Open valve
1
pneumatic or electric latching relays or other types of
hardware. This illustrates the essentially hardware-free
nature of the operational logic portion of the diagram APPENDIX B: COMPLEX TIME-ELEMENT EXAMPLE
and the emphasis on logic function.
B.1 Word Description
2. Logic diagram For an illustration of the logic equivalent of the word descrip-
Air tion (Figure 5.1d), assume a process operation, as follows:
ow If air flow becomes high and is so sustained for 4 seconds,
high 4
Close vent then open vent, actuate alarm, and initiate heating by east
S and west heaters. If heating by east heater is initiated, the
Open vent
heater goes on for 2 seconds, off for 1 second, and on again
Alarm for 4 seconds, regardless of whether the air flow remains high
Auxiliary
while this is occurring. If heating by west heater is initiated,
10 blower then heater goes on for 20 seconds, off for 18 seconds, and
S operation on for 40 seconds, but only if the air flow remains high while
permitted this is occurring.
If high flow of air is sustained for 10 seconds, stop the
auxiliary blower if it is running.
East
4 2 1 4 When air flow is no longer high, close the vent and permit
heater
S S S S
on the auxiliary blower to be restarted and the alarm to be reset.

APPENDIX C: LOSS OF POWER SUPPLY FOR MEMORY

4 30 18 40 West
heater
S S S S There are no symbols in the new Table 5.1a from Draft 4 of
on
the new proposed Standard to indicate how to symbolize mem-
FIG. 5.1d ories that are lost in the event of loss of power supply. The use
Logic diagram equivalent of the word description. of a logic feedback to symbolize a memory is deprecated.
Thus, the symbolisms shown in Figure 5.1e shall not be used:

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892 PLCs and Other Logic Devices

Bibliography Draft 4 of ISA Draft 5.01.01, Instrumentation Symbols and Identification,

Research Triangle Park, NC: ISA, 2000.
International Electrotechnical Commission Recommendation, Publication
American National Standards Institute Standard Y32.14-1973, Graphic
117-15, Binary Logic Elements, 1972.
Symbols for Logic Diagrams (Two-State Devices), 1973.
National Electric Manufacturers Association Standard ICS 1-103, Static
American National Standards Institute Standard X3.5-1970, Flowchart
Switching Control Devices.
Symbols and Their Usage in Information Processing, 1970.
National Fluid Power Association Standard T.3.7.68.2, Graphic Symbols
ANSI/ISA-S5.2-1976 (R 1992), Binary Logic Diagrams for Process Oper-
for Fluidic Devices and Circuits.
ations, reaffirmed July 13, 1992.

2006 by Bla Liptk