Beruflich Dokumente
Kultur Dokumente
Digital Electronics
B. Mazhari
Dept. of EE, IIT Kanpur
172
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B. Mazhari, IITK
Clock cycles per instruction: CPI
Instruction cycles
LDA 5020 13
ADD B 4
MVIB,20 7
MOVB,M 7
Call 5020 18
RET 10
SPHL 6
LHLD 16
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B. Mazhari, IITK
Instruction pipelining to improve CPI
Performance = IPCfclk
1976, 8085 Tr~6500
~(1/7) x 3~0.5 MIPS 1994, Intel Pentium
~1.88 x 100=188 MIPS
Tr~3M
1. MOV B, M Fetch Decode Execute Cache~16kb
2. RLC
Fetch Decode Execute
3. MOVC,A
Fetch Decode Execute
CPI~1
175
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B. Mazhari, IITK
Logic vs DRAM Memory delay
60% per year
Borker, future of mp
176
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B. Mazhari, IITK
Logic vs DRAM delay
CPU
DRAM
MVI B, 35H
Loop 2: MVI C,FEH
CPU SRAM DRAM Loop1: DCR C
Cache
JNZ Loop1
DCR B
2ns JNZ Loop2
100ns
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B. Mazhari, IITK
Multi-level Cache
L1
d-Cache L3
CPU L2 i-Cache
Cache main
R L1 memory
i-Cache
1
3 10 DRAM
40
Latency:
180 cycles
178
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B. Mazhari, IITK
~8 billion units sold in 2013
Microcontroller
4K ROM
128 bytes RAM
4 8-bit ports
2 timer counters.
8051
179
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B. Mazhari, IITK
Logic Synthesis
S0 a b c d
R1 a R3 c LD5 LD1 LD3
R2 b R4 d R5 R1 R2 R3 R4
LD2 LD4
S1 Sel1
Sel0 Mux1 Mux2 Sel2
R5 R1 + R 2
S2
R5 R5 + R 3
Adder
S3
R5 R5 + R4
180
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B. Mazhari, IITK
Boolean expression Gate netlist
Minimization
Two level
Multi-level
Technology mapping
181
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B. Mazhari, IITK
Area Minimization
182
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B. Mazhari, IITK
Delay Minimization
K-map : xy x y x
186
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B. Mazhari, IITK
KMAP
xy x y x
Q1Q0
x 0 0 0 1 1 1 1 0
0 1 0 0 1
1 0 1 0 1
D1 = Q1 Q0 + x Q0 + x Q1 Q0
187
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B. Mazhari, IITK