Printed Circuit Board Failures

Causes and Cures Webinar

Bob Willis
bobwillis.co.uk

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Bob Willis
Bob Willis has been involved with the introduction and implementation of lead-free process technology for the last seven years.
He received A SOLDERTEC/Tin Technology Global Lead-Free Award for his contribution to the industry, helping implementation
of the technology. Bob has been a monthly contributor to Global SMT magazine for the last six years. He was responsible for co-
ordination and introduction of the First series of hands-on lead-free training workshops in Europe for Cookson Electronics during
1999-2001. These events were run in France, Italy and the UK and involved lead-free theory, hands-on paste printing, reflow,
wave and hand soldering exercises. Each non commercial event provided the first opportunity for engineers to get first hand
experience in the use of lead-free production processes and money raised from the events was presented to local charity. More
recently he co-ordinated the SMART Group Lead-Free Hands On Experience at Nepcon Electronics 2003. This gave the
opportunity for over 150 engineers to process four different PCB solder finishes, with two different lead-free pastes through
convection and vapour phase reflow. He also organised Lead-Free Experience 2, 3 + 4 in 2004-2006.

He has also run training workshops with research groups like ITTF, SINTEF, NPL & IVF in Europe. Bob has organised and run
three lead-free production lines at international exhibitions Productronica, Hanover Fair and Nepcon Electronics in Germany and
England to provide an insight to the practical use of lead-free soldering on BGA Ball Grid Array, CSP Chip Scale Package, 0210
chip and through hole intrusive reflow connectors. This resulted in many technical papers being published in Germany, USA and
the United Kingdom. Bob also defined the process and assisted with the set-up and running of the first Simultaneous Double
Sided Lead-Free Reflow process using tin/silver/copper for reflow of through hole and surface mount products.
Bob also had the pleasure of contributing a small section to the first Lead-Free Soldering text book Environment - Friendly
Electronics: Lead-Free Technology written by Jennie Hwang in 2001. The section provided examples of the type of lead-free
defects companies may experience in production. Further illustrations of lead-free joints have been featured in here most recent
publication Implementing Lead-Free Electronics 2005. He has helped produce booklets on x-ray inspection and lead-free
defects with DAGE Industries, Balver Zinn and SMART Group

Mr Willis led the SMART Group Lead-Free Mission to Japan and with this team produced a report and organised several
conference presentations on their findings. The mission was supported by the DTI and visited many companies in Japan as well
as presenting a seminar in Tokyo at the British Embassy to over 60 technologists and senior managers of many of Japans
leading producers. Bob was responsible for the Lead-Free Assembly & Soldering "CookBook" CD-ROM concept in 1999, the
worlds first interactive training resource. He implemented the concept and produced the interactive CD in partnership with the
National Physical Laboratory (NPL), drawing on the many resources available in the industry including valuable work from NPL
and the DTI. This incorporated many interviews with leading engineers involved with lead-free research and process introduction;
the CD-ROM is now in its 3rd edition.
 Bob Willis currently operates a training and consultancy business based in England. Bob is a member of the SMART Technical Committee.
Although a specialist for companies implementing Surface Mount Technology Mr Willis prov ides training and consultancy in most areas of
electronic manufacture. He has w orked w ith the GEC Technical Directorate as Surface Mount Co-Coordinator for both the Marconi and GEC
group of companies and prior to that he w as Senior Process Control Engineer w ith Marconi Communication Systems, where he had w orked
since his apprenticeship. Follow ing his time w ith GEC he became Technical Director of an electronics contract manufacturing company
w here he formed a successful training and consultancy division.

As a process engineer, he w as involved in all aspects of electronic production and assembly involv ed in setting up production processes and
ev aluating materials; this also inv olv ed obtaining company approval on a w ide range of Marconi's processes and products including printed
circuit board manufacture. During the period w ith Marconi, ex perience was gained in methods and equipment for env ironmental testing of
components, printed boards and assemblies w ith an interest dev eloped in many areas of defect analy sis. Over the last 15 y ears he has been
inv olv ed in all aspects of surface mounted assembly , both at production and quality lev el and during that time has been inv olv ed in training
staff and other engineers in many aspects of modern production.

Ov er the past few y ears Mr. Willis has trav elled in the United States, Japan, China, New Zealand, Australia and the Far East looking at areas
of electronics and lecturing on electronic assembly . Mr. Willis w as presented w ith the Paul Eisler aw ard by the IMF (Institute of Metal
Finishing) for the best technical paper during their technical programmes. He has conducted SMT Training programs for Tex as Instruments
and is currently course leader for Reflow and Wav e Soldering Workshops in the United Kingdom. Mr Willis is an IEE Registered Trainer and
has been responsible for training courses run by the PCIF originally one of Europe's largest printed circuit associations. Bob has conducted
w orkshops with all the major organisations and ex hibition organisers World Wide and is know n for being an entertaining presenter and the
only presenter to use unique process v ideo clips during his w orkshops to demonstrate each point made.

Mr. Willis w as Chairman of the SMART Group, European Surface Mount Trade Association from 1990-94 and has been elected Honorary
Life President and currently holds the position of SMART Group Technical Director, he also w orks on BSI Standards Working Parties. He is a
Fellow of the Institute Circuit Technology , an NVQ Assessor, Member of the Institute of Quality Assurance and Society of Env ironmental Test
Find out more at: Engineers. Bob Willis currently w rites regular features for AMT Ireland, Asian Electronics Engineer and Circuits Assembly the US magazine.
Bobwillis.co.uk He also is responsible for w riting each of the SMART Group Charity Technology reports, which are sold in Europe and America by the SMTA
to raise money for w orthy causes. Bob ran the SMART Group PPM Monitoring Project in the United Kingdom supported by the Department of
Trade and Industry . He w as coordinator of the LEADOUT Project for SMART Group. LEADOUT w as one of the largest EU funded projects,
currently he is coordinating European projects TestPEP, uBGA and ChipCheck

Printed Circuit Board Failures Causes & Cures Webinar

Through hole plating failures

CAF contamination shorts
PCB Delamination
Nickel/Gold Black pad & Black Tar
Inner layer separation
Solder mask cracking
Outgassing
Need for product specifications
Auditing a PCB supplier
PCB Manufacturing Reference Books

PCB Manufacturing Reference Books

 IPC Specification Documents

IPC 600 F

IPC Specification Documents

Specifications for solderable surface finish

Printed Circuit Board Defects

Printed Circuit Board Defects

 Plated Through Hole Manufacture
Dr Paul Eisler credited with making the first PCB

Printed Boards were commonly used after World War II

During 1950 - 1960s single sided boards were used

Through Hole Plating developed during late 1960s

Multi Layers boards were developed during the 1970s

Plated Through Hole Manufacture

PCB

PCB

PCB
 Plated Through Hole Manufacture

PCB

PCB

PCB

Plated Through Hole Manufacture

Blind via hole

 Plated Through Hole Manufacture

Buried via hole

Initial Supplier Audit Requirements

Supply a full package of information electronically or hard copy

five days before any visit, this should include:

You should obtain general information on the company, location,

map and contact details

List of production equipment and capability for the products being

proposed for fabrication

List of production process capabilities and processes available on-

site, any off site services should be confirmed
 Initial Supplier Audit Requirements

Design requirement/customer DFM Report for new builds

Fabrication flow path for each type of circuit being considered

List or Inspection/process checks conducted for the build

List of training modules production and quality staff attend

Copy of technology roadmap and its introduction time scales, good to

ask for one a couple of years before the date of visit

Supplier Audit Report

Procure a sample batch of the new circuit board design

Assess the quality of the samples to relevant standards and run

through assembly process as part of a NPI build

Produce a report to compare suppliers strengths & weaknesses

Alternatively highlight issues at the end of the visit

 Traditional Sulphur Free Tissue Paper

Outer packaging to provide protection to the boards and tissue paper

interleaved between boards to prevent surface damage to solder mask, legend
ink and solder pad surfaces. These techniques are still used but vacuum
sealed is the most common standard offered

Pink Poly or Other Packaging

 Moisture Barrier Bag

Bags available with and without zip lock.

Also the barrier material can be provided
in roll format with a sealing unit to
produce custom sized bags

PCB Mechanical Inspection

 PCB Mechanical Inspection

Measurement of bow and twist on a flat surface

PCB Mechanical Inspection

Copper through hole measurement using eddy current principle, typical through
hole thickness would be 25 - 30um of copper
Optical Inspection Systems

Optical Inspection Systems

 Adhesion Testing (Tape Test)

Adhesion Testing (Tape Test)

Tape testing is all about the bond to the base material, normally solder mask and not necessarily a test of the
coating materials performance. Different solder masks formulation may give varying results ASTM D3359
 Solder Mask Thickness

Solder Mask Thickness

Agree specification with supplier for mask thickness and variation on the surface of the panel
 Solder Mask Undercutting

Printed Board Markings

Date of PCB manufacture will be marked on the surface of the board in the legend, formed in the solder mask or on the copper surface
 Multilayer PCB Manufacture
Microsection example of
through hole copper plating
and tin/lead plating on the knee
of the hole

The original copper laminate

foil is also visible

Multilayer PCB Manufacture

Microsection of surface
conductor copper foil, copper
plating and tin/lead plating
 Multilayer PCB Manufacture
Microsection of inner layer
conductor foil copper plating
connection in the through hole

Multilayer PCB Manufacture

Microsection showing blind and
buried via holes with
connection to the inner layer
 Plated Through Hole Manufacture

Plated Through Hole Manufacture

Copper metallisation on
through hole prior to copper
plating

Copper through hole

metallisation inspection using
the back light test for coverage
 X-Ray Inspection

X-Ray Non Destructive Inspection

 X-Ray Non Destructive Inspection

Blind Via PCB Examination In Process

Close up of the PCB surface copper after drilling and prior to metallisation to make the interconnection to the capture pad
 Via Too Deep to Image Successful

SEM examination would also not be possible due to the depth of the hole. Most PCB produces also dont have SEM

Grind Down PCB Sample Closer to Pad

Close up of the PCB surface copper after drilling and prior to metallisation to make the interconnection. The sample has been
ground down to reduce the step height between the capture pad and the top of the lam inate, it is possible to grind down closer to
the copper pad surface
 Ultrasonic Clean Sample in IPA

Surface of the Capture Pads ay High Magnification

Testing Blind Via Hole Quality in Printed Board Manufacture

Minimum tools required

Customers defective boards
Grinding wheels
Very fine scalpel blade
Very good quality tweezers
Magnification low and high
Good deal of patience

Printed Board Assembly Featuring Blind Via Holes

If open circuits are suspected on blind

vias this is a way to look at the interface
of the capture pad and copper plating. Grind the PCB
Often there is great debate on what is to just below
good and bad, failure or not. Often it is the capture pad
difficult to see the interface or conduct
analysis of the interfaces.
Printed Circuit Board Featuring Blind Via Holes
Printed circuit boards could be tested prior to assembly using
standard thermal shock tests defined in international standards.
The photograph shows the track and capture pads through the
laminate as we start to grind to the back of the pad.

Grind the PCB

to just below
the capture pad

Printed Board Assembly Featuring Blind Via Holes

Capture pad & track

can then be peeled
from the base of
the via hole
The image shows the track and pad with thin layer of resin still below
the copper foil prior to peeling the copper from the laminate and via.
With care you can still continue to grind with 800-1000 grit paper
to just touch the copper surface which reduces the strain on the
copper during peeling, you must not expose the base of the via barrel
 Printed Board Assembly Featuring Blind Via Holes

Capture pad & track

If a test board was used for this can then be peeled
assessment it would be possible to Away from the base
of the via hole
use a bond tester to measure peel
force of the track and its separation force

Blind Via Connection to Inner layer

Bottom of via hole 0.010 Via hole capture pad 0.020

Examples of Via & Capture Interfaces

Testing Blind Via Hole Connection

The following is a simple concept for a test coupon for quality control of
blind via holes. Daisy chain pattern of blind vias tested for continuity
 Testing Blind Via Hole Connection

Daisy chain pattern of blind vias tested for continuity, if they fail after some form of stress like
temperature cycling, bending etc. they can be tested visually using back microsection techniques
outlined previously. The length of the capture pad or pad to pad separation should be as long as
possible to allow cutting and peeling of the track. The width of the track should be equal to or
larger than the via capture pad top aid peeling and avoid breaking at the pad to track interface

Optical Examination of Via Connection

With a true plated interface
between the via and pad. M arks
on both surfaces should
correspond after pad
separation.

Grind sample board up to the base of the capture pad, peel off the capture pad between
blind via holes. Examine the via and capture pad interfaces. Depending on the design of
the test coupon it would also be possible to conduct peel tests on via holes
 Blind Via Test Board Option
It may be possible to make a test board from etched double sided laminate.
Laser drill the blind vias through etched apertures in the copper foil on side one of
the board down to the back of the copper. Then peel the copper off for inspection.
In this way no grinding of the board is required.

What is Pad Cratering

Pad cratering is the partial or complete separation of the copper termination pad, typically seen on area array
designs after mechanical strain has been applied. This failure is different to pad lifting when heat is applied
during rework. However pad cratering has been reported on board assemblies with large BGA packages directly
after reflow soldering and assumed to have occurred during cooling

Pad lifting has also been seen on boards which have been reworked but this may be due to pop corning of
devices. In this case the copper pads were retained on the solder sphere and separated from the PCB. It is
easier to see pad cratering on area array devices with optical inspection than x-ray although pad separation and
track breaks have been investigated by the author and Dave Bernard with x-ray in one of their technical papers
 PCB Pad Cratering

Different examples of pad separation from the PCB and component package surface

PCB Pad Cratering

Copper needles provide greater surface adhesion to the laminate surface but this in turn
may impact electrical performance of the laminate on multilayer designs. Its a balance
between mechanical and electrical performance. The hardness of the epoxy and the
solder alloy increases the possibility of separation
 Possible Cratering Causes
Pad cratering seen with lead-free, less ductile alloy
Can be related to the PCB laminate, harder epoxy
Commonly seen during flex or drop testing
Difference in package expansion rates, possible impact of
reflow and cooling steps
Does not always results in open circuit failure!!

PTH/Surface Mount Pad Surface

Silver

Tin
 PTH/Surface Mount Pad Surface

Nickel gold pad

Copper OSP Organic Surface Protector

PTH/Surface Mount Pad Surface

Solder Levelled
Surface Finish Thickness Measurement

PTH/Surface Mount Pad Surface

Nickel/gold foot is an unusual formation that
can lead to shorts or reduction in surface
insulation. The photograph shows a gold
hallow around the surface mount pads. Nickel
has plated onto the surface of the laminate
and the edge of the solder mask. This has
also allowed gold to coat the surface of the
nickel reducing the design gap

Microsectioning of the nickel/gold foot clearly

shows the plating defect. The nickel can be
seen to extend from the bottom of the pad
across the laminate and up the solder mask
wall
Bob Willis - Texas Instruments Workshop

Solder wicking

Three examples of solder wicking;

On the left due to incorrect process parameters in the 80s with vapour phase reflow

In the centre due to slow wetting on copper OSP. The copper surface had been exposed to a wash
off operation which impacted the solderability of the PCB.

The example on the right is on a nickel gold board due to poor wash off practices on a night shift in
high volume production

Solderability Testing with Wetting Balance

Wetting Balance Solderability Testing

Wetting Balance Solderability Testing

 Solder Spot Wetting Test Pattern

In the design we use six 0.020" parallel tracks on a 0.040" pitch, track and gap are 0.020 and are
approximately 0.900" long. The gang solder mask im age has a clearance of 0.010 around the
pattern. The pattern should be placed on both sides of the board or both sides of a multi panel on the
break-out scrap area

Solder Spot Wetting Test Pattern

 Solder Spot Wetting Test Pattern

CSP CSP

CSP CSP

+ +

BGA BGA BGA BGA

CSP CSP

CSP CSP

+ +

BGA BGA BGA BGA

Impact on PCB Solder Finishes

Images

from NPL Lead-Free Workshops

 Solder Paste Stencil Pattern

Solder paste pattern consists 21 0.5mm (0.020) square apertures, can have slight
rounds on corners. The gap between the apertures increased from 0.16 to
1.16mm in 0.05mm increments
 Tin Whiskers

The images above show tin whiskers on the surface of a plated through hole printed circuit board coated with tin. The boards were produced and
shipped to a manufacturing site in Europe and, when examined prior to assembly, found to have whisker growth. Tin has become popular on printed
boards as one of the alternative coatings, tin has also become the finish of choice in the component manufacturing industry. However, many people
have shown concerns over the formation of whiskers.

There has been a considerable amount of work and technical articles produced on whisker formation and potential for failure in electronics. There is still
a lot of work being undertaken around the world on this subject. The reason is we still do not have guaranteed whisker free products or the process
where the chemistry is being used is not being maintained correctly. If you follow guidelines on designing a whisker free process, use materials that
should not form tin whiskers, somehow they still appear. This problem is not specifically a lead-free issue as it has been around for years as a possible
problem. The increasing use of tin as a component finish and printed board alternative coating has highlighted the potential for failure. Organisations like
NEMI and JEDEC have provided guidelines on what causes whisker formation, ways of accelerating testing for whisker formation and preventative
strategies

Current understanding is tin whiskers form due to stress formed in the plating. This causes tin filaments or single crystals of tin, commonly 2-5 microns
long to be forced out from the surface of the plating during the life of the product. To reduce the possibility of formation engineers have looked at baking
to reduce stress, changing or increasing the thickness of barrier layers. This is the third example of whiskers examined on different products, each
theoretically should not have occurred based on current recommendations and specifications. The other two are related to RF shielding

Test Method for Measurement of the Propensity for Conformal Coatings to Inhibit Tin Whiskering
Martin Wickham and Christopher Hunt, MAT28, December 2008

Testing PCBs & Components with XRF

Engineer measuring surface finish thickness on PCB pads

 Potential Process Failures
Copper dendrites can cause intermittent product failures
during product operation. Copper ferns grow from one
electrode to another in the presence of a moisture layer on
the surface of the board

White residues caused by the use of an incorrect cleaning process

or chemistry. The flux is not soluble in the chosen cleaning
process or some other reaction has caused the flux to become
insoluble

Printed board failure due to a conductive short formed on inner

layers of a multilayer boards generally referred to as a CAF failure.
CAF stands for Conductive Anodic Filamentation and related to
the materials and conditions in side the board

Potential Process Failures

Printed board failure due to a conductive short

formed on inner layers of a multilayer boards
generally referred to as a CAF failure. CAF -
stands for Conductive Anodic Filamentation
and is related to the materials and conditions
inside the board
 Microsection Inspection

Check position of plated through hole centre line during sectioning of the samples

Microsection Inspection
 Microsection Inspection

Microsection preparation requires experience and time there are no shortcuts if you want all the
information to allow correct interpretation of your results. Two examples of a plated through via
0.2mm after lead-free process trials and then temperature cycling of the board over 1000 cycles
must show up some changes

Blind Via Laser or Control Depth Drill

Microsection Inspection

Inner Layer Separation

 Ionic Contamination Measurement

Measurement of contamination on a board is also a matter of considering the total result, the total time and
the rate at which the contamination rises over time. Remember the ionic contamination can come from
soldering materials, the printed board surfaces, fabrication materials and other sources. Many people are
happy that the result shows it to be less than the specification limit

Printed Board Quality Control

Thermal shock testing with fluidised sand bath and water, left. Five cycles between
25degC & 260degC looking for change of resistance between the cycles. The
sample holder and measuring system is shown on the right
 Printed Board Quality Control

Plated through hole

Multilayer board

Close up of test samples prepared for thermal shock testing, the examples are a
PTH and a multilayer circuit. The fingers are used to make the connections in the
test fixture for immersion into the water and band bath

Printed Board Quality Control

Typical example of a crack forming at the knee of the hole on a plated through hole board during
testing. This would cause a change in resistance during the test
 Printed Board Quality Control

Two coupons after testing showing different degrees of cracking at the

knee of the hole. This would result in a change in resistance

SEM Examination

Industry example images of pads after stripping courtesy of Shipley

 Merlin Circuits Stripping Procedure
20 g / Litre DEGUSSA Gold Stripper 645 plus10 g / Litre Potassium Cyanide

Confirm the solution is appropriate for the suppliers nickel gold process chemistry
Use solution at room temperature

Stripping printed board gold samples to be conducted in a fume cupboard with suitable protective
clothing e.g. gloves, eye protection lab coat

0.06 to 0.08 microns of Immersion Gold will normally strip in 10 to 12 seconds

Take the sample board and gently move back and forth in the solution until the Nickel becomes
visible, quickly remove and rinse thoroughly in demin water and the waste collected for
appropriate disposal via authorised waste streams

Record time taken to strip the Gold and view Nickel surface under suitable magnification.

(It should be emphasized that the solution is highly toxic and only used by an experienced
technician. Under no circumstances should the cleaner be allowed to come into contact with
acids)

Pads Before/After Stripping

Examples of two surface mount pads before and after stripping, fast stripping time
indicated thin gold and a poor surface when inspected
Example Pads After Stripping
Blow Holes & Pin Holes in Solder Joints

Blow Holes & Pin Holes in Solder Joints

 Testing PCBs for Outgassing

Testing PCBs for Outgassing

The video clips show testing of a PCB in production for outgassing. Originally this was suggested
as a test method with some criteria based on the number of bubbles or rate of outgassing. One
engineer even built a machine for counting the bubbles

https://www.youtube.com/user/MrBobwillis
 Copper Pad Erosion with Lead-Free

Copper Pad Erosion

Although examples of copper erosion have been highlighted in the industry there is little evidence to date of this being an issue. In the case
of single sided boards the apparent erosion may have been due to preparation of the copper for OSP treatment. In this case copper is mildly
etched, excessive prep may have removed more copper around the pads as other areas of the tracking would be protected by the solder
mask. Where mechanical cleaning is used and incorrectly controlled the copper can be reduced around the hole leading to a apparent
copper reduction. Further investigation of the problem and the examples circulated in the industry will be further reviewed and where
appropriate further trials conducted.

It is interesting to note that the defects highlighted have not been shown to cause failures. At first examination we would consider them all
rejectable based on our existing knowledge of tin/lead joints. That knowledge is again not necessarily based on failures but the inspection
criteria for solder joints in circulation today. Perhaps we do need to re-look at some of the visual criteria we use in industry for lead-free?

Recent trials have been conducted on selective soldering systems with lead-free alloys. In this case where the boards did have a very thin
copper plating and been solder levelled with lead-free the copper removal was significant. After exposing the boards to a high temperature
during selective soldering for an extended time copper pads were full dissolved from the surface of the board. This is not typical and should
not occur when a sound plated layer is present in a well controlled lead-free assembly facility. However it does demonstrate what can
happen

Outgassing from PCB Via Holes

Oil being used on the surface of the vias and the sample board heated to sim ulate reflow . Even
with epoxy and copper plating outgassing can still occur during reflow soldering leading to
voiding under large packages
 Potential Process Failures
Copper dendrites can cause intermittent product failures during
product operation. Copper ferns grow from one electrode to
another in the presence of a moisture layer on the surface of
the board

White residues caused by the use of an incorrect cleaning

process or chemistry. The flux is not soluble in the chosen
cleaning process or some other reaction has caused the flux to
become insoluble

Printed board failure due to a conductive short formed on inner

layers of a multilayer boards generally referred to as a CAF
failure. CAF stands for Conductive Anodic Filamentation and
related to the materials and conditions inside the board

CAF Failure in PCB

 PCB Delamination

PCB Delamination

Company found delamination of boards in production after reflow soldering. Moisture in the board was
blamed for the failure but it was not the root cause. Moisture is in every board, baking does eliminate it
for a few hours but also has it disadvantages. A simple destructive examination was conducted on a
section of the board, the blister was cut with a sharp knife and the section removed from the surface of
the board. Looking at the copper surface it is clear that no bond had ever been made between the resin
and the copper. This was probably related to the copper preparation

PCB Delamination

PCB Delamination
Company found delamination of boards in production when using Thermount a non woven glass
laminate. Moisture in the board was blamed for the failure but it was not the root cause.

A simple destructive examination was conducted on a section of the board, the blister was cut with a
sharp knife and the section removed from the surface of the board. Looking at the copper surface it is
clear that no bond had ever been made between the resin and the copper. This could have been caused
by the copper preparation or the press cycle which is a higher temperature for this material.
PCB Delamination

Through Via Failure

Open Intermittent Circuit

Solder Mask Lifting

 Solder Mask Lifting

Printed Board Quality Control

Dye pen testing of solder mask

 Printed Board Quality Control

Dye pen testing of solder mask

Printed Board Quality Control

IPC-TM-650 2.4.27.2, called by IPC SM-840

4B-3B-2B-HB-F-H-2H-3H-4H-5H-6H
 Basic Printed Board Manufacture

Test board for the smallest chip

capacitors and resistors available
in industry today 03015 next size
down from 01005

NPL Process Defect Database

http://defectsdatabase.npl.co.uk/
NPL Process Defect Database

http://defectsdatabase.npl.co.uk/

NPL Process Defect Database

http://defectsdatabase.npl.co.uk/
NPL Process Defect Database

http://defectsdatabase.npl.co.uk/

Do you have any questions ?

https://www.youtube.com/user/MrBobwillis