1.

EMBITEL

1. How is various C, ASM, and SV are connected in the system. How do they understand or establish
synchronization between each of them. What is the mechanism behind all these?

2. What is the debug procedure followed in AMD. How verification engineers approach/debug any issue.

3. What all constructs used in OVM in the current projects?

2. TCS

Verilog Questions:

1. Have you heard of NBA blocks in Verilog, what is that?

2. Difference between: TASKS & FUNCTION

3. Can we write Task inside a function or can we write function inside a task?

4. Difference between Blocking & Non-blocking assignments. Where, which is used?

5. Regions in Verilog Expected answer: Active, In Active

6. What is race condition? How to avoid them?

7. a <= 1; a<=0; What is the output? Is this race condition?

System Verilog:

1. Explain the SV verification environment? Expected: Usual generators, drivers, monitors..

2. Explain Polymorphism. Give an example in terms of class.

3. How are drivers & generators connected; how does a driver interact with DUT. Expectations: Exact
explanation in terms of code

4. Arent mailboxes used between Drivers & DUT? What is the usage of Mailboxes?

5. How do you instantiate/connect different modules inside interfaces. Expectation: Coding details.

6. Coverages, Assertions questions.

7. Basic OVM concepts.

Project Related:

1. Whats the difference between: SOC v/s IP level verification.

2. What is the extra aspect which comes in SOC level apart from what is done in IP level?
 3. Explain packet structure in UART. What is that data packet comprises?

4. Explain Booting sequences.

5. ISR details & how it works.

6. Structure/Flow of any C Test cases.

7. What is the differences between functional & Code coverages? What is the significance of EACH?

8. Is that code coverage is sufficient for closure of any verification.

9. How does a module level TC varies from a system level test cases? What is added extra in that?

3. Wipro Technologies

1. Can we randomize a variable without declaring the variable as rand. If yes how to do it?

2. What are the SV constructs/OOPS concepts used in your current (BMS) project? Expectation:
Polymorphism, Inheritance..

2nd Round: Wipro Technologies

1. Write a clock generator code with period 5 ns (its not 10ns)? Also after few cycles of clock the clock
should be 0 for 50ns and then the generation should keep going normally I wrote initial forever
inside forever some external clock stop signal (wait for 50ns)& again forever continues.

2. Write a C function which takes an array of integers using pointer/reference, arrange/swap them and
gives back the array to calling function.

3. What are the differences between tasks & function in Verilog? Where, when, which is used?

4. AXI: A) What are the Burst modes, Cacheable property, protection modes, and Slave responses?B)
When the master gives size, length its pre know that when the last byte is transferred, but still why
there is a special signal called LAST? What is its significance?

5. I2C: How the two masters competing amongst them take control of Bus?
Once a Master establishes connection, Can another master steal control from established connection or
will it wait for the transaction completion? If so how is done? Definitely it cant wait wait till the 1st
master transfer completion since it may take unnecessary long time, other might be very urgent also.
4. INFOTECH SERVICES

Project Related:

1. Explain any project which youre comfortable with.

2. Given a DUT which is a black box: How would you verify? Brief all the Steps Will check the spec,
note down verification points, come up will test plan, test plan should be extensive, check if all covered.

3. AXI: What is the special feature of AXI protocol? Why specifically it is used? List the advantages &
all the features of AXI.

A) How wrap around address is calculated? Is there any specific calculations/procedure for it?
B) All funda questions: Error signals, responses, Burst modes.
C) Why we need to use fixed address mode Targeting address of a peripherals.

4. I2C: how two masters get the control of bus?

SYSTEM VERILOG:

1. What are the data types which allow all the four states he gave a clue to remember RIL Reg,
Integer, and Logic?

2. Similarly, data types which allow unsigned values BLR Bit, Logic, Reg.

3. What are the differences between logic & reg? Both are same except that logic to facilitate
multiple ways of driving. It can be used in both procedural (initial) & continuous (assign) statements.

4. Difference between program & modules almost both are same just for clarity purpose & also
major difference is in program block always are not allowed.
What is the work around for always in program block forever inside initial blocks.

5. Regions of execution in SV? Active, Inactive, NBA, prepone, postpone, bla bla.. some 7 stages.

6. Fork.. Join statements, different types of for.. join, differences.

VERILOG:

1. Task v/s functions.

2. Blocking v/s non-blocking statements.

General Questions:

1. What are all the tools used in the projects?

5. Tata Elxsi

Methodology:

1. What are the basic components of OVM Methodology?

2. How is the general TB structure in an OVM methodology?

3. What is the difference between SV & Verilog in terms of stages of simulation? In Verilog we
compile every time we load/run a new testcase (only alternative is if we happened to load memory/data
to be written via back door only this is to avoid entire compilation repetitively). But in SV we need not
have to compile everything every-time. TB is compiled once & done (needs to check on this).

But - C, ASM we need to compile everytime, no other go!!

4. AXI: A) What is the OUT OF ORDER v/s OUTSTANDING transaction?

B) What are the features of AXI special compared to other?

System Verilog:

1. OOPS concept of SV? Explain each of them with example:

2. Cant we do functional coverage in Verilog?

3. What are virtual functions? Why is it needed?

Project Related:

1. How the processor reads/understand the code?

2. Where is the test code loaded? How is it fetched? Its loaded in microprocessor memory.

3. How are the different components C, ASM, SV interacts/sync up with each other? Expln Mechanism

4. Assertions: Which is the most complex assertion you have developed?

5. Difference between IP & SOC level verifications?

Verilog:

1. What is `timescale? How it affects simulations?

2. What is #5? Which is the parameter for this 1st or 2nd parameter?

3. If you vary these What is the outcome?

4. How do you generate clock for the system?

6. Sasken Communications

Project:

1. Explain the project you have done SOC

2. What is BMS? How is the verification components developed?

3. What is the packet structure? How it can be generated?

4. Assume some DUT: how can we develop the environment? Expectations were regarding
environmental components like: Driver, Generator & checkers.

5. How is the connection between generator & driver? How are the data put exactly? What is the exact
flow?

6. Where is the checkers? Where are scoreboards inserted? How is it connected?

7. Who will call generators (if it is a separate module)? How is it taken across, exact flow details?

8. Where in which module checker (scoreboard) functional coverage block is inserted? How is it done?

9. How do you tap data is it @ input/output/immediately over the DUT or where else?

10. How did you write assertions for Pin Muxing block?

System Verilog:

1. Write a class for packet: 1.Good 2. Bad. In Good again subdivision: 1. Short. 2. Long. Again Short has 1.
Addr: 0-100. 2. Addr: 1:155. While Long(one hierarchy up): Address: 200 300. And Bad: Addr: FF

2. Write an assertion for two input, 2 select line, 4 output block.

3. How you write functional coverage for the above block? Where will you insert functional coverage in
the TB environment?

4. What are Mailboxes? How is it used? What are its applications?

5. Explain the complete SV project flow Drivers, generators, scoreboards. How are they connected?

AXI:

1. How do you write constraint for generating word-aligned address in AXI?

Miscellaneous:

1. What is clock stretching? Why is it done.

Ans: Check w.r.t I2C protocol.

2. How would you write a testplan for I2C bus Protocol?

3. How is the swapping between SV, C, ASM, Memory handlers done in a SOC.

7. ST Ericsson

Project:

1. Brief the project which you have worked on?

2. Give me the architecture of the testbench?

3. In Phoenix, if all the functions are in C, how will you display the result in log files? Intent: Log files
display works for Verilog $display, how will you pass data from C files to Verilog

4. SN2025, How did you ensured that timing parameters like break, ones, zero are detected in the
testbench? Since all are timing related, how did you ensured its correctness?

5. How is the scoreboard implementation done? If in C how?

6. What are the coverages block written, which is important in IP based & which is important in SOC?

Ans: SOC toggle coverage is important.

7. What is that clock gate assertions? How did you write?

Methodology:

1. How is UVM different from OVM? What is extra added in it?

2. How do you write sequences?

System Verilog:

1. Difference between Aspect Oriented w.r.t Spec man& OOPs oriented?

Miscellaneous:

1. What is State Machine? Write a SM for a BULB in a room, for each person swiping bulb should be on,
on all the members in the room logged out, bulb should be switched off.

Ans: So initial, reset state. S1 In count ++, stay in same state till IN, S2 on Out, count --, count = 0 go
to initial state & switch off

Second Round

Project:

1. Give the block diagram of the SOC Project.

2. Explain each and every minute details of the SOC.

3. Give me the boot up sequence of a typical SOC.

Ans: First the Control goes to RAM default location then look for the boot mode security if it satisfies
then only it proceed further (security ensured) clocks are determined 1st, PLLs are enabled and clock
generated thats how clock is supplied to every model all the peripherals are initialised via booting
peripheral (externally/internally) which its gonna be booted is determined by a specific register
read that boot up sequence and proceed control finally comes to the testcase where it behaves
exactly as per intent.

4. How the high level code is exactly understood by the processor? Are we feeding finally feeding ones &
zeroes or ASM code to processor.

Ans: High level code Machine code

5. Whats compiler, cross compiler, simulator differences.

6. Explain the testbench environment arround the SOC DUT, explain everything like BFM, how was the
scoreboard implemented.

7. Write a typical test case flow.

8. What is the difference between differnet types of coverages? Why do we need all of that?

Miscellaneous:

1. Write a state machine for detecting Red Blue Yellow objects coming in a trolley and once the
sequence in order pack it and keep aside.

2. How many states required, what is the minimum requirement. Bla..bla.. write pseudo code.

8. WaferSpace Technologies

Methodology:

1. How will you implement, multiple put (one drives USB packets & other PCIE packets) and what will
the implementation part contains? There can be only 1 put implementation, how will you manage two
put implementation? Case is Multiple drivers, how is the synchronization done between two?

Ans: Using TLM Fifo one method, something called put_** feature is there in UVM check out.

2. Why super.build () is used? If you extend the class, automatically everything comes in child class, what
is the need for including base class elements?

What happens if we dont include super.build()

Ans: Something related to overriding.

3. What is overriding? Where is it used?

System Verilog:

1. Difference between Queues & Dynamic array, which is used where?

2. If a packet with Addr, ID, data is there? Declaring packet pac[$]; how will you find a particular element
using ID = 0? Can you write a logic/function for doing so?

3. Write a randomization for packet class:

Packet good or bad; if good RD or WR; on Rd addr: 0-ff, WR - !Rd. If Bad - Idle 00, 04.

4. Functional coverage code for: two bits interrupt signals Int1 & Int2 generating from an interrupts.

Verilog:

1. Blocking and non-blocking difference?

2. What is the output of this & why so? Always @ (posedge clk); a = 1; a <= 0; $dispaly(a);

Miscellaneous:

1. Write a C program for generating fibinocci series.

2. Write a C program for exchanging the sequence order of an array.

9. Samsung

AXI:

1. Explain the wrap around address for a 16 bit data bus, if the start address is 0x1000; what would be
the WRAP4, WRAP8 address complete sequence of address if we are to transfer 32 bytes.

2. What is the address overlapping, overloading.

3. How the exclusive operation is set up, who is giving Exclusive command master/slave, how is it
coming out of this mode?

4. In exclusive mode, can another master try for another exclusive mode to another slave? Can it
attempt to same slave? Since AXI supports multi-master scenarios.

5. When will the response come in AXI? Is it for each transfer or burst, how is it?

6. How is the different ordering of response dealt within AXI?

7. Exclusive access is it for READ or WRITE transfer?

8. Explain data interleaving with proper example?

System Verilog:

1. Questions on Coverage, bins, how are you gonna get cross coverage.

2. What are SV Call backs? Where it used & what are its advantages?

3. Code vs Functional coverage?

4. What is the necessity/reason behind separate functional coverage & code coverage?

5. Why program block, which phase is it executed in the flow?

6. What all can be included in Interfaces?

7. What is the usage of Virtual Interfaces?

Miscellaneous:

1. Memory whose address are shorted, how are you going find the bug explain the verification
strategy.

Ex: If your writing & read from location 5; it will read from location 6 how are you gonna detect.

Ans: Something like keep writing & reading incremental data to incremental addresses.

Methodology:

1. What are Callbacks?

2, How to configure the TB mode? Where is it done?

3. Where is monitor getting data? Where is it sitting in entire TB?

4. Mailboxes: Is it there in OVM or just there in UVM?

5. Explain the verification components in the project.

6. How is the ports connected, what is the mechanism to connect.

10. Cypress Semiconductors

Project:

1. How would you conclude that you have done 100% feature extraction? How would you know that you
have extracted all features without missing out any?

2. 90% code coverage vs 100% functional coverage is it better? OR 90% functional coverage vs 100%
code coverage??

Ans: 100% functional coverage is the best.

3. In SOC: 100% toggle coverage is targeted, while other code, line, branch coverage is not be necessarily
100%

4. Difference between different coverage & what is what & where itsused?

5. What are the advantages of methodologies? How is it utilized?

11. Cadence Design Automation

System Verilog:

1. What are the different flavors of always block in SV?

2. Difference between Packed vs unpacked array?

3. Difference between dynamic array vs associate array?

4. What is enumerated datatypes, default datatype? Ans: Int

5. What is full case vs parallel case?

6. How to validate the frequency?

Project:

1. How you will decide the frequency @ which a system has to work?

12. Intel Telephonic

System Verilog:

1. Tasks having three inputs (A1, A2, A3), same task with (B1, B2, B3) and another (C1, C2, C3) all used in
fork...join; will it be a problem, if so what, how can it be resolved?

Ans: All the task being a static occupies same memory; if declare automatic it would be possible.

2. What is polymorphism? Where is it to be used?

3. What is Semaphore? How and where it is to be used?

4. What is stratified event queue? What is itssignificance?

Verilog:

1.What is the difference in $display & $monitor in blocking & non-blocking events?

Ans: Explain in terms of Stratified event queue

2. Difference between full case & Parallel case statements?

Project:

1. Though we run a simulation in verification, they might again fail in GLS, what are the possible
reasons?

Ans: Gate delays, X propagations, Latch inferences, coding error not following guidelines.

Miscellaneous:

1. What is the minimum Fifo Depth required for a simple fifo with 80writes/100 clock cycles & 8
reads/10 clock cycles. Assume same clock used & both read & write happens at the same time.

Ans: For 80 writes/ 100 clock cycles can be understood as lets say 1st 20 cycles nothing is done & the
remaining 80 clock cycles continuously 80 writes happen.

A) So with this anology: worst case scenario is:

1st 20 clock cycles no read as Fifo is empty. Next 80 cycles only 64 reads can happen & still 16 bytes are
remaining; so we need a minimum fifo depth of = 16 as a worst scenario.

B) Going further: 21 180 clock cycles continuous writes are happening, so what is fifo depth?

21 180 = 160 writes can happen, while only 64+64=128 reads can be done, so we need a minimum fifo
depth of 160-128 = 32

C) Needs to look @ the fifo depth standard equation.

2. 500 coins Head faced is placed on a table facing HEAD, 500 children are let in one by one... 1st child
flips down all the coins to tail, 2nd child flips whatever is existing for 2, 4, 8 even series, 3rd child flips 3,
6, 9. 4th child flips 4, 8, 12. 5th child flips 5, 10, 15 and so on while 500th child is left with only
flipping 500th coin. How many coins will be flipped in final?

Ans: Break the problem into simpler sample of 10 coins & 10 children. Mark the flips done by each child
to the corresponding corresponding coin.Coins with odd flips are the one who are gonna be TAILs &
coins with even multiples will remain HEAD oly. So by the end of 10 iterations..coins 1, 4, 9 are gonna be
TAIL rest all HEADS.

So, expanding to original sample. 1, 4, 9 are the squares 1square, 2 square, 3square..
Accordingly only square numbers are to be flipped. So, total of 22 coins will be flipped to TAIL rest all
will be HEADS.
Face 2 Faces:

Round 2:

1. Tell about yourself.

2. Realize EXNOR Gate using 4:1 Mux

3. Derive swapping of two variables without using external variable; using logical operators.

Clue: Derive on the lines of equations: A = A + B; B = A B; A = A B. Using EXOR/EXNOR operators.

4. Explain verification strategy/environment/plan that could be realized around a Synchronous FIFO.

5. Calculate the depth for FIFO: Read @ 20MHZ, Write @ 30MHz with 8 bit data size.

Round 3

1. Difference between structures & Union.

Example: struct {int a=20, int b=30} v/s union {int a=20, int b=30}. If you use display statements, what
would be displayed? How is the memory assigned?

2.Write a function which generates fibinocii; which called whenever should display next series.

Catch: here is there has to be STATIC variables declared inside function; such that any point of time its
called it should have values of last fib value displayed & previous to that also.

3. Explain I2C protocol.

4. Write assertions for I2C: Start (high Low) 8 data bits Ack.

Hint: you can neglect 8 bits mentioning as [7:0] time delay, need not have to track the bit values. If @ all
you have to know bits you gotta call another assertion separately.

Round 4

1. Explain the OVM environment of the project, with complete block diagram.

2. How were the test case coded? In detail

3. What is to be used between multiple clock domains. Ans: Not expected Buffer/Fifo but Synchronizer.
What is the digital circuit for that? How is it working?

4. Write a digital circuit realization of 000 111 using FSM, sort of up-counter using Flip-flops.

5. There is a memory model for 4GB, what type of data type you would use in SV? Dynamic array or
associate array or queue or static array? Which one is more appropriate and why is it best?
What if it is in C language/PLI?

6. Code coverage v/s Functional coverage?

7. If code coverage of 50% & Functional 90% - how would you infer & what should be done?

8. If Functional coverage is 50% &code coverage is 90% - how would you infer & what should be done?

Which is best in which situations?

Round 5:

1. Why are you looking for a change now?

2. Whats your core strength? Testplan/Testcase writing/ BFM development?

3. What are your expectations?