ppwl:[0,1,0.0001m,1,8.3329m,1,8.333m,0,16.6659m,0,16.

666m,1]

c_ppwl
mult
+
in1 Control
to
Voltage
-

c_sin in2 var2v in out

Sample-Hold

gate gnd + Voltage

to
Control
- Interfac e

comp_l4 v_ppwl v2var

amplitude:170
frequency:60

ppwl:[0,0,9.9999u,2.7,10.00u,0]

enbl

c_constant
enbl
in1 out
in1 out comp_l4
+1
+1 in2
integ -1 v_ppwl v_ppwl
mult mult in2 k:0.5
1
in1

out in1 k in1
+
Control ppwl:[0,1,5u,0,10u,1] ppwl:[0,0.95,5u,-0.05,10u,0.95]
+1
s to
Voltage
-
in2 in2 k:1 in2
-1 var2v

lag
+ in out + Voltage in1
Control
to Sample-Hold to K
Control
Voltage
Interfac e (s/w) + 1
- gate gnd -
in1 out in2 in1/in2
var2v v2var
+1
v_ppwl in2
2
enbl
ppwl:[0,0,9.9999u,2.7,10.00u,0] in1 out in1 out in1
+
Control
comp_l4

+1 +1 in1 out in2 in1/in2 to

Voltage

mult
integ
mult in2 mult
integ
mult in2 -

in1 out 1 in1 out 1 var2v

in1 k in1

in1 k in1 +1
in2
+1
s +1
s 2

in2 in2 k:1 in2 in2 in2 k:0.5 in2

-1 -1
2.2u enbl

comp_l4

lag
+ in out + Voltage v_ppwl v_ppwl
Control
to Sample-Hold to K 10
Control
Voltage
- - Interfac e (s/w) + 1
gate gnd 40 in out
ppwl:[0,1,5u,0,10u,1] ppwl:[0,0.95,5u,-0.05,10u,0.95]
var2v v2var Sample-Hold
6.8u
sw1_l4 gate gnd

v_ppwl
+
Voltage
to
ppwl:[0,0,0.9999u,2.7,1.00u,0] v_ppwl Control
- Interfac e
20m

v2var
100u ppwl:[0,0,9.9999u,2.7,10.00u,0]
1m 1m
50u 200n
1m 100m 1.5u
6.8u

40 D1 22n
sw1_l4

400n

+
Voltage -
2.5u

Interface
Control
22

50
v2var
+

Interfac e-
pwld

pp DC/DC sp
Control
Voltage

to

+ v_dc
v2var

Voltage 100
to
to

22

4.4u

Control
pwld
143p

Interfac e-
100u
10m

n1:1 n2:2
sw1_l4
5n

v2var v_dc
pm sm
sw1_l4

143p

5n

+ in out + Voltage
Control
to Sample-Hold to
Voltage Control
- - Interfac e
gate gnd
var2v v2var

v_ppwl

ppwl:[0,0,0.9999u,2.7,1.00u,0]

enbl

comp_l4
v_ppwl

ppwl:[0,1,55.999m,1,56m,0,399.999m,0,400m,1]

v_dc

1m

comp_l4

enbl

v_ppwl

ppwl:[0,1,55.999m,1,56m,0,399.999m,0,4000m,1]

v_dc

1m