Dynamic cmos logic

Precharge-evaluate logic

Ist the output capciatance is charged ---precharging

Then output is evaluated depending upon the inputs
These both processes are scheduled using a clock signal
So the dynamic logic ckts uses clock signals

When the clock signal is low (precharge phase )

Pmos is on ie conducting while the nmos transistor is off
The parasitic capacitance of the ckt is charged up through the conducting pmos
transistor to logic high level
Vout=Vdd
The input signals are applied during this phase but they have no effect on the
output since nmos is off

When clock signal is high(evaluation phase)

Pmos is off and nmos is conducting the output node vltage may be high or low
depending upon the input logic.
Now if the input are in such a way that they prvide a conducting path between
the node and the ground, the output capacitance will drop to zero. But the
discharge will depend upon the time period of evaluation period.
Ie if the evaluation period is small then it will not be able to discharge
completely and may remain at high logic level even if the combination of input
level is to have logic low output.

Problem in implementing dynamic logic for multistage application :

Let us consider that the output of ist stage drives the inputs of second second
dynamic cmos stage .
The 2nd stage is assumed to be 2 input nand gate

Process
During precharge phase:
Both input and output v1 and v2 are at logic high as both the pmos are on and
charge the capacitors. The external inputs are applied during this phase.
Assume that input logics of stage one are such that the output of stage one will
drop to logic zero during evaluation phase: vout 1=0 during evaluation phase.

T=0 of evaluation phase

T=t Vout1 vout2
0 1 1 due to precharge phase charging of capaticors
T=t1 1-0 vout 1 evantually drops to voltage 0 as input variables
are assumed to be such that vout=0
2nd input of nand gate is assumed to be at logic1
At the start of evaluation phase both vout and v1 are at logic 1
The vout1 1-0
But evaluation in second stage is done concurrently, with vout 1 =1 at the
beginning of evaluation phase so the vout2 of evaluation phase will be
errrornously low
Vout 11
Vout 21 at the start of evaluation phase
But clk=1
Vout 1= but tends to fall down to logic 0 due to such inputs
But the evalutation of stage happens to be concurrently with the stage one as
same clk are applied hence out put of stage 2 falls to be low but it shoud have
been at logic 1
And this gives errornous results. Although the 1st stage assumes to be at it
correct output at the end of clk period but correction in stage 2 otput is not
possible.

Domino cmos logic

Dynamic cmos logic stage is cascaded with static cmos invertor.
During precharge phase the output node of dynamic cmos ogic becomes 1 and
output of invertor=0
When clock signal is high there is only one possibility that either output of
cmos logic remains high or falls to zero depending uponthe set of inputs.
Hence output of logic can make atmost 1 transistion from low to high or
remains high. But regardless of the input applied it is not possible for cmos
invertor to make transision from logic 0 to logic 1 during evaluation phase.