Electric Power Systems Research 81 (2011) 967973

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Electric Power Systems Research

journal homepage: www.elsevier.com/locate/epsr

A proposal for standard VSC HVDC dynamic models in power system

stability studies
S. Cole a, , R. Belmans a,b
a
Katholieke Universiteit Leuven, ESAT/ELECTA, Kasteelpark Arenberg 10, 3001 Heverlee, Belgium
b
Elia, Keizerslaan 20, 1000 Brussel, Belgium

a r t i c l e i n f o a b s t r a c t

Article history: In this paper, two standard VSC HVDC dynamic models are proposed. The full system model, consisting of
Received 4 January 2010 the converter and its controllers, DC circuit equations, and coupling equations, is derived mathematically.
Received in revised form 24 October 2010 Special attention is given to the lter and phase-locked loop (PLL), often neglected in VSC HVC modelling.
Accepted 30 November 2010
A reduced order model is then derived from the full model by neglecting the smallest time constants,
Available online 3 January 2011
resulting in a reduced set of differential equations that can be integrated with a larger time step. The
models are implemented in MatDyn, a Matlab based stability program. Simulations validate the proposed
HVDC converters
models.
HVDC transmission
HVDC transmission control 2010 Elsevier B.V. All rights reserved.
Power system modelling
Power system simulation

1. Introduction
Power system stability studies require phasor models of the var-
ious equipments present in the modern power system, such as
generators and their controls, FACTS devices, and loads. In most
power system software, the user can select models from a stan-
dard models library or specify his own, user-dened models. Using
standard models for power system equipment has certain advan-
tages. Data exchange between utilities, and the transition to new
software packages proves much more convenient if standard mod-
els are used. Furthermore, standard models can be used for a wide
range of studies. In the planning stage, when the details of the
equipment are not yet known, standard models can be used. In
order to obtain acceptable results, the generic models should be
quite detailed. We call such models full models. If the equip-
ment is located far away from the part of the system under study,
the equipment can be modelled with less detail; we refer to such
models as reduced models. Only for a detailed study of a part of
the system where the equipment plays a prominent role, standard
models should not be used. A model that very closely mimics the
behaviour of the actual system is needed. Such a detailed model is
usually delivered by the manufacturer. An example of this approach
are stability studies in the early days of computer simulation of
power systems when it was common practice to represent all gen-
Corresponding author.
E-mail addresses: stijn.cole@esat.kuleuven.be, stijn.cole@gmail.com (S. Cole).
erators by the classic generator model, and only a few generators
of interest by detailed models of the generators and their con-
trols.
Standard models exist for numerous power system equipment,
such as excitation systems [1], and steam and hydro turbines
[2]. However, to the authors best knowledge, no standard mod-
els for VSC HVDC have been proposed in literature. We believe
there is a need for generic, standard models for VSC HVDC sys-
tems. VSC HVDC has an increasingly wide range of application
in the power system [3]. Hence, it is clearly an area of inter-
est and receives a lot of attention. Quite some research papers
are dedicated to the subject of modelling VSC HVDC systems
[47]. However, most of these models are not generic, e.g. the
model in [6] is derived explicitly for twelve pulse converters
[4,7] are only valid for systems using Pulse Width Modulation
(PWM).
This paper proposes two standard VSC HVDC dynamic mod-
els for power system stability studies, that are generic, i.e. valid
regardless of power electronics topologies. The phasor modelling
approach is used in this paper, as is customary in transient stabil-
ity studies. First, a full model will be constructed: the converter
equations, equations of the DC circuit and coupling equations are
derived in Section 2. In Section 3, the controller equations are
appended to the system of equations to get the complete sys-
tem of equations for the full model. Next, a reduced order model
is derived in a mathematically rigorous way in Section 4. Lastly,
simulations validate and compare the proposed models (Section
5).

0378-7796/$ see front matter 2010 Elsevier B.V. All rights reserved.
doi:10.1016/j.epsr.2010.11.032
968 S. Cole, R. Belmans / Electric Power Systems Research 81 (2011) 967973

Uf i +
1+sa
Kpd Kvco
itr ipr sb s
Xtr Rtr Xpr Rpr
Us Cf Uc

Fig. 2. PLL implementation.

Fig. 1. One-line diagram of the AC Circuit with lter. U s is the system voltage, U c
the converter voltage.
0.1

2. VSC HVDC model 0.09

0.08
2.1. Converter 0.07
0.06
VSC HVDC converters are connected to the system through a

Q
0.05
phase reactor and a transformer. A lter is connected between the
0.04
phase reactor and the transformer (Fig. 1). It was shown in [8], that
0.03
the lter behaves as a pure capacitor at system frequency. The basic
equations of this circuit, 0.02
0.01
dipr
uc uf = Lpr + Rpr ipr , (1) 0
dt 0.15 0.16 0.17 0.18 0.19 0.2 0.21 0.22 0.23 0.24 0.25
ditr Time [s]
uf us = Ltr + Rtr itr , (2)
dt
Fig. 3. Converter reactive power without PLL (close up).
duf
ipr = itr + Cf , (3)
dt
in phase-locked loops [10, p. 16]. The differential equations of the
are transformed to a rotating reference frame: system are:
d
dipr Rpr d 1
=
q
i + ipr + (ud udf ), (4a) x = bKpd (i o ), (7)
dt Lpr pr Lpr c
q o = Kvco (bKpd (i o ) + ax). (8)
dipr Rpr q d 1 q q
= i ipr + (u uf ), (4b)
dt Lpr pr Lpr c The design of the PLL can have a large inuence on the dynamic
d behaviour of the system. Therefore, it is now common practice
ditr Rtr d q 1 d
= i + itr + (u uds ), (5a) to include a detailed PLL model in electromagnetic programs. A
dt Ltr tr Ltr f
problem that can occur is that during or immediately after abnor-
q
ditr Rtr q 1 q mal system conditions such as faults, the PLL is not able to lock,
d q
= i itr + (u us ), (5b) and consequently does not produce a correct phase signal. Another
dt Ltr tr Ltr f
problem is the operation in weak AC grids: the angle settling time
dudf 1 d after disturbances is slow, while the current loop is fast. To cor-
= udf + d
(i itr ), (6a) rectly study this kind of behaviour and interactions, a phasor model
dt Cf pr
is not sufcient, as it can not capture the behaviour of the PLL in
q abnormal system conditions and weak AC grids. A detailed electro-
duf q 1 q q
= uf + (i itr ). (6b) magnetic model needs to be used. In phasor models it is therefore
dt Cf pr
less common to include the PLL. However, it has been shown in
The angle t is provided by the phase-locked loop (PLL), arbi- some contributions that the PLL has an inuence on stability. A PLL
trarily assumed here to align system voltage with the q-axis. introduces a small delay which is here in the order of 1 ms. In [11],
it has been shown that the PLL delay can cause undesired power
exchange. To investigate the inuence of the PLL on power system
2.2. Phase-locked loop
stability, we perform simulations with and without PLL, using mod-
ied versions of MATPOWER [12] and MatDyn [13]. At t = 0.2, a large
In general, a PLL is a circuit synchronizing an output signal (gen-
load with P and Q component is switched in. Fig. 3 shows a close up
erated by an oscillator) with a reference or input signal in frequency
around t = 0.2 of the converters reactive power output when no PLL
as well as in phase. [9, p. 1]. It is a control system that acts on
is included in the model. If a PLL is modelled, its time delay causes
the phase difference between the reference signal and the output,
the reactive power output to drop rst (Fig. 4), in accordance with
such that the phase of the output is locked to the phase of the ref-
the results obtained in [11]. When looking at overal reactive power
erence [9, p. 1]. All PLLs consist of three basic components: a phase
output (Figs. 5 and 6), it can be seen that the difference is very small
detector (PD), a voltage controlled oscillator (VCO), and a loop l-
and does not signicantly impact the other state variables, and thus
ter (LF). The phase detector compares the phase of the input or
can be safely neglected in power system stability studies.
reference signal with the phase of the output signal, produced by
the voltage controlled oscillator. The voltage controlled oscillator
produces an oscillating signal with a frequency determined by the 2.3. Filter
output signal of the loop lter. The loop lter removes noise and
high frequency signals, and is responsible for the control of the PLL. Many models proposed in literature do not take into account
Here the circuit of Fig. 2 is used. It is a type 2 loop, most prevalent the lter bus, e.g.: [46,14]. The one-line diagram is then simplied
 S. Cole, R. Belmans / Electric Power Systems Research 81 (2011) 967973 969

0.1 1
0.09 C=0
0 C=0.015
0.08 C=0.020

Ud [pu]
0.07 C=0.025
1
0.06
0.05
Q

2
0.04
0.03 3
0 0.05 0.1 0.15 0.2
0.02 Time [s]
0.01
0 Fig. 8. d-Axis converter voltage for different values of lter capacitance in p.u.
0.15 0.16 0.17 0.18 0.19 0.2 0.21 0.22 0.23 0.24 0.25
Time [s]
5
C=0
Fig. 4. Converter reactive power with PLL (close up).
4 C=0.015
C=0.020

Uq [pu]
C=0.025
0.8 3

0.6 2

1
Q

0.4 0 0.05 0.1 0.15 0.2

Time [s]
0.2
Fig. 9. q-Axis converter voltage for different values of lter capacitance in p.u.
0
0 1 2 3 4 5
1.2
Time [s] C=0
C=0.015
Fig. 5. Converter reactive power without PLL. 1
C=0.020
C=0.025
0.8
P [pu]

0.8

0.6
0.6
0.4
0.4
Q

0.2
0.2 0 0.05 0.1 0.15 0.2
Time [s]
0 Fig. 10. Converter active power for different values of lter capacitance in p.u.
0 1 2 3 4 5
Time [s]
1.6
Fig. 6. Converter reactive power with PLL. C=0
1.4 C=0.015
C=0.020
1.2 C=0.025
i
Q [pu]

1
Xeq Req
Us Uc 0.8

0.6

0.4

Fig. 7. One-line diagram of the AC circuit without lter. 0.2

0 0.05 0.1 0.15 0.2
Time [s]
(Fig. 7), and Eqs. (4a)(6b) reduce to:
Fig. 11. Converter reactive power for different values of lter capacitance in p.u.
did Req d 1
= i + iq + (ud uds ), (9a)
dt Leq Leq c
2.4. DC circuit modelling
diq Req q 1 q q
= i id + (u us ). (9b)
dt Leq Leq c The DC circuit of a VSC HVDC is represented in Fig. 12[15]. The
In Figs. 8 and 9 the response of converter voltage to a step in basic differential equations are:
d-axis reference current is shown for different values of lter capac- dudc1
itance. A slightly higher or lower value of the lter capacitance Cdc = idc1 icc , (10)
dt
has a large inuence on the magnitude of the converter voltage.
The effect on active and reactive power output is less pronounced dudc2
Cdc = idc2 + icc , (11)
(Figs. 10 and 11). dt
970 S. Cole, R. Belmans / Electric Power Systems Research 81 (2011) 967973

Rdc Ldc 3.1. Current controllers

udc1 icc udc2
The converter equations with lter, (4a)(6b), or without lter,
(9a) and (9b), are controlled using vector control. The reference
Cdc Cdc voltage in d and q components are expressed as:
 Ki1

udref = uds + udc + Kp1 + (id d
ipr ), (15a)
pr ref
idc1 idc2 c s
 Ki1

q q q q q
u = us + uc + Kp1 + (i ipr ), (15b)
c ref s pr ref
Cdc Cdc
with
q
udc = Lpr ipr , (16)
icc
Rdc Ldc q d
uc = Lpr ipr , (17)

Fig. 12. DC circuit. the cross-coupling terms, that compensate for the cross coupling
between the two control loops.
We introduce two additional state variables, Md and Mq , such
dicc that:
Ldc = udc1 udc2 Rdc icc . (12)
dt dMd d
= Ki1 ipr + Ki1 id ref , (18a)
dt pr
These equations can represent overhead lines, underground
cables or back-to-back installations by an appropriate selection of dMq q q
= Ki1 ipr + Ki1 i ref . (18b)
parameters. dt pr

The reference voltage can now be expressed as an algebraic

equation:
2.5. Coupling equations
udref = uds + udc + Kp1 (id d
ipr ) + Md , (19a)
c pr ref
The AC and DC circuit equations have to be coupled. As men-
q q q q q
tioned in Section 1, some models proposed in the literature u = us + uc + Kp1 (i ipr ) + Mq . (19b)
c ref pr ref
explicitly rely on PWM to derive the model. In that case, the mod-
The actual value of the voltage lags the reference due to the
ulation index can be used to provide a relation between AC and DC
time-lag of the converter. The relation between the actual value
side. Here we aim to develop a generic model, also valid for VSC
and the reference value can be represented by a time delay with
HVDC systems that do not use PWM. AC and DC side are related
time constant T [20]:
by the active power balance, that allow to calculate the q-axis ref-
erence current of the slack converter,1 and the DC currents of the dudc 1 1 d
= udc + u , (20a)
other converters: dt T T cref
q
d ud
2idcn udcn ipr duc 1 q 1 q
i
q
= n cn
, (13) = uc + u . (20b)
ref q dt T T cref
prn ucn
Combining the time-lag equations and the equations of the cur-
q q
udci ipr
d +u i
ci pri rent controllers yields:
idci = i
, i n 1. (14)
2udci dudc Kp1 d Lpr q 1 d 1 Kp1 d 1 d
= i i u + M + i + u ,
dt T pr T pr T c T d T pr ref T s
The factor two in the denominator is present because a bipolar (21a)
conguration is assumed. For a monopolar conguration, this factor
needs to be removed.
q
duc Kp1 q Lpr d 1 q 1 Kp1 q 1 q
= i + i u + Mq + i + u .
3. Control systems dt T pr T pr T c T T pr ref T s
(21b)
Control strategies is one of the most popular research topics in
the eld of VSC HVDC. A variety of controllers have been proposed
in literature: internal model control in [16], H controllers are pro- 3.2. Outer controllers
posed in [16,17], a control strategy based on Lyapunov functions in
[18], and optimal coordinated control of VSC and AC line in par- 3.2.1. Reactive power control and voltage control
allel [19]. While it is commendable to try to improve VSC HVDC Every converter can control its reactive power injection. When
systems performance by innovative control strategies, these new the system voltage is aligned with the q-axis, the reactive power Q
control strategies are often very specic and therefore not very suit- can be calculated as:
able for a generic standard model. Furthermore, more conservative d q
control strategies are used in real applications. The control strategy Q = us ipr . (22)
that is most used is vector control [17], which will be adopted here The d-axis current setpoint, id ref , is thus calculated from the
too, in conjunction with PI controllers. pr
reactive power setpoint Qref . A combination of an open loop and a
PI controller is used, leading to the equation [21]:
Qref
 Ki2

1
We call the converter that controls DC voltage the slack converter because it id = q + Kp2 + (Qref Q ). (23)
pr ref us s
compensates for the losses in the DC system.
 S. Cole, R. Belmans / Electric Power Systems Research 81 (2011) 967973 971

We nally introduce state variable Nd , resulting in an additional The AC voltage dynamics can be neglected formally by assum-
differential equation for the PI controller, ing that the voltage is equal to the voltage reference, or T = 0.
The equations describing the voltage dynamics (21a) and (21b)
dN d q d disappear.
= Ki2 (Qref us ipr ), (24)
dt DC line current (icc ) dynamics
such that substitution of (22) and (24) in (23) leads to an algebraic By removing the inductor from the DC circuit, Ldc is set to zero
expression for the d-axis current reference: and the dynamics of the DC line currents disappear from the
Qref model.
q
id = q + N d + Kp2 (Qref us ipr
d
), (25) DC voltage dynamics
pr ref us By removing the capacitors from the DC circuit, Cdc is set to zero
which can be substituted in (21a). and the dynamics of the DC voltage disappear from the model.
Instead of reactive power, AC system voltage can be controlled. This is also of theoretical interest only, as the DC capacitors are
The d-axis current reference can be calculated using a PI controller: the most important element in the DC circuit.
 Ki3
 DC current (idc ) dynamics
q
id = Kp3 + (Usref us ). (26) Lastly, the assumption Tdc = 0, removes the DC current dynam-
pr ref s
ics. It assumes that the DC current required by the DC voltage
controller is provided by the converter without delay.
3.2.2. Active power control
The q-axis reference current can be calculated in a similar way
as the d-axis reference current. It must be noted that only n 1 The ve simplications can be implemented separately or can
converters of a general n converter VSC HVDC system can set the be combined with each other. In total, 31 simplied models can
active power reference. be constructed, corresponding to 25 1 = 31 possible combinations.

Pref
 Ki4
 The advantage of the simplications is a reduction of the number
q q q of differential equations. Furthermore, less data is needed which
i = q + Kp4 + (Pref us ipr ). (27)
pr ref us s can be hard to collect. Even more advantageous is the possibility
to speed up calculation signicantly by using a larger integration
3.2.3. DC voltage control step size, if the overal systems dominant time constant is removed.
The remaining q-axis reference current can be obtained from An intelligent way to simplify the full model is thus to remove one
the DC voltage control equation of the slack converter: or more of the smallest time constants. The difculty in proposing
 Ki5
 a standard simplied model lies in the fact that the smallest time
i ref = Kp5 + (udcref udcn ). (28) constants are dependent on the parameters, which can vary con-
dcn s
siderably between different systems. The following generalities can
The dynamics of the DC circuit are approximated by a time con- nevertheless be agreed upon:
stant Tdc :
didcn 1 1 the DC capacitors is the dominant element in the DC circuit and
= i + i ref . (29)
dt Tdc dcn Tdc dcn its corresponding time constant should be maintained;
the phase reactor is the dominant element in the converter AC
All equations are now derived. The full model consists of the AC
side and its corresponding time constant should be maintained.
side equations with lters ((4)(6)) or without (9), DC circuit equa-
tions ((10)(12)), coupling equations ((13) and (14)), and current
(() and outer controllers ((24), (25) and (27)(29)). It is explained in The three time constants that can be removed, are: T , Tdc , and
[15] how these equations can be generalized to account for multi- the time constant related to Lpr . The remaining dynamics are those
terminal VSC HVDC systems. associated with the outer controllers, the phase reactor and the DC
capacitors. Compared to the full model, the order of the model is
4. Simplied models reduced with 2n + m + 1, for a n converter system with m DC lines.
Furthermore, a larger step size can be selected.
In Section 1 it was explained that reduced order, or simplied,
models can be useful in power system analysis. In this section, a 5. Simulations
set of new models is now derived that are simplications of the full
model. A correct way of deriving simplied models is eliminating The step response of two models are compared. The rst model
very small time constants. This is equivalent to making the assump- is a full model, without lter or PLL. The second model is a reduced
tion that very fast dynamics are innitely fast compared to slower order model that neglects time constants T , Teq , and the time con-
phenomena. The full model has ve time constants. For the AC side: stant related to Lpr , as explained in Section 4. The VSC HVDC system
T , the time constant of the power electronics, and the time con- is connected between two innite buses. The response to a step in
stant associated with the phase reactor. For the DC circuit: the time DC voltage reference is shown in Figs. 1316. All simulations are
constant Tdc , and the time constants related to Ldc , and Cdc . Each of performed in a modied version of MatDyn [13,22]. For this simula-
the time constants are analysed now. tions operating limits are not taken into account. It can be observed
in all gures that the full model responds satisfactorily to the step
AC current dynamics input in DC voltage. The reduced order model, while not as accu-
By removing the phase reactor from the AC circuit (Lpr = 0), the rate as the full model, reproduces the overal dynamic phenomena.
q
AC current responds instantaneously to variations in the voltage Especially for the variables Uc and Icc , shown in Figs. 14 and 16,
difference between the AC system and the converter. The dif- it can be observed that the initial response of the reduced order
ferential equations describing the current dynamics (4a)(6b) or model is more abrupt than for the full order model. This conforms
(9a) and (9b) disappear. This simplication is only of theoretical to the mathematical derivation of the simplied models: the time
interest, as the phase reactor is the most important element of constants associated to these variables are eliminated. Mathemat-
the converters AC side. ically, this means that the variables can change instantaneously. In
AC voltage dynamics Fig. 15, it can be clearly seen that the current dynamics are elimi-
972 S. Cole, R. Belmans / Electric Power Systems Research 81 (2011) 967973

0.6 0.2
full full
reduced reduced
0.5 0.15

0.4 0.1

0.3 0.05
Uc [pu]

[pu]
0.2 0
d

cc
I
0.1 0.05

0 0.1

0.1 0.15

0.2 0.2
0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1
Time [s] Time [s]

Fig. 13. Converter d-axis voltage. Fig. 16. DC current.

nated from the reduced order model: the remaining dynamics are
1.4 those associated with the charging of the DC capacitors.
full
reduced
1.3 6. Conclusion

1.2 Two standard dynamic models for VSC HVDC systems have been
proposed in this paper. The full model is constructed by combin-
1.1 ing AC side equations, DC system equations, control systems and
Ucq [pu]

coupling equations. The inuence of the AC lter and PLL, often

1 neglected, has been investigated. It is veried by simulations that
the inuence of PLL on stability can be safely neglected. Neglect-
0.9 ing the lter bus results in a small error. A reduced model was
derived mathematically by neglecting three small time constants.
0.8 The advantages are a reduced set of differential equations, and the
possibility to increase the integration step size. Simulation of a
0.7 change in DC voltage reference has been simulated. It showed that
the full model responds satisfactorily and that the reduced model
0 0.2 0.4 0.6 0.8 1 simulates the lower order dynamics.
Time [s]
References
Fig. 14. Converter q-axis voltage.
[1] IEEE Committee Report, Excitation system models for power system stability
studies, IEEE Trans. Power apparatus and systems 100 (2) (1981) 494509,
doi:10.1109/TPAS.1981.316906.
[2] IEEE Committee Report, Dynamic models for steam and hydro turbines in
1.14
power system studies, IEEE Trans. power apparatus and systems 92 (6) (1973)
full
19041915, doi:10.1109/TPAS.1973.293570.
reduced
1.12 [3] S. Cole, R. Belmans, Transmission of bulk power: the history and applications of
voltage-source converter high-voltage direct current systems, IEEE Ind. Elec-
tronics Magazine 3 (3), (2009) 1924.
1.1 [4] C. Zheng, X. Zhou, R. Li, Dynamic modeling and transient simulation for VSC
based HVDC in multi-machine system, in: Proc. International Conference on
1.08 Power System Technology PowerCon 2006, 2006, pp. 17.
[5] S. Cole, R. Belmans, Modelling of VSC HVDC using coupled current injectors,
Udc [pu]

in: Proc. IEEE Power and Energy Society General Meeting Conversion and
1.06 Delivery of Electrical Energy in the 21st Century, 2008, pp. 18.
[6] K.R. Padiyar, N. Prabhu, Modelling control design and analysis of VSC
1.04 based HVDC transmission systems, in: Proc. International Conference on
Power System Technology PowerCon 2004, vol. 1, 2004, pp. 774779,
doi:10.1109/ICPST.2004.1460096.
1.02 [7] O.A. Giddani, G.P. Adam, O. Anaya-Lara, K.L. Lo, Grid integration of a large off-
shore wind farm using VSC-HVDC transmission system in parallel with AC
submarine cable, in: Proceedings of the 44th International Universities Power
1
Engineering Conference, University of Strathclyde, 2009.
[8] C. Du, E. Agneholm, G. Olsson, Comparison of different frequency controllers
0.98 for a VSC-HVDC supplied system, IEEE Trans. Power Delivery 23 (4) (2008)
0 0.2 0.4 0.6 0.8 1 22242232, doi:10.1109/TPWRD.2008.921130.
Time [s] [9] R.E. Best, Phase Locked Loops, McGraw-Hill Professional, 2007.
[10] F.M. Gardner, Phaselock Techniques, Wiley-Interscience, 2005.
Fig. 15. DC voltage. [11] A.H. Norouzi, A.M. Sharaf, Two control schemes to enhance the dynamic per-
formance of the STATCOM and SSSC, IEEE Trans. Power Delivery 20 (1) (2005)
435442, doi:10.1109/TPWRD.2004.839725(410) 2.
 S. Cole, R. Belmans / Electric Power Systems Research 81 (2011) 967973
[12] Matpower website, http://www.pserc.cornell.edu/matpower/.
[13] MatDyn website, http://www.esat.kuleuven.be/electa/teaching/matdyn/.
[14] J.M. Mauricio, A.G. Exposito, Modeling and control of an HVDC-VSC
transmission system, in: Proc. IEEE/PES Transmission. Distribution Confer-
ence and Exposition: Latin America TDC06, 2006, pp. 16, doi:10.1109/
TDCLA.2006.311385.
[15] S. Cole, R. Belmans, Generalized dynamic VSC MTDC model for power sys-
tem stability studies, IEEE Trans. Power Systems 25 (3) (2010) 16551662,
doi:10.1109/TPWRS.2010.2040846.
[16] H. Liang, G. Li, P. Li, M. Yin, Analysis and design of H1 controller in VSC HVDC sys-
tems, in: IEEE/PES Transmission and Distribution Conference and Exhibition:
Asia and Pacic, 2005, p. 6.
[17] L. Zhang, H.-P. Nee, Multivariable feedback design of VSC-HVDC connected
weak AC systems, in: PowerTech 2009, 2009, pp. 18.
973
[18] G. Li, G. Ma, C. Zhao, G. Li, Research of nonlinear control strategy for VSC-HVDC
system based on Lyapunov stability theory, in: Proc. 3rd International Confer-
ence on Electric Utility Deregulation and Restructuring and Power Technologies
DRPT 2008, 2008, pp. 21872191, doi:10.1109/DRPT.2008.4523773.
[19] C. Mao, Z. Hu, J. Lu, D. Chang, S. Fan, Application of an optimal coordinated
control strategy to VSC HVDC, in: Proc. IEEE PES Power Systems Confer-
ence and Exposition PSCE06, 2006, pp. 21412145, doi:10.1109/PSCE.2006.
296275.
[20] G. Terrde, Electrical Drives and Control Techniques, Acco, 2004.
[21] C. Du, VSC-HVDC for industrial power systems, Ph.D. Thesis, Chalmers Univer-
sity of Technology, 2007.
[22] S. Cole, R. Belmans, MatDyn, a new Matlab based toolbox for power system
dynamic simulation, IEEE Trans. Power Syst., in press.