VHDL in Deld

Pune Vidyarthi Grihas
COLLEGE OF ENGINEERING, NASHIK 3.
VHDL
By
Prof. Anand N. Gharu
(Assistant Professor)
PVGCOE Computer Dept.
30th June 2017

.
Introduction to VHDL
Introduction
Entity
Architecture
Package
Data Objects
CASE Statement
Examples of VHDL Codes
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Introduction
What is VHDL?
VHDL is a Hardware Description Language used for
modeling digital systems made of interconnection of
components.
It is used for describing hardware from the abstract to
concrete level.
10/14/2017 Mrs. Sunita M Dol, CSE Dept. 3

Introduction
What is VHDL?
V- VHSIC
Very High Speed Integrated Circuit
H- Hardware
D- Description
L- Language

Introduction
VHDL source code file has two main sections
Entity
Each entity declaration includes a list of interface signals and
their types that can be used to connect it to other modules.
Architecture
The behavior of the circuit and each of its component is
described .
The behavior may be described in
Structural form or
Set of concurrent statement or
Set of sequential statement

Introduction
Basic concept of VHDL
Entity
Architecture

Introduction
Use of Lower Level Entities by Higher Level
Architecture
Entity A Entity E
Architecture Architecture
A E
Entity B Entity C Entity D
Architecture Architecture Architecture

B C D

Introduction
VHDL Rules and Characteristics
1. A strongly typed language: Each signal, variable and
constants must match with the predefined type in the
program.
1. Operators: AND, OR, NAND, NOR, XOR, XNOR, NOT,

addition, subtraction, multiplication, division etc.
1. Reserved Keywords
1. Special Notation Symbols 8

Introduction
5. A Free Form Language: Carriage returns, blank
lines, and additional blank spaces may be used
between the words for clarity.
6. Long line can be continue over more than one line.
7. A line starting with two adjacent hyphens is treated

as comment
-- This is a comment
Introduction
8. Concluding semicolon is syntactically required
9. TIME is predefined type.
10. It allows arrays to be indexed in either direction

(ascending or descending)

Introduction
11. Data Flow Language: It is a programming paradigm
whose execution model can be represented by a directed
graph, representing the flow of data between nodes,
similarly to a dataflow diagram
12. A basic identifier in VHDL is composed of a sequence of

one or more alphanumeric character and underscore
character. The first character must be an alphabet and the
last character must not be an underscore. Two
consecutive underscores are not allowed

Introduction
13. VHDL is case insensitive.
14. Boolean operators AND, OR, NAND, NOR, XOR,

XNOR, NOT are built in VHDL
15. A system library ieee library is provided which

stores the package for standard logic gates and
other commonly used gates. User library can be
created by the users.
Chapter 6: Introduction to
VHDL
Introduction
Entity
Architecture
Package
Data Objects
CASE Statement

Entity
Entity refers to any digital device that posses
some form of intercommunication characteristic.
It is hardware abstraction of an actual digital

hardware device.
It may be decomposed into its constituents lower

level entity or subcomponents or it may be
treated as a building block to construct a high
level entity.
Entity
All designs are created using entities.
A design must have at least one entity.

Entity
The syntax of entity declaration:
Data types:
In-built
ENTITY entity_name IS User-defined
Name of the ENTITY
circuit
User-defined
PORT(signal1,signal2,.. :mode type;
signal3,signal4,.. :mode type);
Direction of port
Note the absence
3 main types:of semicolon ; at
END entity_name; the end of the last signal and the
Port names or in: Input
presence at the end of the closing
Signal names out: Output
bracket
inout: Bidirectional
Entity Example
ENTITY my_ckt IS Datatypes:

Name of the circuit
PORT ( In-built
User-defined
User-defined
A: in bit; A Filename same as circuit
name recommended X
B: in bit;
B Example:
Example. my_ckt
S: in bit; Circuit name: my_ckt
Y
S
X: out bit; Direction
Filename: my_ckt.vhd
of port
Y: out bit 3 main types:
names
Port ); or Note the absence
in: Inputof semicolon ;
at the end
of theOutput
out: last signal and the
END
Signal names
my_ckt; presence at the end of the closing
bracket inout: Bidirectional
Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated) 17
Entity
Entity Declaration for AND gate:
ENTITY and2 IS
PORT(A, B: IN BIT;
Q: OUT BIT);
END and2;

Entity
Entity Declaration for OR gate:
ENTITY or2 IS
PORT(A, B: IN BIT;
Q: OUT BIT);
END or2;

Entity
Entity Declaration for NOT gate:
ENTITY not2 IS
PORT(A: IN BIT;
Q: OUT BIT);
END not2;

Entity
Entity Declaration for XOR gate:
ENTITY xor2 IS
PORT(A, B: IN BIT;
Y: OUT BIT);
END xor2;

Entity
Entity Declaration for XOR gate:
ENTITY ckt_fig IS
PORT(A, B: IN BIT;
Y: OUT BIT);
END ckt_fig;

Entity
Entity Declaration for RSFF gate:
ENTITY rsff IS
PORT(SET, RESET: IN BIT;

Q, QB: INOUT BIT);
END rsff;

VHDL
Introduction
Entity
Architecture
Package
Data Objects
CASE Statement

Architecture
A VHDL design entity is modeled using an entity
declaration and at least one architecture body.
Entity Declaration describe the external view of

the entity whereas the architecture of body
contains the internal description of the entity.

Architecture
The internal description can be specified as
A set of interconnected components that represents
the structure of the entity.
A set of concurrent statement that represent the
behaviour of the entity.
A set of sequential statement that represent the
behaviour of the entity.
An architecture body is composed of two parts

Declarative part and
Statement part
Architecture
The syntax of architecture body is
ARCHITECTURE architecture_name OF entity_name IS
[declarative part]
BEGIN
[statement part]
END architecture_name
Declarative part cab be used to declare signals, user

defined types, constants, components, function and
procedure definitions which are local to that architecture.
All the statement in statement part are concurrent
statement which means these are executed concurrently
and not sequentially.
Architecture
Structural Modeling
An entity is described as a set of interconnected
component in the architecture body.
The component declaration lists its name, mode and

type of each of its port.
For each component, component instantiation

statement is required which includes
a label
component name and
10/14/2017 Mrs. Sunita M Dol, CSE Dept.
association between the actual signals that are visible 28in
Architecture
Structural Modeling Example
This circuit has two

2-input AND gates,
one 2-input OR gate
and two NOT gates

ENTITY xor2 IS
PORT(A, B: IN BIT; Y: OUT BIT);
Architecture name
END xor2;
entity name
ARCHITECTUER XOR_STRUCTURE OF xor2 IS
COMPONENT and2
PORT(X, Y: IN BIT, Z:OUT BIT);
For each type of
END COMPONENT;
component, component
COMPONENT or2 declaration is required
PORT(P, Q: IN BIT, R:OUT BIT);
END COMPONENT;
COMPONENT not2
Local signals or buried nodes
declaration which are neither
inputs nor outputs of the entity
of architecture
Component instantiation statements

includes
a label such as I1, I2, A1, A2,.. ;
component name such as not2, and2,
or2,etc. and
association between the actual signals
that are visible in architecture body and the
ports of a component with being instantiated
SIGNAL AB, BB, X1, X2: BIT;
BEGIN The signals in PORT MAP list are in
the same order in which they
appear in entity definition of the
component
I1: not2 PORT MAP (A, AB);
ENTITY rsff IS
Q, QB: INOUT BIT);
Architecture name
END rsff;
entity name
ARCHITECTUER RSFF_STRUCTURE OF rsff IS
component
declaration
COMPONENT nand2
PORT(A, B: IN BIT, Y:OUT BIT);
END COMPONENT; Component
instantiation statements
BEGIN
N1: nand2 PORT MAP(SET,
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Architecture
Data Flow Modeling
In this modeling, the flow of data through the entity
is expressed using concurrent signal assignment
statements.
These statement execute concurrently i.e. in

parallel.
The statement contained in the model assigns the

values to signals.

Architecture
Data Flow Modeling
Signal assignment statement is executed whenever a

signal in its sensitivity list changes value.
Time delay can also be introduces in the signal

assignment statement.
A<= B AFTER 10 ns;
Signal A gets the value of signal B after a lapse of 10
ns.

Architecture
Architecture Body of AND gate using Data flow
model :
ENTITY and2 IS
PORT(A, B: IN BIT;
Q: OUT BIT);
END and2;
ARCHITECTUER df_and2 OF and2 IS

BEGIN
Y <= A AND B AFTER 10ns;
END df_and2;
Architecture
Architecture Body of OR gate using Data flow
model :
ENTITY or2 IS
PORT(A, B: IN BIT;
Q: OUT BIT);
END or2;
ARCHITECTUER df_or2 OF or2 IS

BEGIN
Y <= A OR B AFTER 10ns;
END df_or2;
Architecture
Architecture Body of NOT gate using Data flow
model :
ENTITY not2 IS
PORT(A: IN BIT;
Q: OUT BIT);
END not2;
ARCHITECTUER df_not2 OF not2 IS

BEGIN
Y <= NOT A AFTER 10ns;
END df_not2;
Architecture
Architecture Body of XOR gate using Data flow
model :
ENTITY xor2 IS
PORT(A, B: IN BIT;
Q: OUT BIT);
END xor2;
ARCHITECTUER df_xor2 OF xor2 IS

BEGIN
Y <= (A AND (NOT B)) OR (B AND (NOT A));
END df_xor2;
Architecture
Architecture Body of RSFF using Data flow
model:
ENTITY rsff IS
Q, QB: INOUT BIT);
END rsff;
ARCHITECTUER df_rsff2 OF rsff IS

BEGIN
Q <= NOT (QB AND SET) after 5ns;
QB <= NOT (Q AND RESET) after 5ns;
Architecture
Data Flow Modeling
There are two types of concurrent signal assignment
statement :
Conditional Signal Assignment and
Selected Signal Assignment

Architecture
Data Flow Modeling
Conditional Signal Assignment allows a signal to be
one of several values based on certain conditions to be
satisfied.
It uses keywords WHEN and ELSE, boolean operators

such as AND, OR, NOT, and XOR and relational
operators =, /=(inequality), >, >= and <=

Architecture
Data Flow Modeling
Conditional Signal Assignment Example
Use if IEEE library which
includes STD_LOGIC
type.
LIBRARY ieee; STD_LOGIC type is a standard
data type for representation of
USE ieee.std_logic_1164.all;
logic signals in VHDL
ENTITY mux2 IS A
PORT(A, B, S: IN STD_LOGIC; 2:1 MUX Y
Y: OUT STD_LOGIC); B
END mux2;
S
ARCHITECTURE df_mux2 OF mux2 IS
Architecture
Data Flow Modeling
Selected Signal Assignment allows a signal to be
assigned one of several values based on selection
criterion.
It begins with the keyword WITH, specifies the

selection criterion and then SELECT keyword.
Syntax is
WITH select_signal SELECT
signal_name <= value1 WHEN value1_of_select_sig,
value2 WHEN value2_of_select_sig,
value3 WHEN value3_of_select_sig,
Architecture
Data Flow Modeling
Selected Signal Assignment Example
Use if IEEE library which
includes STD_LOGIC
type.
LIBRARY ieee; STD_LOGIC type is a standard

data type for representation of
USE ieee.std_logic_1164.all
logic signals in VHDL
ENTITY mux2 IS A
PORT(A, B, S: IN STD_LOGIC; 2:1 MUX Y
B
Y: OUT STD_LOGIC);
END mux2;
S
Architecture
Behavioural Modeling
The behaviour of the entity is expressed using
statement which are executed sequentially.
A process statement is the main mechanism used to

model the behaviour of an entity.
The process statement starts with keyword PROCESS

and ends with the keyword END PROCESS.

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Any assignment made to the signal
Mrs. Sunita M Dol, CSE Dept.
inside the process
45
are not visible outside the process until all of the
Architecture
The process statement consist of three parts
Sensitivity list
Declarative part and
Statement part.
Sensitivity list:
A process statement is always active and executes at all times
if not suspended.
Following the PROCESS keyword, the sensitivity list in
parentheses is specifies.
It includes all input signals that are used inside the PROCESS.
Architecture
Sensitivity list:
When the program flow reaches the last sequential statement,
the process becomes suspended until another event occurs on
the signal that it is sensitive to.

Architecture
Declarative part:
It is used to declare local variables or constants that can be
used only inside the process.
Signals and constant are declared in declarative part of an
architecture that encloses a process statement can be used
inside the process.
Initialization of objects declared in a process is done only once
at the beginning of a simulation run.
The initialization in a subprogram are performed each time the
subprogram is called.

Architecture
Statement part:
It consist of the area between the keywords BEGIN and END
PROCESS.
All the statements are sequential and are executed one after
the other in sequential order.
The statement part of a process is always active.
When the program flow reaches the last sequential statement
of this part, the execution returns to the first statement in the
statement part and continues.

ENTITY rsff IS
Q, QB: INOUT BIT);
END rsff; Sensitivity list which
includes all input
signals will have
SET and RESET.
ARCHITECTUER behave_rsff2 OF rsff IS
BEGIN
Statement
part
PROSESS (SET, RESET)
BEGIN
IF SET=1 AND RESET=0 THEN
Q<= 1 AFTER 10ns;
QB<= 0 AFTER 10ns;
ELSEIF SET=0 AND RESET=0 THEN
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Architecture
Example:
Behavior for output X:
When S = 0
X <= A A
X
When S = 1 B my_ckt
X <= B Y
S
Behavior for output Y:
When X = 0 and S =0
Y <= 1
Else
Y <= 0

Architecture
ARCHITECTURE ARCH_NAME OF MY_CKT IS
BEGIN
PROCESS (A,B,S)
BEGIN
IF (S=0) THEN
X <= A;
ELSE
X <= B;
Error: Signals defined as
END IF; output ports can only be
driven and not read
IF ((X = 0) AND (S = 0)) THEN

Y <= 1;
ELSE
Y <= 0;
END IF;
Architecture
ARCHITECTURE ARCH_NAME OF MY_CKT IS Signals can only be defined in
this place before the BEGIN
SIGNAL XTEMP: BIT
keyword
BEGIN
PROCESS (A,B,S, XTEMP)
General rule: Include all
BEGIN signals in the sensitivity list
IF (S=0) THEN of the process which either
appear in relational
XTEMP <= A;
comparisons or on the right
ELSE side of the assignment
XTEMP <= B; operator inside the
PROCESS construct.
END IF;
In our example:
IF ((XTEMP = 0) AND (S = 0)) THEN XTEMP and S occur in

relational comparisons
Y <= 1;
A, B and XTEMP occur on
ELSE
the right side of the
Y <= 0; assignment operators 53
Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated)
END IF;
Complete AND GATE Example
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY AND_EXAMPLE IS
PORT(A,B: IN STD_LOGIC;
YA,YB,YC: OUT STD_LOGIC);
END ENTITY AND_EXAMPLE;
ARCHITECTURE TEST OF AND_EXAMPLE IS
BEGIN
-- DATAFLOW MODEL (YA)
YA <= A AND B;
-- STRUCTURAL MODEL (YB)
AND2:A_7408 PORT MAP(A,B,YB);
-- BEHAVIORAL MODEL (YC)
PROCESS(A,B)
BEGIN
YC <= 0;
VHDL
Introduction
Entity
Architecture
Package
Data Objects
CASE Statement

Package
Package is a collection of codes of commonly
used data type definition, declaration of signals
and component.
It allows the sharing of definitions of data type,

signals and components among design entities
which access the package.
It is stored in a computer file system at a location

specified by its name.
Package
Definition and declarations provided in the
package can be used in any source code file by
including the statement
USE is
used for
accessing LIBRARY library_name,
the
package USE library_name.package_name.ALL
The library_name
represents the location in The package name
the computer file system is specified by a ALL is used to
where the package is package_name for having
stored. A library may a which may a access to the
system library or a user system library or a entire
library user library package

VHDL
Introduction
Entity
Architecture
Package
Data Objects
CASE Statement

Data Objects
In VHDL code, information is represented as
signals, variables and constants which are
referred to as data objects.
Signals basically represent wires in a circuit.
VHDL variables are similar to signals but they do

not have physical significance in a circuit.
Variables are used in functions, procedures and

processes
Data Objects
Declaration of Data Objects
A signal is declared as
SIGNAL signal_name: type_name
Signal Type: The most commonly used signal types

are:
BIT
BIT_VECTOR
STD_LOGIC
STD_LOGIC_VECTOR
INTEGER
10/14/2017 ENUMERATION Mrs. Sunita M Dol, CSE Dept. 60
Data Objects
Signal Type
BIT: this type is predefined signal type in VHDL. Objects of BIT
type can have the values 0 or 1
SIGNAL A: BIT;
BIT_VECTOR: This is also a predefined type. It is used to

declare a group of elements of the same type together as a
single object such as byte
MSB LSB
SIGNAL byte: BIT_VECTOR(7 DOWN TO 0);
byte(7)=1 Byte(6)=1 Byte(0)=1
byte<= 11001001;

Data Objects
Signal Type
STD_LOGIC: This type of data object was added to VHDL
standard in IEEE standard 1164. For using this type, the
following two statements are to be included
LIBRARY IEEE;
STD_LOGIC_VECTOR: This type is an extension of

BIT_VECTOR type. It represents an array of STD_LOGIC
objects. A signal declaration statement can be:
SIGNAL A, B, C: STD_LOGIC_VECTOR (3 DOWN TO 0);
10/14/2017 Mrs. Sunita M Dol, CSE Dept.

Use of STD_LOGIC_VECTOR type also require access 62to
Data Objects
Signal Type
INTEGER: It is similar to mathematical integer. An INTEGER
signal represents a binary number of 32 bits and hence it can
represent the number s from (231-1) to +(231-1). It is also
possible to declare integer with fewer bits using the RANGE
keyword.
SIGNAL B: INTEGER RANGE -127 TO 127;
ENUMERATION: This type of signal can have user specified

possible values of the signal. Its type declaration has the list-
value separated by commas.
TYPE traffic_light_state IS (reset, stop, wait, go);

Data Objects
Signal Type
BOOLEAN: This type of object has two values, true and false
where true is equivalent to 1 and false is 0. BOOLEAN type is a
predefined type.
SIGNAL lock_out: BOOLEAN;

Data Objects
VARIABLE data object
A variable is declared as
VARIABLE variable_name: variable_type;
Assignment operator used for variable is :=.
Examples
VARIABLE temp: INTEGER;

temp:=0;
VARIABLE sum : INTEGER RANGE 0 TO 100 :=10;

VHDL
Introduction
Entity
Architecture
Package
Data Objects
CASE Statement

CASE statement
It is similar to a selected signal statement.
The CASE statement has a selection signal or

expression and WHEN clauses for various
valuations of the selection signal.

CASE statement
Its general form is shown below:
CASE expression IS
WHEN constant_value => statement;
WHEN constant_value => statement;
WHEN OTHERS => statement;
END CASE;

Examples of VHDL Code
Multiplexers in VHDL:
Consider the 4:1 multiplexer circuit

Using
CASE
statement
VHDL
Introduction
Entity
Architecture
Package
Data Objects
CASE Statement

Describing Truth Table in VHDL:
Consider the truth table given below
Row Inputs
no
A B C
0 0 0 0 0
1 0 0 1 1
2 0 1 0 1
3 0 1 1 0
4 1 0 0 1
5 1 0 1 0
6 1 1 0 0
7 1 1 1 1
Row Inputs
no
ENTITY table1 IS A B C
PORT(A, B, C: IN BIT; Y: OUT BIT);

0 0 0 0 0
END table1; 1 0 0 1 1
2 0 1 0 1
3 0 1 1 0
4 1 0 0 1
ARCHITECTUR truth_table of table1 IS 5 1 0 1 0
6 1 1 0 0
SIGNAL comb_cir : BIT_VECTOR (2 DOWN TO 0);
7 1 1 1 1
BEGIN
comb_cir <= A&B&C;
& is used to connect
Y <= 0 WHEN 000,
the bit variables to
1 WHEN 001, form a bit vector
1 WHEN 010,
0 WHEN 011,
1 WHEN 100,
0 WHEN 101,
0 WHEN 110,
Arithmetic Circuits in VHDL:
Consider the half adder circuit

Using Structural Architecture:
LIBRARY IEEE;
ENTITY H_A IS
PORT (A, B: IN STD_LOGIC; S, C: OUT STD_LOGIC);
END H_A;
ARCHITECTURE HA_STR OF H_A IS

COMPONENT XOR2
PORT (X, Y: IN STD_LOGIC; Z: OUT STD_LOGIC);
END COMPONENT;
COMPONENT AND2
Using Data Flow Architecture:
LIBRARY IEEE;
ENTITY H_A IS
END H_A;
ARCHITECTURE HA_DF OF H_A IS

BEGIN
S <= A XOR B AFTER 10ns;
C <= A AND B AFTER 5ns;
END HA_DF;
Using Behavioural Modeling
ENTITY H_A IS
PORT(A, B: IN BIT;
S, C: OUT BIT);
END H_A;
ARCHITECTUER BEHAVE_HA OF H_A IS

BEGIN
PROSESS (A, B)
BEGIN
IF A=0 AND B=0 THEN
S <= 0 AFTER 10ns;
C <= 0 AFTER 10ns;
Using Data Flow Architecture with selected
signal assignment:
LIBRARY IEEE;
ENTITY H_A IS
END H_A;
ARCHITECTURE HA_DFSS OF H_A IS

BEGIN
HA_X <= A & B;
HA_Y <= C & S;
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WITH HA_X SELECT Mrs. Sunita M Dol, CSE Dept. 78
Arithmetic Circuits in VHDL:
Consider the half subtractor circuit

Using Structural Architecture:
LIBRARY IEEE;
ENTITY H_S IS
PORT (A, B: IN STD_LOGIC; DIFF, BORROW: OUT STD_LOGIC);
END H_S;
ARCHITECTURE HS_STR OF H_S IS

COMPONENT XOR2
PORT (X, Y: IN STD_LOGIC; Z: OUT STD_LOGIC);
END COMPONENT;
COMPONENT AND2
PORT
10/14/2017 (P, Q: IN STD_LOGIC;Mrs.
R: Sunita
OUTMSTD_LOGIC);
Dol, CSE Dept. 80
Using Data Flow Architecture:
LIBRARY IEEE;
ENTITY H_S IS
END H_S;
ARCHITECTURE HS_DF OF H_S IS

BEGIN
DIFF <= A XOR B AFTER 10ns;
BORROW <= ((NOT A) AND B) AFTER 5ns;
END HS_DF;
Using Behavioural Modeling
ENTITY H_S IS
PORT(A, B: IN BIT;
DIFF, BORROW: OUT BIT);
END H_S;
ARCHITECTUER BEHAVE_HS OF H_S IS

BEGIN
PROSESS (A, B)
BEGIN
IF A=0 AND B=0 THEN
DIFF <= 0 AFTER 10ns;
BORROW <= 0 AFTER 10ns;
Using Data Flow Architecture with selected
signal assignment:
LIBRARY IEEE;
ENTITY H_S IS
END H_S;
ARCHITECTURE HS_DFSS OF H_S IS

BEGIN
HA_X <= A & B;
HA_Y <= BORROW & DIFF;
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WITH HA_X SELECT Mrs. Sunita M Dol, CSE Dept. 83
Multiplexers in VHDL:
Consider the 4:1 multiplexer circuit

Using
CASE
statement
Decoder in VHDL:
Consider the 2:4 decoder circuit

Using Sequential Architecture model
LIBRARY IEEE;
ENTITY DECODER24 IS
PORT( A, B, EN:IN STD_LOGIC;
Z:OUT STD_LOGIC_VECTOR(0 TO 3));
END DECODER24;
ARCHITECTURE BEHV_DEC OF DECODER24 IS

BEGIN
-- PROCESS STATEMENT
PROCESS (A, B, EN)

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VARIABLE AB, BB: STD_LOGIC; Mrs. Sunita M Dol, CSE Dept. 87
Using CASE Statement
LIBRARY IEEE;
ENTITY DECODER24 IS
Z:OUT STD_LOGIC_VECTOR(0 to 3));
END DECODER24;
ARCHITECTURE BEHV_DEC2 OF DECODER24 IS

SIGNAL AB : STD_LOGIC_VECTOR (1 DOWN TO 0);
BEGIN
AB <= A & B;
PROCESS (AB, EN)
BEGIN
IF EN = 1 THEN
Using Selected signal Assignment Statement
LIBRARY IEEE;
ENTITY DECODER24 IS
Z:OUT STD_LOGIC_VECTOR(0 TO 3));
END DECODER24;
ARCHITECTURE BEHV_DEC2 OF DECODER24 IS

SIGNAL ENAB : STD_LOGIC_VECTOR (2 DOWN TO 0);
BEGIN
ENAB <= EN & A & B;
WITH ENAB SELECT
Z <= 1110 WHEN 100,
1101 WHEN 101,
Priority Encoder in VHDL:
Consider the Decimal to BCD Priority Encoder circuit

Using Conditional Signal Assignment
Statement
LIBRARY IEEE;
ENTITY PRIORITY_ENCODER IS
PORT( I : IN STD_LOGIC_VECTOR(9 DOWN TO 0);
Y : OUT STD_LOGIC_VECTOR(3 DOWN TO 0) );
END PRIORITY_ENCODER;
ARCHITECTURE BEHV_PE OF PRIORITY_ENCODER IS

BEGIN
Y <= 0110 WHEN I(9) = 0 ELSE
0111 WHEN I(8) = 0 ELSE
1000 WHEN I(7) = 0 ELSE
Using Sequential Signal Statement
LIBRARY IEEE;
ENTITY PRIORITY_ENCODER IS
PORT( I : IN STD_LOGIC_VECTOR(9 DOWN TO 0);
Y : OUT STD_LOGIC_VECTOR(3 DOWN TO 0) );
END PRIORITY_ENCODER;
ARCHITECTURE BEHV_PE2 OF PRIORITY_ENCODER IS

BEGIN
PROCESS(I)
BEGIN
IF I(9) = 0 THEN Y <= 0110;
ELSEIF I(8) = 0 THEN Y <= 0111;
ELSEIF I(7) = 0 THEN Y <= 1000;
Comparator in VHDL:

USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COMPARATOR IS
PORT( A, B : IN STD_LOGIC_VECTOR(1 DOWN TO 0);
AGTB, AEQB, ALTBY : OUT STD_LOGIC);
END COMPARATOR;
ARCHITECTURE BEHV OF COMPARATOR IS

BEGIN
AGTB <= 1 WHEN A>B ELSE 0;
AEQB <= 1 WHEN A=B ELSE 0;
ALTB <= 1 WHEN A<B ELSE 0;
END BEHV;

BCD to 7-Segment Decoder in VHDL:

PORT( BCD : IN STD_LOGIC_VECTOR(3 DOWN TO 0);
LED7 : OUT STD_LOGIC_VECTOR(1 TO 7));
END DEC_7_SEG;
ARCHITECTURE BCDTO7SEG OF DEC_7_SEG IS

BEGIN
PROCESS(BCD)
BEGIN
CASE BCD IS
WHEN 0000 => LED7 <= 1111110;
WHEN 0001 => LED7 <= 0110000;
WHEN 0010 => LED7 <= 1101101;
WHEN 0011 => LED7 <= 1111001;
WHEN 0100 => LED7 <= 0110011;
WHEN 0101 => LED7 <= 1011011;
WHEN 0110 => LED7 <= 0011111;
WHEN 0111 => LED7 <= 1110000;
WHEN 1000 => LED7 <= 1111111;
WHEN 1001 => LED7 <= 1110011;
WHEN OTHERS => LED7 <= -------;
Describing Sequential Circuit using VHDL:
EVENT Attribute: the EVENT attribute when attached
to a signal name such as Clock, yields a value of type
Boolean that is 'true' or 'false' depending upon the
occurrence of the event or not respectively.
It is expressed as Clock' EVENT.
Its value is 'true' when a change occurs in the value of clock
and 'false' when there is no change.
The Clock' EVENT AND Clock='1' statement describes LOW to
HIGH transition of the clock signal when a change occurs in the
value of Clock. This statement describe the positive edge
triggered FLIP-FLOPS.

WAIT statement: A WAIT statement is used to suspend
the sequential execution of a process or subprograms.
The suspended process or subprogram can be resumed
by specifying the WAIT statement in the following three
ways:
WAIT ON signal changes
WAIT UNTIL an expression is true
WAIT FOR a specific amount of time

WAIT statement
WAIT ON: This statement is used for suspending the
execution of the process for the time specified in terms of
an event occurring on the signal specified in the WAIT
statement.
e.g. in a clocked FF with an asynchronous reset input
WAIT ON reset, clock; statement causes the process to
suspend execution until an event occurs on either reset or
clock input.
This clause can be used in clocked synchronous circuits
description.

WAIT statement:
WAIT UNTIL: This statement suspends execution of the
process until the expression specified in the statements
returns a value true.
e.g. for a clocked FF, the WAIT UNTIL statement given
below causes resumption of execution of the process when
a rising edge occurs on the clock input
WAIT UNTIL Clock = '1' AND Clock' EVENT;

WAIT statement:
WAIT FOR: This statement is used for suspending the
execution of the process for the time specified either
directly or by an expression. The execution continues on
the statement following the WAIT statement after the
specified time.
e.g. WAIT FOR 10 ns;
suspends the execution for 10 ns after which the execution
continues with the statement following the WAIT statement.
If the time is specified by an expression such as (A+B*C)
then the time is calculated evaluating the expression.

Flip Flop in VHDL:
Consider DFF
D Q
Data IN
Output
Clock
_
Q

D Q
Data IN
LIBRARY IEEE; Output
Clock _
Q
ENTITY DFF IS
PORT(DATA_IN:IN STD_LOGIC;
CLOCK:IN STD_LOGIC;
DATA_OUT:OUT STD_LOGIC);
END DFF;
ARCHITECTURE BEHV_DL OF DFF IS

Flip Flop in VHDL:
Consider DFF
D Q
Data IN
Output
Clock
_
Q

D Q
Data IN
LIBRARY IEEE; Output
Clock _
Q
USE WORK.ALL;
ENTITY DFF IS
CLOCK:IN STD_LOGIC;
END DFF;
ARCHITECTURE BEHV OF DFF IS

Flip Flop in VHDL:
Consider DFF
D Q
Data IN
Output
Clock
_
Q

D Q
Data IN
LIBRARY IEEE;
Output
USE IEEE.STD_LOGIC_1164.ALL; Clock _
USE WORK.ALL; Q
ENTITY DFF IS
CLOCK:IN STD_LOGIC;
END DFF;
ARCHITECTURE BEHV1 OF DFF IS

BEGIN
PROCESS
BEGIN
WAIT UNTILCLOCK'EVENT AND CLOCK='1'
Register in VHDL:
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ENTITY SHIFT4 IS
PORT(DIN:IN STD_LOGIC;
CLOCK, CLEAR:IN STD_LOGIC;
Q:OUT STD_LOGIC(3 DOWN TO 0));
END SHIFT4;
ARCHITECTURE BEHV OF DFF IS

BEGIN
PROCESS(CLEAR, CLOCK)
BEGIN
IF CLEAR ='0' THEN Q <= 0000;
ELSEIF (CLOCK='1' AND CLOCK'EVENT) THEN
Q(3) <= DIN;
Q(2) <= Q(3);
Q(1) <= Q(2);
Q(1) <= Q(0);
END IF;
END PROCESS;
Thank You
10/14/2017 110

VHDL in Deld

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VHDL in Deld

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Pune Vidyarthi Grihas

COLLEGE OF ENGINEERING, NASHIK 3.

30th June 2017

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Entity B Entity C Entity D

Architecture Architecture Architecture

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1. Operators: AND, OR, NAND, NOR, XOR, XNOR, NOT,

1. Special Notation Symbols 8

6. Long line can be continue over more than one line.

7. A line starting with two adjacent hyphens is treated

9. TIME is predefined type.

10. It allows arrays to be indexed in either direction

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12. A basic identifier in VHDL is composed of a sequence of

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14. Boolean operators AND, OR, NAND, NOR, XOR,

15. A system library ieee library is provided which

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It is hardware abstraction of an actual digital

It may be decomposed into its constituents lower

A design must have at least one entity.

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ENTITY my_ckt IS Datatypes:

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PORT(SET, RESET: IN BIT;

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Entity Declaration describe the external view of

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An architecture body is composed of two parts

Declarative part cab be used to declare signals, user

The component declaration lists its name, mode and

For each component, component instantiation

This circuit has two

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Component instantiation statements

These statement execute concurrently i.e. in

The statement contained in the model assigns the

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Signal assignment statement is executed whenever a

Time delay can also be introduces in the signal

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ARCHITECTUER df_and2 OF and2 IS

ARCHITECTUER df_or2 OF or2 IS

ARCHITECTUER df_not2 OF not2 IS

ARCHITECTUER df_xor2 OF xor2 IS

ARCHITECTUER df_rsff2 OF rsff IS

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It uses keywords WHEN and ELSE, boolean operators

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It begins with the keyword WITH, specifies the

LIBRARY ieee; STD_LOGIC type is a standard

A process statement is the main mechanism used to

The process statement starts with keyword PROCESS

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