Stepper Motor

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Steprmotor is
Port ( clk,dir,rst : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR (3 downto 0));
end Steprmotor;

architecture Behavioral of Steprmotor is

signal clk_div:std_logic_vector(15 down to 0);
signal shift_reg:std_logic_vector(3 down to 0):
begin

process(clk)
begin
if(rising_edge(clk))then
clk_div<=clk_div+'1';
end if;
end process;

process(rst,clk_div(15))
begin
if(rst='1')then shift_reg<="0001";
elsif(rising_edge(clk_div(15)))then
if(dir='1')then
shift_reg<=shift_reg(0)&shift_reg(3 downto 1);
else
shift_reg<=shift_reg(2 downto 0)&shift_reg(3);
end if;
end if;
end process;

dout<=shift_reg;
end Behavioral;
 DC MOTOR

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dcmotor is
Port ( dir,clk,rst : in STD_LOGIC;
row : in STD_LOGIC_VECTOR (0 to 3);
pwm : out STD_LOGIC_VECTOR (1 downto 0);
rly : out STD_LOGIC);
end dcmotor;

architecture Behavioral of dcmotor is

signal countr: std_logic_vector(7 downto 0);
signal div_reg: std_logic_vector(16 downto 0);
signal ddclk, tick: std_logic;
signal duty_cycle: integer range 0 to 255;
begin

process (clk, div_reg)

begin
if (clk'event and clk='1') then
div_reg<=div_reg+'1';
end if;
end process;

ddclk<=div_reg(12);
tick<=row(0) and row(1) and row(2) and row(3);

process(tick)
begin
if Falling_edge(tick) then
case row is
when "1110" => duty_cycle<=255;
when "1101" => duty_cycle<=200;
when "1011" => duty_cycle<=150;
when "0111" => duty_cycle<=100;
when others => duty_cycle<=100;
end case;
end if;
end process;
process(ddclk, rst)
begin
if rst='0' then
countr<=(others=>'0');
pwm<="01";
elsif(ddclk'event and ddclk='1') then
countr<= countr+'1';
if countr>=duty_cycle then
pwm(1)<='1';
end if;
end if;
end process;

rly<='1' when dir ='1' else '0';

end Behavioral;