Electrostatic Discharge in Semiconductor

Devices: Protection Techniques

JAMES E. VINSON AND J. J. LIOU, SENIOR MEMBER, IEEE

Invited Paper

Electrostatic discharges (ESDs) are everywherein our homes
and businesses. Even the manufacturers of the electronics experi-
ence ESD failures in their factories. Electronic devices are sensitive
to ESD. ESD results in failure of our computers, calculators, and
car phones. There are ways to protect these sensitive components.
This paper looks at ESD protection from a two-pronged approach:
reducing the likelihood of having an ESD event and improving the
robustness of the devices themselves. The first approach focuses on
reducing the amount of charge that is developed and controlling the
redistribution of any charges that are developed. The second ap-
proach reviews ways to improve the circuit robustness by improving
individual circuit elements and by adding additional elements for
charge flow control and voltage clamping.
KeywordsAir ionizers, electrostatic discharge, ESD protection,
ESD safe packaging, ESD safe workstation, floor finishes, input
protection, static clamps, static dissipation, transient clamps.
I. INTRODUCTION
A. ESD Environment
Electrostatic discharge (ESD) is a subclass of the failure
causes known as electrical overstress (EOS). This class ap-
plies electrical stimulus to a part outside of its designed tol-
erance. ESD is a charge driven mechanism because the event
occurs as a result of a charge imbalance [1]. The current in-
duced by an ESD event balances the charge between two ob-
jects. Our previous paper [2] gave an overview on the various
aspects of the ESD event. This paper will cover the specifics
of protection techniques for preventing the ESD damages
in semiconductor devices. The ESD event has four major
stages: 1) charge generation; 2) charge transfer; 3) charge
conduction; and 4) charge-induced damage. ESD protection
looks first to minimize the charge generation and slow the
Manuscript received February 26, 2000; revised June 20, 2000.
J. E. Vinson is with Reliability Engineering, Intersil Corporation, Mel-
bourne, FL 32902 USA (e-mail: jvinson@intersil.com).
J. J. Liou is with the Electrical and Computer Engineering Department,
University of Central Florida, Orlando, FL 3286-2450 USA (e-mail:
liou@pegasus.cc.ucf.edu).
Publisher Item Identifier S 0018-9219(00)10760-1.
charge transfer by controlling the environment where parts
are handled and stored. The next aspect focuses on the circuit
elements. Here, protection techniques look for ways to make
the individual elements more robust to the currents induced
while at the same time adding additional circuit elements to
alter the conduction paths the charge takes through a circuit.
B. Real-World Events
The movement of objects generates ESD events by pro-
viding the charging mechanism to produce a charge imbal-
ance. No work area is immune to ESD events. The areas in-
clude office environments, homes, laboratories, wafer fabri-
cation facilities, and assembly/test sites. People as well as
equipment generate ESD events. People are charged to high
voltages when they walk across the carpet. If a shock is felt
from the ESD event, then the event had more than 3000 V
of potential [3]. Computer monitors in homes and offices
are sources for inductive charging of parts and produce ESD
events in parts and equipment used around them [4].
These two sources of ESD generated eventspeople
and equipmentproduce current discharges that are quite
different in shape, peak current, and duration. In fact, ESD
from a person can be very different based on the footwear
worn, whether they are sitting or standing, and whether they
have a metal object (tool) in their hand. Chase and Unger,
in [5], showed that the selection of footwear defines the
persons capacitance which ranged from 100 to 500 pF. If
4 C were developed by the charging process, the induced
voltage would range from 800 V for the 500-pF case to
4000 V for the 100-pF case. The generated voltage is the
driving force behind the ESD event. The capacitance of a
person could double if they were sitting versus standing
[6]. In addition to these inconsistencies, Calvin et al., in
[7], showed that real-life ESD from people can consist of
multiple discharges with each one progressively smaller in
magnitude. Holding a metal object during an ESD event can
lower the series resistance of the discharge increasing the
current generated by the event [8][10]. The large variability

00189219/00$10.00 2000 IEEE

1878 PROCEEDINGS OF THE IEEE, VOL. 88, NO. 12, DECEMBER 2000
Fig. 1. Human body model ESD schematic diagram with parasitic elements.
Fig. 2. HBM ESD current waveforms resulting from parasitic elements.
in real-life ESD events makes it clear that a set of standards
is needed to judge a circuits response to ESD.
The integrated circuit industry has standardized on three
basic models related to ESD events. The models are based
on the charge storage location. These are: 1) the human body
model (HBM); 2) the machine model (MM); and 3) the
charged device model (CDM). Each model is described by
standards or draft standards. The ESD Association of Rome,
NY, publishes one such group of standards. The three stan-
dards are ESD STM5.1-1998 Sensitivity TestingHuman
Body Model (HBM)Component Level; ESD S5.2-1999
Sensitivity TestingMachine Model (MM)Component
Level; and ESD DS5.31996 Charged Device Model
(CDM) Nonsocketed ModeComponent Level. These
standards were accurate at the time of this writing, but the
reader should contact the ESD Association directly for the
latest revision. These methods of testing are intended to
simulate the average ESD event. As such, results obtained
using these test methods are for comparisons of the robust-
ness of various designs and not as an absolute measure of a
parts capability in the real-world environment [11].
VINSON AND LIOU: ELECTROSTATIC DISCHARGE IN SEMICONDUCTOR DEVICES
A schematic diagram of the HBM model is shown in Fig. 1
[12], [13]. A plot of the current pulses as a function of these
elements is shown in Fig. 2. The inductance controls the rise
time of the current pulse. The parasitic capacitor C1 provides
current overshoot. The parasitic capacitor C2 can generate an
additional current pulse if the device under test (DUT) has a
protection element that suddenly changes state such as a sil-
icon controlled rectifier (SCR). C2 represents the test board
capacitance. Modern ESD testers are designed to minimize
these parasitic elements however many times the user designs
and builds the DUT socket for their device. The user must
take care not to introduce stray impedance into the current
path, or undesired results would occur.
C. Damage Caused
The currents induced by ESD are extremely high. In Fig. 2,
the HBM-generated current peaks are in excess of 2 A. CDM
and MM ESD generate currents even higher than this. These
current levels are in excess of the normal operational cur-
rents. It is this current, directly or indirectly, that causes the
1879

Fig. 3. Current-induced damage mechanisms.
physical damage observed in an ESD failure. Direct damage
is caused by the power generated during the event. It melts
a section of the device causing failure. Indirectly, the current
generates a voltage by the ohmic resistance and nonlinear
conduction along its path. Small voltages are generated when
junctions are operated in forward bias mode, but large volt-
ages are generated when they are in reverse bias mode. The
reverse bias conduction causes thermal damage at lower cur-
rent levels because the power dissipation is higher from the
higher voltage across the junction. In addition, the voltage
generated by this event weakens dielectrics by charge injec-
tion. The limiting case for this charge injection is dielectric
rupture.
Electrical testing of damaged parts shows increases in
leakage current. The high currents generated during an
1880
Fig. 4. Voltage-induced damage mechanisms.
ESD event damage electrical junctions as well as rupture
dielectrics materials. The damage caused by ESD is a result
of five damage mechanisms. More than one damage mecha-
nism may be active in a single failure. The current induced
damage mechanisms are thin-film fusing, filamentation,
and junction spiking. The voltage-induced mechanisms are
charge injection and dielectric rupture. These mechanisms
are illustrated schematically in Figs. 3 and 4 for the current-
and voltage-induced mechanisms, respectively. An overview
of these damage mechanisms is presented here.
Thin-film resister damage is shown in Fig. 5. This is a
photo of the input structure on a silicon-on-sapphire (SOS)
logic part. This photo illustrates a limitation of this design.
The ESD current entered the bond pad and traveled through
the resistor to the active device. The 90 bend in the resistor
caused current crowding along the inside edge of this resistor.
The temperature of the polysilicon rose by joule heating until
it melted and damaged the resistor. The inside edge no longer
conducts. The resistor fused at this point. It is important to
consider the large currents present during an ESD event and
lay the structure out to account for the larger currents. Sharp
corners should be avoided for both current paths and voltage
fields. The sharp corners cause current crowding as well as
high electric fields. High electric fields increase the proba-
bility of having charge injection and dielectric rupture.
Filamentation damage is difficult to see in a transistor. It is
typically seen based on the electrical signature. A degraded
PROCEEDINGS OF THE IEEE, VOL. 88, NO. 12, DECEMBER 2000
Fig. 5. Blown polysilicon resistor.
trace is observed resulting in a leaky junction. The ex-
treme case of filamentation is junction spiking. This is illus-
trated in the zener diode of Fig. 6. Fig. 6 shows the residual
metal left at the surface of the device. The device was thinned
from the backside and the silicon removed. This photo was
taken from the backside. This device experienced an EOS
event that allowed the metal to flow from the cathode con-
tact to the anode contact shorting the zener diode.
The first voltage generated damage mechanisms is charge
injection. This failure will not leave a physical damage site
observable by typical deprocessing techniques. The charge
state of the dielectric material changes. These damage sites
are typically reversible by an unbiased bake or ultraviolet
light irradiation. Both of these techniques allow the trapped
charge to be recombined. A junction with a trapped charge
becomes leaky. This may be mistaken for filamentation
damage. The main difference is that filamentation damage
cannot be bake recovered. If significant charge is injected at
a localized site, the dielectric will rupture. An oxide rupture
site is shown in Fig. 7. The rupture site was enhanced by a
silicon etch, making it more clearly visible.
II. PROTECTION REQUIREMENTS
A. The Need
A typical laboratory, manufacturing floor, or wafer fabri-
cation area is capable of generating ESD voltages ranging
from several hundreds of volts to well over 20 000 V if no
controls are put in place. This is caused by the people and
equipment used in the area as well as the atmospheric en-
vironment of the lab. The people are charged as they walk
across the synthetic carpet and tile. Triboelectric charging
applies a charge to their shoes, inducing a charge on their
body. More details about the different charging mechanism
is contained in our first paper [2]. The key aspect about the
environment is the amount of humidity in the air. The amount
of moisture in the air defines its electrical resistance. In dry
areas, larger charges can build up before they are dissipated.
This increases the risk of ESD damage. We have all experi-
enced this in winter, when it is easier to shock yourself while
walking across the carpet and touching a doorknob.
VINSON AND LIOU: ELECTROSTATIC DISCHARGE IN SEMICONDUCTOR DEVICES
Fig. 6. Zener diode with junction spiking.
Fig. 7. Oxide rupture in capacitor oxide from ESD.
The manufacturing of integrated circuits consists of many
steps, but these can be grouped into functional areas. The
first grouping is wafer fabrication. Our earlier paper [2] de-
scribed some of the effects charge generation and ESD can
have on an IC. These include particle contamination caused
by electrostatic adhesion and damage to masks used to pro-
duce the circuits as well as damage to the circuits themselves.
The next grouping of operation is assembly. This functional
area takes the wafers and separates the individual circuits,
placing each of them in a package. Even in this operation,
the die cannot escape large potential voltages. One example
occurs during the die separation process. Typically, a wafer
is placed on a sheet of sticky film and then the die are sawn
apart. The sticky film is an insulator and does not contami-
nate the wafer or die with foreign materials. The sticky nature
of the film keeps the individual die in place during sawing.
The die must now be removed from the tape, as shown in
Fig. 8. The film is stretched to provide larger separation be-
tween the die and a vacuum wand selects the die for use.
The removal process triboelectrifies the tape and die. Without
proper protection, voltages in excess of 10 000 V can occur.
The high voltages can attract particles to the die surface as
well as produce an ESD discharge event damaging the cir-
cuit. Protection from these two phenomena comes in the form
of air ionizers. These devices bathe the work area, the film,
and the die with a balance of negative and positive ions to
neutralize any developed charge.
1881

Fig. 8. Die remove from film used during sawing.
It is important to compare the voltage levels generated by
ESD with the sensitivity levels of unprotected devices. This
comparison is necessary to determine the impact of ESD. An
example of how sensitive unprotected devices are is found in
the MOSFET. The gate oxide thickness in these transistors is
shrinking with each generation. A voltage of 10 V is capable
of rupturing a 10-nm-thick gate oxide under dc conditions.
In an transient condition this voltage will be slightly higher
(15 V). In either condition, it is easy to see why handling
an unprotected device in an unprotected environment is very
dangerous. The voltages produced are many orders of mag-
nitude greater than the devices are able to handle. They can
be easily damaged. It is important to include ESD prevention
in a work area and ESD protection on the circuit.
B. ESD is Probabilistic
ESD is a probabilistic event. The environment where the
parts are handled has a probability of generating a voltage. It
can be visualized as each voltage level has a probability of
being found at any point in time. This aspect is represented
in Fig. 9 by curve A. Four key items define the probability
of finding a selected voltage. The first is the type of pro-
tection equipment present to control static charges. This in-
cludes room ionizers, local ionizers, as well as ESD smocks
and wrist straps. The second aspect of this probability is the
reliability of the protection equipment. If any piece of pro-
tection equipment fails the probability of having a higher
voltage generated increases. The third aspect is the main-
tenance practice to keep the protection equipment working
at peak performance. Some topical antistatic coating must
be renewed on a periodic basis to keep them working well
[14], [15]. If the maintenance intervals are too long, then
the coating will not dissipate the charges as well and higher
voltage levels will result. The last aspect determining the
probability, and the most important, is the employees dis-
cipline to use the protection equipment properly. It does not
matter how well the equipment functions or how much equip-
ment is present; if it is not used properly, then it cannot per-
form its function.
Another aspect in defining the probability of having an ESD
event create a damaged unit is the ability of the device to with-
standanESDeventofafixedmagnitude.ThisisshowninFig.9
as curve B. As we saw earlier, an unprotected gate oxide is
very poor at protecting itself. A typical way of providing pro-
tection for this sensitive element is to put an ESD protection
structure in series with this gate oxide. The ESD event must
1882
Fig. 9. ESD as a probability function.
travel through the protection structure to reach the gate oxide.
The job of the protection structure is to clamp the voltage gen-
erated by the charge as well as divert the charge away from
sensitive elements. The capability of this protection structure
is the circuits first line of defense. Three items impede the
protection elements ability to provide a level of protection.
The first is in its design. The design has a limitation of its own.
It is only capable of providing protection up to a fixed level
based on its size, layout, and schematic diagram. The second
is in the variability of the process. The last aspect is the de-
fect density within the process. Process variability relates to
how well the electrical parameters of the protection circuit are
controlled from one wafer fabrication lot to another and from
one wafer to another. Consistency is important for protection
elements. Each one must look like every other one. The best
protection element can be rendered inoperative if a defect is
present [2]. The current or voltage induced by an ESD event
is focused at the defect rather than dissipated uniformly. This
focused energy damages the device more quickly, resulting
in a lower ESD threshold. Uniform electric fields and current
conduction are important for optimum protection.
TheshadedareaofFig.9iswheretheenvironmentpresentsa
voltagethatishighenoughtocausedamagetotheproduct.This
overlap determines the probability of failure. It is difficult to
quantify these two distribution functions. This discussion was
presented more as an aid to the reader to understanding that
both aspects of protection must be addressed. The goal of any
protection activity is to minimize the overlap area. The envi-
ronment must be made safer for devices as well as the devices
themselves must be made more robust to an ESD event. Re-
moving charge-generation sources as well as providing a con-
trolled discharge path for any charges that are developed im-
prove the environment. Adding additional circuit elements to
divert the charge in an ESD event as well as improving the un-
protected elements ability to absorb charge improve the ESD
thresholds of circuits. The administration of these two activ-
ities is the topic of the next section, followed by a review of
environmental protection and circuit protection.
III. ESD ADMINISTRATION
Several authors [3], [16][22] have revealed how they
implemented an ESD protection program at their facility.
A common theme was that fixing the environment was
not enough to ensure success. A successful ESD program
requires a two-prong approach to reduce the occurrence
of ESD events and to harden the circuits to these events.
PROCEEDINGS OF THE IEEE, VOL. 88, NO. 12, DECEMBER 2000
Reducing ESD events includes reducing both the number
of occurrences and the magnitude of each occurrence. The
probability discussion illustrates this. It was also clear from
these papers that starting and sustaining an ESD program
is not a small feat and should not be entered into without a
strong commitment from the people that control the money,
time, and equipment necessary to be successful. Welscher et
al., in [3], detailed why ESD will be a continuing problem.
They attribute it to the continuing advancement of tech-
nology producing ever more sensitive components and the
automation of manufacturing coupled with the delay in
production of ESD controls to keep up with this automation.
There are three major aspects to a successful ESD protection
program. These are commitment, implementation, and con-
tinuous improvement. Each of these aspects is continuously
renewed throughout the life of the program.
A. Organizational Commitment
The most important aspect of setting up and maintaining
an ESD program is the commitment from management to
support it and the employees to implement it. This includes
all levels of management and all functional areas. Design
engineering and manufacturing must agree. Areas have dif-
ferent responsibility but the same goalreduce ESD losses.
ESD protection must involve all areas of the manufacturing
process. The process starts with venders of raw materials
used in building the product and the supplies and equipment
that must be used in its manufacture. It ends with the product
being shipped to the customer and how he receives and uses
the product. A supportive organization is distinguished by
how the circuit and process designers view ESD circuit pro-
tection. Supportive organizations have embraced the need for
ESD and are willing to abide by the rules and procedures set
forth for ESD protection. They work closely with the ESD
steering committee to design-in protection to the circuits
architecture. In this cooperative environment, the circuit is
properly protected. An unsupportive organization views ESD
requirements as an obstacle to overcome. They may make an
attempt to include ESD protection, but it always takes up too
much die area or impairs the circuits performance. When
the circuit does not meet the ESD objective the design team
declares it is good enough because it does not have time to
fix it and make the market window. Many times the desire for
quick revenues overrules the need to fix the circuit. Later in
the products life cycle, manufacturing is stuck with the yield
loss and cycle time stretchouts because of ESD failures. This
results in the customers poor image of the delivery process
and the reliability/quality of the parts. In the customers fac-
tory, the parts become harder to handle because of the extra
ESD safety precautions needed to keep the products from
failing. Managements support does not mean just lip ser-
vice, but a commitment to supply the necessary personnel
and resources (including time) to get the job done correctly.
It also means supporting the ESD team to ensure compliance
to the plan when necessary.
Compliance to ESD requirements is a must. They are not
ESD suggestions, but ESD requirements. The need for ESD
threshold testing and design requirements must be formal-
VINSON AND LIOU: ELECTROSTATIC DISCHARGE IN SEMICONDUCTOR DEVICES
ized into the product design process though a design spec-
ification. This allows the requirements to be communicated
to all designers uniformly. To aid in meeting these require-
ments, the designer must be given the tools and structures to
use and simulate ESD events. These tools are used to predict
ESD thresholds in the design process. When a design does
not meet the requirements, a corrective action plan should be
developed to address how the part can be improved. Failure
analysis (FA) is a necessary part of this process. FA shows
where the weak link is in the circuit. A workable action plan
with defined dates of completion is required. This plan de-
fines what has to be done, who is responsible, and when it is
to be completed. It may also detail whether the part can be
sold as is and what extra measures are required to manufac-
ture the units with minimum yield loss due to ESD damage
while the fix is being developed.
Getting management approval may require a cost analysis
or similar review to help them see the benefits of imple-
menting an ESD program. These cost savings and benefits
included higher yield, improved outgoing quality, better cus-
tomer satisfaction, and decreased field failures. Preliminary
funding may be required to perform a site survey and com-
petitive analysis to define what the cost and savings would be
as well as determine what the competitors are doing. During
this review, it is important to document where improvements
are needed so this survey can be used as the basis of an imple-
mentation plan. The survey should also measure the cultural
aspects of the plan and gauge the attitude of the workforce
and management about ESD and its impact. The cultural as-
pects may be the most difficult factors to change.
To gain and maintain commitment from management and
the organization, it is important to communicate the bene-
fits of having and maintaining a fully implemented ESD pro-
gram. Payback and cost savings are key drivers for funding
any new project. A review of the failure causes both in the
factory and in the field can show a significant number of fail-
ures attributed to ESD damage. Several authors have reported
greater than 25% of all failures related to EOS damage [2],
[23]. Reduction in these product losses and the subsequent
rework savings are easily quantified. A more difficult cost
savings to quantify is the loss of confidence from your cus-
tomers because of ESD related failures. These failures cause
shipment delays and reworks.
Routing reports showing ESD failures per factory turns
or a similar measure is a metric one could use to show im-
provement with respect to ESD robustness. These metrics
and other information help rally support for the ESD pro-
gram and must be routinely communicated. The ESD pro-
gram committee must continue selling itself and its impor-
tance to the organization. Just like a company without ad-
vertisements will lose market share, so will an ESD program
lose support without feedback to its usefulness.
B. Implementation Plan
From the site survey, a detailed and exhaustive implemen-
tation plan is devised. It is important not to develop a piece-
meal plan. Each part of the ESD program is an element of
the whole program and not a piece unto itself [19]. The pro-
1883
gram is only as effective as its weakest piece [20]. It is im-
portant to set realistic goals for the areas and for the circuits.
The goals should be obtainable with the tool set available. If
higher threshold levels are required in a circuit to meet the
voltage levels present in an area, then improvements must be
made in the circuit protection. Research and development of
new protection elements for designers to use must be a part of
the implementation plan. If better protection is not possible,
then that area must have more equipment and procedures in
place to lower the voltages generated. The goals may not be
the same for all functional areas as well as for all types of
circuits. It depends on what types of devices are handled in
each area as well as what the device type is. Some devices
are easier to protect than others. It is equally important to
engineer the program so human error is minimized. Dangel-
mayer in [19], [22] terms this human factors engineering.
Here, he uses the example of a grounding strap on the shoe
to dissipate charge from a person. The strap was difficult to
put on correctly. This made it ineffective in providing the de-
sired protection. The dissipation element was integrated into
a special shoe, allowing all workers to use the equipment cor-
rectly because everyone knows how to put on a shoe.
The ESD Program Committee is a multidisciplined team
composed of representatives from each functional area.
These people are champions of ESD in their respective
areas. They provide feedback to the Committee as well as
give unique insight into the best ways to improve ESD for
these areas. The Committee has a strong technical focus to
assist in developing and reviewing ESD protection elements
and procedures. Their technical focus is on the improvement
of the wafer fabrication process, circuit design, and handling
equipment and procedures to improve ESD in the circuits
that are built. The ultimate goal is reducing the number of
failures caused by ESD to zero.
A common part of each program is a full-time ESD Coor-
dinator. This person acts as a champion for the plan as well
as a consultant for the organization. He is also the Program
Manager for the plans implementation and upkeep. The
ESD Program Committee reports to him. Dangelmayer
in [19] and [22] recommend this person be a part of the
Quality Organization reporting to the corporate staff. This
provides the Coordinator with a global responsibility not
tied to either the manufacturing or engineering organiza-
tions. Communication from the coordinator to management
and the organization is key to the plans success [22]. The
Coordinator must have a wide background and be well
versed in ESD protection as well as program management.
The second most important aspect of an ESD program is
training. Training includes education on how ESD occurs and
what damage it inflicts as well as proper handling of sensi-
tive parts and the use of protection equipment. Our first paper
can serve as an outline for a description of ESD and how it
occurs. Reviews of selected failure analysis reports can be
beneficial to drive home the point about how and what type
of damage can be introduced. Once an operator can asso-
ciate a part they have handled with a type of damage it may
make them more careful. Education should include constant
reminders of the need for ESD safety. These could come in
1884
the form of posters and signs to help remind people that ESD
safety is important. Handbooks are useful as guides to proper
operation of equipment and safe handling practices. A check-
list of things needing to be done can be used. The key is to
keep the information fresh in their minds and make it perti-
nent to the products they are handling. Make the information
personal so they see the importance of following the proce-
dures to protect the parts they are handling.
Centralizing information resources is important to keep
people from repeating mistakes [17]. Lessons learned on
one project should be easily assessable to the next project
whether or not team members are shared between projects.
This level of documentation takes discipline of the team
but is time well spent if it saves several weeks of learning
by the new team. One aspect of this discipline is for a new
team to seek out previous knowledge rather than trying to
reinvent it all. Build on previous success and learn from
previous mistakes. The explosion of the Internet and the
use of intranets to share information provide an excellent
vehicle to share knowledge between workgroups and an
excellent tool to gather and disperse ESD information. An
internal web server can be set up to enter and retrieve ESD
information. The reader should talk with the local computer
administrator or information technology group about adding
ESD information to a companys internal web server.
Most of the previous discussions were about training for
the people that handle product or come into contact with
product, but this is not the limit of training. These people may
have the most immediate impact but training is also needed
for others; however, it must be tailored to their needs. Man-
agers are trained so they recognize the importance of ESD
safety and continue to provide support in the form of dol-
lars and resources. Designers need to be trained on the best
available protection techniques to use and process designers
should be trained on how to provide protection in the ad-
vanced processes. The key thing here is training is for every-
body, but everybody does not receive the same training. The
content of the training must be targeted toward the group and
focused on bringing about a measurable change in behavior,
not just filling the mind with more information [19].
C. Continuous Improvement
The last aspect of an ESD program is continuous improve-
ment. This aspect is vital to the long-term success of the pro-
gram. If the program stagnates it will die [21]. There are sev-
eral aspects to continuous improvement. These include an
audit program, a failure feedback program, and a technology
improvement program. The first thing people think of when
the word audit is used is an IRS tax audit. Obviously this
is not the type of audit expected here, but some of the same
fears and anxieties can arise. An audit program ensures com-
pliance to the documented procedures and rules. Unfortu-
nately, some auditors use this as an opportunity to display
their power over an individual or group and punish or dis-
cipline them. This atmosphere creates significant tension be-
tween the auditor and the one being audited. It does not result
in the desired action. The auditor is an instructor designed to
PROCEEDINGS OF THE IEEE, VOL. 88, NO. 12, DECEMBER 2000
improve the compliance to the specification and to interpret
the specification [21]. An audit when viewed from this per-
spective is not adversarial and is more likely to accomplish
the desired resultscompliance to the specifications. Audits
help encourage improvements and also spot problems that
can lead to product failure [20]. An example of this is where
a technician, by using the equipment, determines a better way
to use it. The procedure can be updated in the specification
and the improved procedure implemented for all stations to
use. An audit may consist of several stages or levels. Braude,
in [20], recommended a three-stage audit: daily self-checks,
monthly local audits, and a yearly third-party audit. An in-
dependent group should perform the audit whether it is done
internally or externally. The audit results should be posted
and published for accountability purposes.
A failure feedback program identifies where ESD failures
occur and what types of parts are being affected. In some
cases it can also identify what type of ESD event occurred
(HBM, MM, or CDM) to case the failure. The program may
reside in the failure analysis or reliability groups, or it could
be in the quality organization or as a part of the ESD Program
Committees responsibilities. It should encompass both in-
ternal and external failures. This program can produce a good
measure of how effective an ESD program is by showing
the reductions for ESD-generated failures. As the program
matures a reduction in the number of ESD-related failures
should be seen. It may also highlight areas that are weak in
terms of ESD or areas where protection equipment needs ser-
vicing or replacement. This may come in a sudden increase
in the number of ESD-related failures through a functional
area. This helps locate the source of the ESD event so it can
be corrected. The second aspect of this effort is to identify
weak parts from an ESD viewpoint. These may be candidates
for redesign or for special handling procedures. The key as-
pect is that failure analysis should be performed to determine
if ESD is causing yield loss, and these results should be used
to improve the environment or part.
Technology improvements are an important part of contin-
uous improvement. The process and circuits continue to im-
prove in complexity and speed. These improvements make
them more susceptible to ESD damage. If the development
of new protection techniques is neglected, technology will
quickly outstrip the ability to provide protection. The search
for new protection techniques is not limited to the integrated
circuits. New ways of preventing charge generation and con-
trolled discharge of developed charges also evolves. As these
techniques and equipment become available, they should be
evaluated and integrated into the overall strategy if deemed
appropriate. A good ESD program will not focus on one as-
pect of ESD protection, but will provide a unified focus for
all areas.
Improvements in technology include integrating new cir-
cuit elements into the process architecture as well as looking
for weaknesses caused by process advances. A research
and development (R&D) effort to improve ESD should be
a part of the overall organizations research budget. This
effort is focused on development and implementation of
new circuit architectures to provide protection. These topics
VINSON AND LIOU: ELECTROSTATIC DISCHARGE IN SEMICONDUCTOR DEVICES
are discussed later. Improvements in ESD production do not
happen by themselves. It takes a team of individuals and
the resources to experiment with new ideas and designs to
determine the best structures.
IV. ENVIRONMENTAL PROTECTION
An ESD event requires the existence of a voltage differ-
ential between two bodies. If low impedance connects these
bodies, then the voltage is rapidly equalized, leading to
damage of one or both bodies. If a high impedance connects
them, the charge transfer is more controlled and does not
cause damage. These are the two concepts used in environ-
mental controls: minimize the voltage level generated and
optimize the transfer impedance between bodies but do not
allow a condition where someone could be shocked. These
concepts are illustrated in the following sections looking at
the various areas parts are handled during manufacture.
A. Room-Level Controls
Control measures used at the room level are designed to
minimize the voltages developed in a work area. This is typ-
ically a large laboratory, test area, or wafer fabrication area.
The conductivity of the air is the primary line of defense in
these types of area. It is difficult to sustain a charge on an
object if the charge is bled off through the air. There are
two ways to control the airs conductivity: humidity levels
and ionization. The amount of moisture in the air determines
its conductivity. This is easily illustrated by comparing the
ease one can be shocked by static electricity in the winter
versus the summer. In the winter, the air is dryer because it
holds less moisture when it is cold. In a home, this low-mois-
ture content air is heated, allowing it to be even lower rela-
tive humidity. The low-moisture content allows charges to
grow on people without being dissipated. In general, higher
levels of humidity produce lower levels of generated and sus-
tained charge [24][26]. The higher humidity also allows the
charges to be dissipated more quickly. The upper limit on
how humid an area may be is governed by equipment oper-
ational specifications and personal comfort. The typical safe
working range is 30%70% relative humidity.
Another way to control air conductivity is by injecting
conductive species in the air. The charge must be injected
in balance (equal numbers of positive and negative species)
so no net charge is introduced [27]. Room ionizers do this,
as illustrated in Fig. 10. There are two types of air ionizers
based on how they produce ions. These are electrical and nu-
clear ionizers [28]. Electrical ionizers produce ions by corona
discharge, whereas nuclear ionizers produce ions by nuclear
decay [27][29].
Ionizers are more effective at controlling charges than hu-
midity; in fact, ionization can cause a 20 reduction in the
decay time of charge compared to humidity alone [27]. Ion-
izers neutralize objects and people entering a work area as
well as maintain the work area neutral [28]. Ionizers are not
a panacea for charge control but are an important part of a
total ESD program and should be used in conjunction with
other protection techniques [30], [31].
1885
Fig. 10. Ionizers for room-level control of charge generation.
The two most important parameters for ionization equip-
ment are neutralization time and ion balance [31]. Neutral-
ization time is the time it takes to neutralize a fixed amount of
charge. This is a measure of the effectiveness of the ionizer.
The ion balance provides a measure of the ionizers ability to
generate an equal number of positive and negative ions. If an
imbalance occurs, potential gradients will form. This is the
very thing the ionizers try to eliminate! Two other aspects of
ionizers are the generation of stray electric fields and ozone.
Stray electric fields interfere with some sensitive measure-
ment equipment and their effect should be evaluated [31].
Ozone is a byproduct of all ionizers [28], [31]. The produc-
tion levels must be controlled and monitored to ensure a safe
working environment. As with all protection devices, proper
maintenance is a must to keep the ionizers in balance and
produce the correct level of ions for neutralization.
Another room-level control is conductive flooring. Floors
and carpets are major sources of charging in a manufacturing
area [32]. The use of antistatic finishes can reduce charge
generation, but their effectiveness is dependent on the
quality of the installation and proper maintenance [33], [34].
In addition, the footwear chosen should be matched with
the flooring [34]. Chase and Unger in [32] showed leather
shoes to be the best because they had a high capacitance
and low-charge generation. The addition of a toe and heel
ground strap can greatly reduce the voltage levels obtained
[34]. The user should evaluate each flooring/footwear
option carefully. Some antistatic coatings are worse than
commercial floor finishes [32].
B. Workstation Controls
Once the area controls are in place, it is necessary to move
the protection attention to the area where parts are being
handledthe workstation. An example of a workstation is
shown in Fig. 11. The work surface is the main place that
needs attention. The parts rest here waiting further testing or
1886
Fig. 11. Workstation with necessary controls for ESD.
inspection. The surface should neither induce a static charge
on the parts nor provide a rapid discharge path. The most ef-
fective work surface is a static dissipative surface with a sheet
resistance of 10 10 per square [34], [35]. The surface
should be impregnated with conductive material rather than
have a topical spray to make it static dissipative. The top-
ical spray can wear off and may leave residual material on
the parts, causing corrosion [36]. These work surfaces must
be connected to a common ground by a low-resistance con-
nection [4]. The common ground prevents voltage gradients
from developing. The low-resistance connection does not im-
pede fault detectors from removing power should a shock
hazard present itself. If a high resistance is used, the ground
fault circuit may not trip and high voltages could be present
on the work surface shocking the personnel using the work-
bench [4].
The use of conductive work surfaces (stainless steel for
example) presents a hazard for the parts as well as a shock
hazard for people [34]. The part can be rapidly discharged
because the metal surface acts as a large charge sink. The sur-
face can absorb a large amount of charge without changing
its surface potential significantly. With little or no series re-
sistance the part may discharge very quickly, resulting in ex-
tremely high currents and power dissipation.
As we saw with floor finishes and ionizers, proper main-
tenance is necessary for continued performance. The surface
must be cleaned periodically and the connections checked for
proper grounding. If topical sprays are used, they must be re-
newed on a periodic basis.
Other furniture at the workstation needs to be evaluated
for its ability to charge and discharge. The sitting surface of
chairs used at a workstation should neither charge nor in-
duce a charge on the operator. A charged chair can cause the
PROCEEDINGS OF THE IEEE, VOL. 88, NO. 12, DECEMBER 2000

Fig. 12. Person with necessary ESD protection equipment in place.
person to charge by induction as well as cause electromotive
interference (EMI) to radiate from the legs of the chair as the
potential discharges in the seat cushion [37], [38].
Inductive charging is a real concern at the workstation.
Any charged surface can induce a charge on the parts being
worked, causing them to be damaged. Because of this,
all materials that charge and other charged sources must
be removed from the workstation. These include papers,
computer monitors, cups, plastics, and synthetic materials.
A more complete description of inductive charging is found
in our first paper [2].
C. Personal Controls
Part handlers must take special care while doing their jobs.
Fig. 12 shows a person with the necessary ESD equipment in
place. They also must employ special equipment that keeps
the charge levels on their bodies to a low level. The first line
of defense are grounding straps [39][41]. These can be ap-
plied to the wrist and/or shoe. The purpose of these is to re-
move charges that developed on a persons body in a con-
trolled manner. There are two types of wrist straps: contin-
uously monitored and periodically monitored [42]. For the
first, the wrist strap is connected to a piece of equipment
that continuously checks the straps connection to the person
wearing it. The second must go to a special checking sta-
tion to ensure the strap is working properly. The continuously
monitored straps cost more initially but provide a real-time
feedback to the operator if a grounding problem occurs. Lost
work time resulting from the need for periodic monitoring
can provide a payback in about a year for the extra cost.
The ability of the wrist strip to function correctly is largely
dependent on its ability to contact the skins surface [39].
The wrist strap should be in direct contact with the skin.
Body hair, skin dryness, and clothing can interfere with this
contact. There are specially formulated creams that can help
improve the electrical contact. As with all ESD preventative
equipment, it is important that these straps are properly main-
tained.
Clothing can aid in the fight against ESD damage or it
can hinder. People handling ESD-sensitive equipment must
realize that the synthetic fibers used in many clothes generate
charge. This charge can then damage equipment. Sweaters
VINSON AND LIOU: ELECTROSTATIC DISCHARGE IN SEMICONDUCTOR DEVICES
Fig. 13. Protective carrier with conductive inserts.
worn in the winter can charge our bodies just by the normal
movements such as reaching for a tool. The use of special
smocks that have conductive fibers woven into them can help
reduce the risks from this type of clothing [43][46].
Proper training is important for people handling sensitive
equipment or parts. They need to realize that the safety mea-
sures take time to work and should allow time for their bodies
to stabilize prior to picking up a sensitive component. You
should not remove your sweater and then pick up a sensitive
component. Remove your sweater away from the workbench,
then walk over to the workbench and connect the grounding
strap and turn on any other safety equipment. Allow a few
moments for the area to stabilize, and then start working on
the parts.
D. Packaging and Storage
The storage and transportation of parts from one area of
manufacturing to another or from the manufacturer to the end
user are critical areas for protection. The protection measures
come in the form of carriers and containers. At the lowest
level, a part may require a supportive carrier to prevent me-
chanical damage during handling. An example is a clip used
to hold the leads in place during electrical testing, as illus-
trated in Fig. 13. It is important that the clip does not generate
or hold charge. The added complication is that the part must
be tested with the clip in place, so the clip must not alter the
electrical characteristics of the part it is attached to. To ac-
complish this, static dissipative inserts can be placed around
the leads. The resistance is high enough to prevent distortion
of the electrical characteristics of the part but low enough so
any accumulated charge is dissipated in a controlled manner.
The containers may take the form of tubes, bags, boxes,
or reels. Special coatings or metal foils can be used in these
containers to reduce the generated static or provide a shield
against external fields [47][53]. It is important to know
the limitation of protection provided with each method of
transportation. ATT implemented a policy that shipping
tubes could not be used for devices with CDM 200 V and
no tape and reel for CDM 1000 V on corners and 500 V
on all others [3]. Another attribute to consider in selection
of the proper container is whether the coating poses a threat
of contaminating the parts with a foreign substance that may
promote corrosion [36]. A careful study and trial period
should be done for each package style change.
E. Automatic Test Equipment
The increased use of automatic handlers for electrical test
and robotics for automatic assembly has highlighted a defi-
1887
Fig. 14. Temperature rise in a bulk and SOI transistor for a 2000-V HBM pulse; darker gray indicates
hotter region.
ciency with these tools. They generate static charges and can
damage parts [54][60]. The use of plastics and other syn-
thetic parts in the pathway allows triboelectrification to occur
to the parts. Once the parts become charged, they can rapidly
discharge as they come into contact with a grounded test head
or metal surface, resulting in a CDM ESD event. The key is
to realize that the equipment must be properly grounded to
prevent charges from developing on it, and insulators around
where the parts travel must be replaced with static dissipative
or antistatic material [57], [58]. The use of local air ionizers
may aid in reducing the charge levels produced if insulators
are required for proper operation of the equipment [61].
V. CIRCUIT PROTECTION
The first thing to remember when evaluating a circuit or
process for ESD robustness is that ESD is a charge-driven
event [1]. The movement of that charge or the current pro-
duced causes the damage. It does this by two effects: Joule
heating and charge injection. The current passing through re-
sistance in the current path causes joule heating. This heats
the structure, resulting in damage. The resistance in the cur-
rent path also causes the second aspect. As the current passes
through these resistive elements, a voltage drop proportional
to the current and resistance is established. This voltage cou-
pled with the geometry yields the electric field present in the
structure. The electric field causes charge injection and di-
electric rupture. These two aspects, heat generation and elec-
tric field strength must be minimized to provide robust circuit
to ESD events. Circuit protection involves much more than
just the schematic of a protection network. It also encom-
passes the wafer fabrication process, circuit elements, and
1888
their interaction with the layout. All of these play into circuit
protection and each will be discussed in the following sec-
tions.
A. Wafer Processing Issues
The first step in developing a circuit protection strategy
is to assess the technology used to manufacture the part.
Each technology has strengths and limitation. For example,
technologies that use insulated substrates to improve perfor-
mance [silicon on sapphire (SOS), silicon on insulator (SOI),
or gallium arsenide (GaAs)] have difficulty removing the
heat that is produced by an ESD event. This is illustrated in
Fig. 14. The same size circuit element was used with the only
difference being the insulating substrate rather than a bulk
substrate. The SOI device has a temperature rise of 300 C
more than the bulk transistor for the same discharge energy
and the temperature contours are grouped much tighter. The
heat is generated by the current flow during an ESD event.
As this current flows through the reversed biased drainbody
junction, the electrical insulation acts as a thermal barrier.
This lowers the heat flow and thermal mass that can absorb
the energy, making these technologies more difficult to pro-
tect.
Not only is the heat flow an issue, but also electric field
is important. Fig. 15 shows the electric field at the gate edge
for a LOCOS (local oxidation) bulk transistor and an SOS
transistor. The SOS transistor is built on an island of silicon
called a silicon mesa. The poly gate extends along the edges
as well as on the top. At the corner of the mesa, the gate
oxide has the highest field. This is the most likely point of
failure. The sidewall slope can be improved to minimize this
PROCEEDINGS OF THE IEEE, VOL. 88, NO. 12, DECEMBER 2000

Fig. 15. Electric field distribution in the gate oxide between bulk
LOCOS transistor and SOS transistor at transistor edge.
Fig. 16. Circular gate structure used on SOS protection elements.
field but at the expense of larger mesa size and increasing
the parasitic effects of the side wall transistor. This type of
transistor cannot be used in an ESD protection circuit. It is
too sensitive to voltage transients. A more effective design is
to use a circular gate structure, as shown in Fig. 16. In this
design, the gate does not cross the mesa edge.
The continuing technological advancement in the IC
industry also stands in the way of ESD protection [62]. The
technology may scale to higher levels of integration but the
sources of ESD, like human beings, are not scaling. They
pose the same threat to a more sensitive device. Four areas
of scaling make a technology more sensitive to ESD events.
These include interconnect lines, junction depths, oxide
thickness, and the activation of parasitic devices. Scaling
is the reduction of feature size to improve integration and
performance. These advances have a negative effect on ESD
performance. Packing more transistors into a smaller space
requires the interconnecting lines to be scaled. These finer
lines can handle less current. Several authors [63][71] have
discussed metal lines ability to withstand different current
stress; however, Vinson, in [71], discusses a physics-based
model that is appropriate for the adiabatic case such as an
ESD event. This is discussed in more detail later.
The junctions formed in the process are also affected by
scaling rules. Junctions typically become shallower as the
process scales. This can cause problems in diffused resistors
and cross-unders. The shallow junctions are more easily
spiked (metal penetrating the junction shorting it out) if
ESD current flows through them. Diffused resistors should
be formed in a well of similar doping so if the metal does
spike through the more heavily doped layer, the spike will
not short out the isolation. This is illustrated in Fig. 17 for
an n-well process.
VINSON AND LIOU: ELECTROSTATIC DISCHARGE IN SEMICONDUCTOR DEVICES
Fig. 17. Diffused resistor built in an n-well to improve ESD
tolerance to junction spiking.
Fig. 18. Excessive voltage generated because of high bus and
clamp resistance during event.
In a similar fashion, the gate oxides scale and, to a smaller
degree, so do the interlevel oxides. As mentioned earlier, the
electric field is an important aspect of the damage process.
A thinner oxide produces a higher electric field for the same
voltage level. This allows dielectric rupture to occur at lower
voltages. There is not much that can be done to strengthen
a dielectric except use one with a higher dielectric strength.
Extra elements must be included to clamp the voltage levels
below the rupture strength. In addition, one should pay
careful attention to the resistance of the ESD current paths.
If the internal resistance of the clamp and bus structures
are too high, internal voltages are generated. These could
rupture dielectrics. This aspect is illustrated in Fig. 18. If
the diode is made too small, its external voltage rises above
the breakdown of the gate oxide resulting in rupture. It is
best to avoid thin gates on inputoutput (I/O) pins and also
minimize bus and component resistance. The metal bus
line must be kept from melting. If it melts, the dynamic
resistance doubles and contributes to damaged oxides [71].
The last aspect of scaling is the most difficult to analyze.
As geometry shrinks and spacing between devices decreases,
parasitic transistors may form. These parasitic elements may
not be present during normal circuit operation but will be-
come active and conduct because of the high currents and
high bias applied during an ESD event. A conservative ap-
proach is needed in spacing where areas of opposite polarity
diffusions are close to each other. Look for parasitic bipolar,
MOS, and SCR structures in the layout.
The last aspect of wafer processing issues deals with
the effect of process enhancements on ESD robustness.
Three recent advances that can degrade ESD performance
are LDDlightly doped drains used to improve hot carrier
performance; silicided junctions used to reduce contact
resistance; and thin epitaxial starting material used to reduce
1889
Fig. 19. NMOS transistor with LDD implant and silicided drain
and source regions.
latch-up susceptibility. The LDD structure is illustrated in
Fig. 19. The lightly doped drain area reduces the electric
field at the oxide surface. This reduces the generation of hot
(high energy) carriers at the surface. Some of these hot
carriers can be injected in the oxide shifting the transistor
threshold. The LDD structure gives rise to added resistance
in the channel and also produces higher holding voltage once
snapback is triggered. Both of these reduce the ESD current
handling ability of the transistor [73][75]. Correcting the
effects of LDD implants on ESD protection element requires
that the LDD implant be blocked or carefully engineered to
account for the high currents during an ESD event.
A silicided transistor is also illustrated in Fig. 19. The sili-
cide is a thin layer of tungsten, titanium, or cobalt deposited
on exposed silicon and heated to form a silicide. The sili-
cide is a thin layer of low-resistivity material at the surface.
It is typically on the order of a few hundred or a few thou-
sand angstroms, depending on the process. The current flows
mainly in the silicide layer because of the high ratio in resis-
tance between the silicide and the silicon. The low resistance
of the silicide does not allow the current to spread well across
the transistors full width. It tends to crowd in a small portion.
Because of this, it is recommended that a silicided transistor
be kept narrow in width ( 30- m) to more easily balance the
current across the width [76]. Another technique is to mask
off a section of the drain so no silicide is present between the
contacts and the gate edge. This adds a small resistance in
series that provides a ballast resistor to aid in balancing the
current.
The use of thin epitaxial material is another example
of how process improvements degrade ESD performance.
Snapback is caused in n-MOSFETs when lateral currents
trigger on a parasitic n-p-n transistor. This is illustrated in
Fig. 20 for both thick and thin epitaxial silicon. An epitaxial
layer of silicon is grown on top of heavily doped silicon to
encourage the vertical current path with all of the lateral
currents flowing in the heavily doped layer. Lateral currents
produce voltage drops from the current flow and the silicon
resistance. This voltage can bias the bodysource diode
triggering on the n-p-n transistor. By thinning the epitaxial
layer, the effective resistance is reduced so a higher current
is required for latchup. The triggering of the parasitic bipolar
into snapback is also what takes the transistor into a lower
power dissipation mode during an ESD event. If the trigger
current increases, so does the power dissipation, making the
transistor less robust to an ESD event. The gain or beta of
this parasitic bipolar element contributes to the snapback
1890
Fig. 20. Thin and thick epitaxial layers effect on latchup and ESD
performance.
characteristics. The process architecture determines the
characteristics of this element. An example of this behavior
is presented later in the paper.
It is clear that all aspects of wafer fabrication need to be
evaluated with regard to how these changes affect the ESD
performance of the circuit elements and parts built on this
process. These effects must be considered during the design
of the process and its integration into the design and layout
tools used to bring a circuit into silicon.
B. Circuit-Level Issues
The entire design team, including designers, marketing,
manufacturing, reliability, and the end customers, must re-
alize that tradeoffs are required when designing ESD into a
circuit. Areas of concern cover the input impedance, perfor-
mance of the circuit, and the die size. A bare circuit (smallest
die size, no protection elements) typically has a very poor
ESD performance. As we will see in a later section, ESD
performance is improved when circuit elements are added
to divert the charge flow away from sensitive elements and
to clamp voltages generated by this charge. These added ele-
ments increase the input impedance. Added input impedance
is especially not tolerated for very fast transitioning signals
because ESD protection networks look like a low-pass filter.
Fig. 21 shows a typical ESD protection element found on an
input pin. The element closest to the gates of the MOSFETs
clamps the voltage to a level low enough to protect the gate
oxide from rupture. The current flow is through the resis-
tance that allows a voltage drop from the input further pro-
tecting the gate. A supply clamp (not shown but discussed
later) completes the circuit to a common pin. This circuit
presents itself as an filter to any input waveform. Higher
frequencies are shunted to the supply pins where lower fre-
quencies are passed to the gates. Fig. 22 shows the impedance
as a function of input frequency for a sine wave input. The
current handling capability of the diodes and therefore the
ESD level obtained is largely dependent on the diode size.
Larger diodes provide better heat dissipation as well as lower
on resistance. The problem is larger diodes also have higher
capacitance. This causes larger amounts of the input signal
to be shunted to the supply pins. There is a tradeoff between
PROCEEDINGS OF THE IEEE, VOL. 88, NO. 12, DECEMBER 2000

Fig. 21. Simple input protection network.
the frequency of input signals and the level of ESD protec-
tion. This is most noticeable for very high-frequency circuits
that operate in the RF range.
As mentioned earlier, ESD performance can be improved
by increasing the physical size of an element. This improves
its current and power handling ability. A problem occurs
when a die shrink is required to reduce cost. The cost to
produce one wafer is typically fixed and difficult to change.
The unit cost is made up of the wafer and manufacturing
cost amortized over the number of good die per wafer. The
number of good die per wafer is dependent on the yield
and the number of gross die on a wafer. The die yield is
driven by defect density, which is a decreasing function of
area. Larger die yield lower than smaller die. When a die is
made smaller by shrinking the geometries of each element,
a twofold cost saving occurs. The yield goes up from the
smaller die and the total number of possible die on a wafer
increases. The problem is the sources of what causes ESD
do not scale with die size. They are fixed and still generate
the same voltages and charge levels. This condition presents
a problem. The ESD protection cannot shrink and give
the same level of protection. ESD protection structures are
typically located around the bond pads. In designs that are
bond-pad limited, the die size cannot shrink without the size
of the pads shrinking. Bond-pad limited means the number
of bond pads required on the die drives the die size. The
circuitry interior to the die does not drive the die size. This
problem can be overcome by using active area bonding.
This is a technique where the ESD protection network is
incorporated under the bond pad. Bernier and Teems, in
[77], and Anderson et al., in [78], report on their experience
with active area bonding. The key thing to remember is
that active area bonding can be done but, again, tradeoffs
and special considerations must be made. Because of the
extra stress placed in the corners of plastic encapsulated die,
active area pads cannot be used in the corners and special
provisions need to be made in the metal layers under the pad
for the force developed during bonding.
The type of circuit function plays an important role in how
easily the device can be protected. As an example, digital cir-
VINSON AND LIOU: ELECTROSTATIC DISCHARGE IN SEMICONDUCTOR DEVICES
cuits are more easily protected than a mixed-signal analog.
Digital circuits typically have one supply voltage. The in-
puts switch between zero and the supply voltage. In the liter-
ature, digital circuits are the types of circuits with very large
(410 KV) ESD threshold levels. Analog and mixed-signal
parts with multiple supply lines and sensitive input stages
are more difficult to protect. The inputs are high-impedance
JFET transistors. Circuit performance requirements prevent
adding input impedance to these pins. Multiple supplies pose
another challenge because now you must provide protection
between all combinations of supplies without introducing
extra leakage on the supply lines. As the number of supplies
increases, this becomes very difficult and adds a lot of area to
the die size. An extreme case is very high-speed RF circuits
operating in the gigahertz frequency range. There is very
little written about RF ESD protection [79][82]. RF ESD
protection follows other ESD design techniques but there are
just more constraints placed on the design [79].
The operational environment also poses a challenge to the
ESD protection designer. A typical environment is consid-
ered benign if the part is operated in a office and does not
come into direct contact with people or other sources of EOS
once it is assembled into a board or system. This is the eas-
iest environment to design for. In this case all of the tools
and devices are available for ESD protection. One problem
environment is where the circuit is to operate in a hot-plug-
ging application. This means that the parts are plugged into
a system while the power is still applied. This type of circuit
requirement adds another level of complexity to the ESD pro-
tection. In a typical application, the ESD protection is trig-
gered when the part is not operational and no power is ap-
plied. The protection circuit is asked to absorb the energy in
the ESD event itself. Most protection techniques incorporate
some form of clamp, as discussed later. The clamp is trig-
gered in response to a rapid change in voltage or current. It
may also trigger at a predefined voltage level. The problem
with hot insertion is the power-up transient seen by the de-
vice is mistaken as an ESD event. In this case, the full energy
available from the power supply is passed into the protection
circuit. The net result is the protection circuit is destroyed
and the part fails. In this type of circuit, the protection clamp
must be a voltage-level triggered clamp or a transient trigger
clamp that is only triggered if the voltage is above the op-
erational voltage. The second clamp is a more effective but
much more complex clamp structure.
Some circuits must work in an environment where the
input voltage levels exceed the supply lines. Examples of
these are multiplexers and switches. The inputs are speci-
fied with a 25-V overvoltage rating, even though the sup-
plies are rated at 15 V. Having inputs exceeding the supply
lines poses challenges because typical protection techniques,
as shown in Fig. 21, cannot be used. One technique is to allow
the inputs to be tied to an isolated bus on chip. This is illus-
trated in Fig. 23.
Parts in a radiation environment also pose limitations on
the designer in their choice of ESD protection circuit. The
transient currents produced by ionizing radiation can trigger
protection networks while the device is operating. This can
1891
Fig. 22. Input impedance of an input protection network as a function of frequency for Fig. 21.
Fig. 23. ESD protection networks for input voltages that exceed
supply levels.
lead to soft errors (changes in functional behavior that are
reset after the radiation event) to physical destruction of
the device. Destruction can occur when the ESD network
turns on with power applied. The energy available from the
supply line is much greater than that found in an ESD event.
The ESD structure is destroyed shorting or opening internal
nodes. The type of physical damage observed is in the form
of melted metal and silicon.
The last area of operational environment is the special case
of line drivers and receivers. This group of parts must operate
in an environment outside of the system and interface with
outside equipment. Typically these devices tie long cables
together. The long length of cable can produce high-voltage
transients and make it more prone to receiving an ESD event.
The pins that connect to the outside world need higher levels
of protection and may be rated at 10 KV rather than 2 or 4 KV.
1892
It is clear that the environment plays a large part in se-
lecting what type of protection is needed and the best way to
implement it. The next section covers the technique used to
incorporate protection into a circuit design.
C. Protection Techniques
Implementing an ESD protection circuit first requires a
review of the building blocks in a process and an under-
standing of the limitation of each element from an ESD per-
spective. Voldman et al., in [72], described the results of a
SEMATECH working group that is defining a strategy for
characterization, evaluation and benchmarking the ESD ro-
bustness of technologies. This group is defining standardized
test structures. The reader is encouraged to keep up with the
progress of this working group.
In a semiconductor wafer process, the elements of interest
include interconnect traces, resistors, inductors, diodes, tran-
sistors, and capacitors. These are the physical building blocks
for a circuit and an ESD protection network. The parasitic
n-p-n in a NMOS FET, for instance, plays an important role
in its high-current behavior. When it goes into snapback, the
voltage across the device drops, reducing its power dissipa-
tion. It is important to know the high-current behavior of the
elements so an adequate protection scheme can be designed.
Metal lines form both the interconnect channels between
circuit elements as well as the inductors used on some
circuits. These metal traces have two issues when viewed
from an ESD perspective: fusing and electromigration
degradation. Vinson, in [71], describes a simple adiabatic
model for predicting aluminum line failure from EOS
phenomenon. He shows the line fails because of an eruption
of aluminum vapor. This is caused by a section of the line
absorbing enough energy to vaporize. The volume occupied
by aluminum vapor is significantly larger than the volume
occupied by solid aluminum. The silicon dioxide cannot
withstand the pressures developed. The model is based on
the enthalpy and temperature-dependent resistivity of alu-
PROCEEDINGS OF THE IEEE, VOL. 88, NO. 12, DECEMBER 2000
minum. The model presented was developed in MathCAD.
For most ESD events, 15 m is adequate to prevent fusing
[76]. Larger lines may be required to minimize the voltage
drop during an ESD event. The large currents can gen-
erate voltages capable of rupturing dielectrics and causing
junctions to break down. As an example, a CDM event
can generate current in excess of 7 A. A metal line with a
resistance of 1 would have 7 V dropped just across the
line not including any protection element. This extra voltage Fig. 24. Energy to blow a typical resistor.
could be dangerously close to the rupture limit of the gates.
The additional voltage from a protection element would
cause the dielectric to rupture.
Larger metal lines may also be required to minimize
the heating of the line. Thermal heating takes the line past
aluminums melting point. Once the event is over, the line
cools very quickly. This action alters the grain structure of
the metal and changes its electromigration performance.
Banerjee et al., in [83], reported on an aluminum metal struc-
ture with TiN top and bottom caps. The EM performance
degraded with ESD. The finer grains produced from rapid
Fig. 25. I V characteristic (high current) for a diffused resistor.
cooling after the event cause this. These two factors must [84]
be taken into account when designing an ESD protection
network, so adequate metal is placed in the ESD network to
allow it to function without reliability degradation.
Resistors are another circuit element to consider. They are
typically used to drop the voltage or as isolation elements in
protection networks. In their thin-film form, they are made
from polysilicon or alloys of NiCr or SiCr. They can also be
diffused resistors made by placing a lightly doped diffusion
in the substrate. Resistors fail in one of two waysfuse
open or short out. Most of the thin-film resistors fail by
fusing open. The energy in the event melts a region, causing
a physical separation of the resistor terminating the current Fig. 26. Cross section of n-channel MOSFET.
flow. Large voltage spikes are induced when this separation
occurs. The voltages spikes are caused by the inductance
into the current path and the very quick decay of the current
flowing in the path once fusing takes place. Fig. 24 shows
an example of the energy to blow a resistor. The constant
minimum energy region is where adiabatic fusing takes
place. ESD events produce damage in this area because of
the very fast events. Slower EOS events allow some energy
to escape to the surrounding area, therefore the increased
energy and time required for fusing. Fig. 25 shows the
characteristic for a resistor that shorts. This is typical
of diffused resistors. The resistor element has a region of Fig. 27. I V characteristic (high current) for an n-channel
electron velocity saturation and eventually enters second MOSFET.
breakdown. Second breakdown causes a physical change
in the device structure. Part of the device melts. Fig. 5 also voltage increases with little or no drain current until the
shows how geometry can reduce the point where second drainbody junction enters avalanche breakdown, as shown
breakdown occurs. The 90 bend in the resistor caused by the point . The avalanche current flows to the
current crowding, allowing this region to reach second substrate and out through the body/source contact. The body
breakdown at a lower total current than expected. resistance allows a voltage to develop between the body
The MOS transistor has a parasitic bipolar transistor region near the drain and the body contact. This voltage can
buried within it [85]. Fig. 26 shows the cross section of a forward bias the body source diode, injecting more charge
typical NMOS transistor. As mentioned earlier, this tran- into the base region. Once this occurs, snapback soon follows
sistor plays a significant role in the conduction of current and the drain voltage drops significantly. The sustaining
during an ESD event. Fig. 27 shows a typical conduction voltage and sustaining current are shown in Fig. 27.
curve for this device. With the gate voltage at zero, the drain This point defines the voltage and current level necessary to

VINSON AND LIOU: ELECTROSTATIC DISCHARGE IN SEMICONDUCTOR DEVICES 1893

maintain the snapback condition. Voltages or currents below
this level will shut off the snapback condition. These levels
should be kept above the operating voltage of the device so
it is not possible to sustain snapback during normal device
operation. As the current increases, the drain voltage also
increases. The internal resistance of the device causes this
increase. The voltage and current increase until second
breakdown is reached at , . In a similar fashion to
the diffused resistor, the device destroys itself. It is desired
to have when a protection element is made up
of multiple parallel transistors. If , then the first
leg of a parallel structure to break down will carry all of the
current and be destroyed before the other transistors can turn
on. This defeats the purpose of having multiple transistors
in parallel. Another condition that causes problems is when
. This condition often occurs in technologies
with insulating substrates such as SOS. Once the device
breaks down, it is destroyed. This type of transistor would
not be good to use for ESD protection.
One way of providing protection to the circuit is to
improve the elements themselves so they can handle the
ESD current. Improving unprotected elements involves:
1) reducing the current density of the conduction path; 2)
reducing the electric fields induced; and 3) reducing the
thermal impedance or increasing the thermal mass at the
power dissipation point. In the case of thin-film fusing, it
is as simple as increasing the width of a thin-film resistor
or metal line. This accomplishes two tasks. First, the wider
line lowers the resistance and the power dissipation. Second,
the extra volume increases the thermal mass of the line
[71]. It can then absorb more energy without going into
second breakdown or fusing open. Another option is to use
a different material that has a higher melting/vaporization
temperature. The difficulty with this approach is these types
of metals also have a higher resistivity. The higher resistivity
is undesired when high currents are involved. In the case
of diffused versus polysilicon resistor, another factor must
be considered. A polysilicon resistor is surrounded by a
dielectric that acts both as an electrical insulator as well as a
thermal insulator. A diffused resistor can dissipate the heat
better than a polysilicon resistor because it sits in silicon
rather than on oxide.
Increasing their size and providing more uniform current
flow across the device improve transistors and diodes. As
mentioned earlier, large protection transistors are made up
of many parallel transistors. It is important to balance the
current flow across all of the transistors in the string. This
can be accomplished by placing small resistances in series
with the drain contacts. In the case of a MOSFET transistor,
as shown in Fig. 28, the silicide is omitted from a section
of the transistor near the gate. This places a small resistance
in series with the channel. The resistance helps balance the
current through the transistor during an ESD event. This ac-
tion keeps one spot of the transistor from absorbing all of
the ESD energy. For technologies without silicide, the con-
tact to gate spacing is important. This spacing should be at
least 23 m for submicrometer technologies and 46 m for
larger channel length (12 m) technologies [76]. Geometry
1894
Fig. 28. ESD improvement individual circuit element.
effects are very important for diodes. Their design should be
symmetric with no irregularities that would allow the current
or electric field to be focused in one area.
The other method to increase ESD robustness is to add
additional circuit elements to divert the charge around the
core circuit and clamp the voltage to an acceptable level.
The core circuits are the elements used to perform the func-
tion the circuit was designed to do. The ESD protection net-
work must prevent the damaging ESD current from flowing
in this circuitry. In addition to diverting the charge, the pro-
tection network must limit the voltages developed to a low
enough level so no core circuits enter breakdown. If any core
circuits enter breakdown, then the ESD current would flow
through them, causing damage. Most circuits use a combina-
tion of improving individual elements and adding additional
elements to achieve the desired performance. The obvious
question is where should one place the extra components and
what types of components are necessary. The placement of
components requires an understanding of the current paths
used by ESD.
As mentioned earlier, ESD events come in three versions:
HBM, MM, and CDM. The first two, HBM and MM, are
two terminal events. ESD current enters one terminal and
exits another. The current flows through the device under test
(DUT). In an ESD tester, testing each combination of two
pins simulates this effect. Each independent supply is treated
as a single pin even if multiple pins for that supply exist on
the packaged part. CDM is different in that the charge for the
event is stored internal to the package. CDM is a single pin
event. The part is charged and is discharged through a single
pin. Fig. 29 illustrates this. Fig. 30 shows the current wave-
form for a CDM event. Included in the figure is an HBM
waveform for comparison. As shown, the CDM event is very
fast and significantly higher in current. The fast event and
high peak current makes it difficult for protection networks
to protect circuits. The quickness of the event means the pro-
tection networks must turn on quickly. The higher current re-
quires the series impedance to be very low to reduce the gen-
erated voltages. Dielectric rupture is a more common failure
mode with CDM ESD. In a typical nonsocketed CDM tester,
the DUT is placed on an insulating surface above a metal
plate. The package style and design play an important role in
the CDM ESD threshold for a part. The capacitance, resis-
tance, and inductance of the package determine the rise time,
current peak, and duration of the ESD event. The important
information to note is that ESD events enter or exit the part at
PROCEEDINGS OF THE IEEE, VOL. 88, NO. 12, DECEMBER 2000
Fig. 29. CDM event discharge path.
Fig. 30. CDM event current discharge waveform.
the connections to the outside world. The protection network
must divert the charge as it enters or leaves the package so it
must be placed at or near the bond pads to be most effective.
It is also important to note that each pin must be protected
to every other pin, including all of the supply pins. It does
not matter whether they are outputs, inputs, I/Os, or supply
pinsthey all need some form of protection.
A good protection element will minimize the voltage al-
lowed internal to the unit as well as provide a low-impedance
shunt path for the current. This allows the charge to flow
through the protection element and not the circuit being pro-
tected. By doing this, the energy is dissipated away from the
circuit being protected. The protection element should be ca-
pable of handling multiple events without itself being de-
stroyed. It should also not interfere with the operation of the
circuit it is protecting. Given this discussion a perfect protec-
tion element will have these characteristics:
1) zero on-resistance;
2) zero clamp voltage;
3) instantaneous turn-on time;
4) infinite energy absorption;
5) only trigger during ESD events, not during operation;
6) transparent to circuit operation (i.e., no parasitics);
7) consume zero area on the die.
Zero on-resistance allows it to shunt large amounts of cur-
rent with no voltage rise from an ohmic voltage drop. Zero
clamping voltage is only valid if 5) is also true, otherwise
damage could occur during circuit operation. A more prac-
tical limit on the clamping voltage would be just above the
VINSON AND LIOU: ELECTROSTATIC DISCHARGE IN SEMICONDUCTOR DEVICES
Fig. 31. ESD protection by adding circuit elements.
operating supply voltage of the part being protected. The last
item is included because many times a tradeoff in cost versus
protection level must be made. In this case, the cost is die
area. It is clear that a real clamp of this type cannot be built,
but these criteria provide a list of optimizations and compro-
mises to use when building a protection element.
Fig. 31 illustrates a simple ESD protection network. The
network consists of a resistor and diode. This is not the best
network but illustrates the point of protection. If a negative
pulse with respect to ground enters the part, the current will
flow from ground through the diode and resistor. The voltage
across the n-channel MOSFET gate oxide will be limited
to one diode drop plus the drop from the internal re-
sistance of the diode. This keeps the gate oxide from rup-
turing. The remaining voltage is dropped across the resistor.
For the opposite polarity, the diode is in reverse breakdown.
The voltage across the gate oxide will be clamped at the
diode breakdown point, plus the internal drop and the
remaining voltage is dropped across the resistor. The diode
would be able to handle much more current in the forward di-
rection than in the reverse direction because the voltage drop
is much less in the forward than in the reverse conduction
direction. A better approach is illustrated in Fig. 32. Here,
two diodes are placed on the input and a protection network
is connected between the supply pins. In this arrangement,
the diodes on the input pins can conduct in the forward di-
rection and the supply clamp allows the conduction between
the supplies. It should be noted that the internal resistance
between each of these elements must be minimized to re-
duce the voltage developed across the interconnect. A dis-
tributed supply clamp may be required. This provides mul-
tiple clamps spaced across the die to lower the impedance
between pins.
The protection networks being described here are clamps.
Clamps can come in many different varieties. A simple
clamp was used in Figs. 31 and 32the diode. As discussed,
the diode has good power handling ability in the forward
direction but is a poor clamp in the reverse current direction.
Clamps can be grouped into two categories: static and
transient. As the name implies, static clamps provide a
static or steady-state current and voltage response. A fixed
voltage level activates static clamps. As long as the voltage
1895

Fig. 32. More effective ESD protection architecture than Fig. 31.
Fig. 33. Static clamps.
is above this level, the clamp will conduct current. Fig. 33
illustrates and Table 1 describes a sample of static clamps.
As can be seen, static clamps can be composed of a single
circuit element or a combination of circuit elements. A
diode, MOSFET, or SCR is typically used as the protection
element located on the input or output pin. A combination
clamp is used as the supply clamp. The supply clamp may
be a single clamp or multiple clamps distributed across the
die. Using multiple clamps provides the added benefit of
reducing the parasitic resistance between the supply clamps
and the pin clamps. Transient clamps take advantage of the
1896
Table 1
Static Clamps
rapid changes in voltage and/or current that accompanies
an ESD event. During this transient, an element is turned
on very quickly and slowly turns off. This type of clamp
conducts for a fixed time when it is triggered. An
network determines the time constant. These clamps are
typically triggered by very fast events on the supply lines.
A sample of transient clamps is illustrated schematically in
Fig. 34 and discussed in Table 2.
For the MOSFET transient clamp shown in Fig. 34, both
the normal MOS and parasitic BJT (snapback) can be oper-
ational at the same time. When an HBM ESD pulse with a
relatively fast rise time is introduced to the clamp circuit, the
capacitor will initially be a short circuit, which turns on the
MOS device quickly. Consequently, a large drain current as-
sociated with the HBM ESD will pass through the MOS de-
vice in this initial transient. At the same time, the high voltage
associated with the ESD pulse applied to the drain can give
rise to avalanche multiplication near the reverse-biased drain
junction. This results in a flow of avalanche-generated holes
to the substrate and a voltage drop across the substrate re-
sistance. As this voltage drop approaches 0.7 V, the parasitic
n-p-n BJT in the MOSFET is turned on resulting in snapback.
The dc curve for this event is shown in Fig. 27. During
the initial stage of an ESD event, the MOSFET acts like a
short circuit with a very high total drain current consisting of
the collector current from the parasitic BJT, the drain current
PROCEEDINGS OF THE IEEE, VOL. 88, NO. 12, DECEMBER 2000
Fig. 34. Dynamic clamps.
Table 2
Transient Clamps
from the normal MOS, and the generation current from the
avalanche multiplication. In the next sequence, the capacitor
will be charged through the resistor, and the charging rate de-
pends on the time constant of the clamp circuit. As the
voltage across the capacitor increases, VGS of the NMOS de-
creases, and the capacitor acts as an open circuit when fully
charged. The MOS device is turned off, while the parasitic
BJT is still on, when VGS decays below its threshold voltage.
This leads to a quick decrease in the drain current and a rel-
ative uniformity in the drain voltage during the subsequent
stage of the ESD event (i.e., the voltage across the circuit is
clamped to a fixed value). Eventually, the parasitic BJT is
turned off when the ESD pulse decays to a value below the
critical voltage for avalanche. For an ESD pulse with a rel-
atively small rise time, the voltage drop across the resistor
connected to the gate in the clamp circuit may not be high
enough to turn on the NMOS in the initial stage, and only the
parasitic BJT is operational during the ESD event. Fig. 35
shows the transient drain voltage and current measured for
such a clamp circuit.
Both have advantages and disadvantages. The static clamp
typically occupies less space and is composed of fewer ele-
VINSON AND LIOU: ELECTROSTATIC DISCHARGE IN SEMICONDUCTOR DEVICES
Fig. 35. Measured time-dependent (a) drain voltage and (b) drain
current of the MOSFET transient clamp with a MOSFET of 1.5-m
channel length and 80-m channel width subjected to an HBM ESD
stress.
ments. If a static clamp falsely triggers while power is applied
to the part, it will be destroyed. Transient clamps, on the other
hand, can be designed to turn on very quickly and handle
larger transient events. The disadvantage is that they will also
respond to any fast event, even noise. If they falsely trigger
while the part is powered, they could interfere with circuit
operation and it is likely that the part will be destroyed.
The selection of what type of clamp to employ in a design
is based on several criteria. The first criterion is what circuit
elements are available in the process. The next would relate
to the environment the circuit must operate in. This was dis-
cussed earlier. An SCR is not usable where hot switching or
ionizing radiation is expected. The other criteria needed are
its current handling capability and its turn-on time. Turn-on
is especially important for CDM ESD because this type of
ESD is a very fast event. Many clamps may not be able to re-
spond quickly enough to provide protection against this type
of ESD event.
The design of the clamp needs to consider the clamping
voltage level and internal resistance. Clamping voltage de-
fines what level of protection is provided to the dielectrics in
the process. This includes gate oxides and interlevel oxides.
The internal resistance defines the voltage rise as a result of
1897
the ESD current pulse and contributes to the power dissipated
in the clamp.
The thermal impedance of the camp to a heat sink (sub-
strate) is also important because this determines the internal
temperature rise and ultimately the failure point of the clamp.
A device with lower thermal impedance will have a higher
ESD threshold.
All of these can be combined into a figure of merit used to
describe an ESD structure. This figure a merit is the voltage
per micrometer of width or voltage per square micrometer
area. The voltage listed here is the ESD threshold of the
structure per unit width or area. For example, if a structure
were listed as 10 V/ m, it would require a 200- m device
to achieve a 2000-V protection threshold. Providing the best
ESD thresholds with the smallest devices requires selection
of devices with high ESD figures of merit.
It should be noted that these structures might not scale
linearly. Earlier, it was noted that some designs do not turn
on uniformly. This effectively shrinks the available width or
area of the structure, making its figure of merit lower. Care
must be used when making a selected clamp larger than when
it was characterized.
VI. CONCLUSION
ESD protection is necessary for all circuits. Protection re-
quires a systematic approach with a commitment from the
entire organization. A dedicated team is required to drive
ESD improvement. ESD protection follows a two-pronged
approach to improve both the environments that parts are
handled in as well as the robustness of each part. The envi-
ronment is improved by reducing the amount of charge devel-
oped and by controlling the discharge of any charge that is de-
veloped. Circuits are improved by designing elements better
able to handle the ESD currents and by providing an alter-
nate path (a shunt) for the charge to travel as it passes through
the part. This shunt protects the sensitive elements in the de-
vice by clamping the voltage developed during the event and
diverting the current away from the core circuit. The ESD
program is a dynamic system ever evolving as new tech-
niques and technologies are developed. If it does not grow, it
will die. Only if the entire organization participates and sup-
ports the program can the true benefits of higher yield, better
throughput, and more satisfied customers be realized.
REFERENCES
[1] W. D. Greason, Electrostatic discharge: A charge driven phenom-
enon, in Proc. EOS/ESD Symp., vol. EOS-13, Sept. 1991, pp. 19.
[2] J. E. Vinson and J. J. Liou, Electrostatic discharge in semiconduc-
tors devices: An overview, Proc. IEEE, vol. 86, no. 2, pp. 399418,
1998.
[3] T. L. Welsher, T. J. Blondin, G. T. Dangelmayer, and Y. Smooha,
Design for electrostatic-discharge (ESD) protection in telecommu-
nications products, AT&T Tech. J., vol. 69, no. 3, pp. 7796, 1990.
[4] W. J. Kirk, Designing a workplace, 1993 EOS/ESD Tutorial Notes,
pp. B-1B-23, Sept. 1993.
[5] E. W. Chase and B. A. Under, Triboelectric charging of personnel
from walking on tile floors, in Proc. EOS/ESD Symp., vol. EOS-8,
Sept. 1986, pp. 127135.
[6] L. A. Avery, A review of electrostatic discharge mechanisms and
on-chip protection techniques to ensure device reliability, J. Elec-
trostatics, vol. 24, no. 2, pp. 111113, 1990.
1898
[7] H. Calvin, H. Hyatt, H. Mellberg, and D. Pellinen, Measurement of
fast transients and application to human ESD, in Proc. EOS/ESD
Symp., vol. EOS-2, Sept. 1980, pp. 225230.
[8] J. S. Maas and D. A. Skjeie, Testing electronic products for sus-
ceptibility to electrostatic discharge, in Proc. EOS/ESD Symp., vol.
EOS-12, Sept. 1990, pp. 9296.
[9] R. Saini and K. G. Balmain, Human hand/metal ESD and its phys-
ical simulation, in Proc. EOS/ESD Symp., vol. EOS-17, Sept. 1995,
pp. 9094.
[10] H. M. Hyatt, The resistance phase of an air discharge and the for-
mation of fast rise time ESD pulses, in Proc. EOS/ESD Symp., vol.
EOS-14, Sept. 1992, pp. 5567.
[11] K. Verhaege, C. Russ, D. Robinson-Hahn, M. Farris, J. Scanlon, D.
Lin, J. Veltri, and G. Groeseneken, Recommendations to further
improvements of HBM ESD component level test specifications,
in Proc. EOS/ESD Symp., vol. EOS-18, Sept. 1996, pp. 4053.
[12] T. M. Bilodeau, Theoretical and empirical analysis of the effects
of circuit parasitic on the calibration of HBM ESD simulators, in
Proc. EOS/ESD Symp., vol. EOS-11, Sept. 1989, pp. 4349.
[13] L. Van Roozendaal, A. Amerasekera, P. Bos, W. Baelde, F. Bontekoe,
P. Kersten, E. Korma, P. Rommers, P. Krys, U. Weber, and P. Ashby,
Standard ESD testing of integrated circuits, in Proc. EOS/ESD
Symp., vol. EOS-12, Sept. 1990, pp. 119130.
[14] D. Robinson-Hahn, ESD flooring: An engineering evaluation, in
Proc. EOS/ESD Symp., vol. EOS-17, Sept. 1995, pp. 154161.
[15] J. M. Kolyer, W. E. Anderson, and D. E. Watson, Hazards of static
charges and fields at the work station, in Proc. EOS/ESD Symp.,
vol. EOS-6, Sept. 1984, pp. 719.
[16] N. B. Fugua and D. J. Dekkers, An ESD expert system, in Proc.
EOS/ESD Symp., vol. EOS-9, Sept. 1987, pp. 129133.
[17] E. C. Y. Lai and J. S. Plaster, ESD control in the automotive
electronics industryA case study, in Proc. EOS/ESD Symp., vol.
EOS-9, Sept. 1987, pp. 1017.
[18] H. C. Snyder, A comprehensive ESD control program for a large
disk file, in Proc. EOS/ESD Symp., vol. EOS-10, Sept. 1988, pp.
2632.
[19] G. T. Dangelmayer, A systematic ESD program revisited, in Proc.
EOS/ESD Symp., vol. EOS-14, Sept. 1992, pp. 18.
[20] R. Braude, Setting up an effective corporate ESD program, in
Proc. EOS/ESD Symp., vol. EOS-15, Sept. 1993, pp. 3537.
[21] W. Y. McFarland and R. A. Brin, Youve implemented an ESD pro-
gramWhat next?, in Proc. EOS/ESD Symp., vol. EOS-15, Sept.
1993, pp. 4147.
[22] G. T. Dangelmayer, ESD Program Management: A Realistic
Approach to Continuous Measurable Improvement in Static Con-
trol. New York: Van Nostrand Reinhold, 1993.
[23] R. G. Wagner, J. M. Soden, and C. F. Hawkins, Extent and cost
of EOS/ESD damage in an IC manufacturing process, in Proc.
EOS/ESD Symp., vol. EOS-15, Sept. 1993, pp. 4955.
[24] D. Blinde and L. Lavoie, Quantitative effects of relative and abso-
lute humidity on ESD generation/suppression, in Proc. EOS/ESD
Symp., vol. EOS-3, Sept. 1981, pp. 913.
[25] J. M. Calderbank, D. E. Overbay, and H. Z. Sayder, The effects
of high humidity environments on electrostatic generation and
discharge, in Proc. EOS/ESD Symp., vol. EOS-2, Sept. 1980, pp.
1216.
[26] D. E. Swenson, J. P. Weidendorf, and E. C. Gillard, Resistance
to ground and tribocharging of personnel, as influenced by relative
humidity, in Proc. EOS/ESD Symp., vol. EOS-17, Sept. 1995, pp.
141153.
[27] C. F. Mykkanen and D. R. Blinde, The room air ionization system,
a better alternative than 40% relative humidity, in Proc. EOS/ESD
Symp., vol. EOS-5, Sept. 1983, pp. 6775.
[28] J. N. Antonevich and M. Blitshteyn, Measuring effectiveness of
air ionizers, in Proc. EOS/ESD Symp., vol. EOS-5, Sept. 1983, pp.
7686.
[29] D. M. Fehrenbach and R. R. Taso, An evaluation of air ionizers for
static charge reduction and particle emission, in Proc. EOS/ESD
Symp., vol. EOS-14, Sept. 1992, pp. 1225.
[30] P. Madden, Selection and applications for ionization equipment,
in Proc. EOS/ESD Symp., vol. EOS-9, Sept. 1987, pp. 241245.
[31] B. A. Unger, R. G. Chemelli, and P. R. Bossard, A room ionization
system for electrostatic charge and dust control, in Proc. EOS/ESD
Symp., vol. EOS-6, Sept. 1984, pp. 4044.
[32] E. W. Chase and B. A. Under, Triboelectric charging of personnel
from walking on tile floors, in Proc. EOS/ESD Symp., vol. EOS-8,
Sept. 1986, pp. 127135.
PROCEEDINGS OF THE IEEE, VOL. 88, NO. 12, DECEMBER 2000
 [33] D. Robinson-Hahn, ESD flooring: An engineering evaluation, in
Proc. EOS/ESD Symp., vol. EOS-17, Sept. 1995, pp. 154161.
[34] J. M. Kolyer, W. E. Anderson, and D. E. Watson, Hazards of static
charges and fields at the work station, in Proc. EOS/ESD Symp.,
vol. EOS-6, Sept. 1984, pp. 719.
[35] N. I. Safeer and J. R. Mileham, A material evaluation program
for decorative static control tabletop laminates, in Proc. EOS/ESD
Symp., vol. EOS-6, Sept. 1984, pp. 8593.
[36] D. E. Swenson and R. Gibson, Triboelectric testing of packaging
materials practical considerations what is important? What does it
mean?, in Proc. EOS/ESD Symp., vol. EOS-14, Sept. 1992, pp.
209217.
[37] M. Honda and T. Kinoshita, New approaches to indirect ESD
testing, in Proc. EOS/ESD Symp., vol. EOS-17, Sept. 1995, pp.
8689.
[38] D. C. Smith, A new type of furniture ESD and its implications, in
Proc. EOS/ESD Symp., vol. EOS-15, Sept. 1993, pp. 37.
[39] J. M. Kolyer, D. E. Watson, and W. E. Anderson, Controlling
voltage on personnel, in Proc. EOS/ESD Symp., vol. EOS-11, Sept.
1989, pp. 2331.
[40] R. Kallman, Realities of wrist strap monitoring systems, in Proc.
EOS/ESD Symp., vol. EOS-16, Sept. 1994, pp. 3441.
[41] J. E. Sohl, An evaluation of wrist strap parameters, in Proc.
EOS/ESD Symp., vol. EOS-2, Sept. 1980, pp. 218224.
[42] A. P. Hohl, A wrist strap life test program, in Proc. EOS/ESD
Symp., vol. EOS-6, Sept. 1984, pp. 9496.
[43] T. Minami, Static electricity elimination using conductive fiber
by dyeing, in Proc. EOS/ESD Symp., vol. EOS-9, Sept. 1987, pp.
137141.
[44] G. L. Johnson and D. D. Steffe, A study on the effectiveness of
ESD smocks, in Proc. EOS/ESD Symp., vol. EOS-12, Sept. 1990,
pp. 263267.
[45] A. Fujie, H. Uchida, A. Iwasaki, and T. Numaguchi, Control of
static charge on personnel in an electronics work area, in Proc.
EOS/ESD Symp., vol. EOS-19, Sept. 1997, pp. 163169.
[46] J. A. Gmzalez, S. A. Rizvi, E. M. Crown, and P. R. Smy, Mathe-
matical modeling of electrostatic propensity of protective clothing
systems, in Proc. EOS/ESD Symp., vol. EOS-19, Sept. 1997, pp.
153162.
[47] J. M. Kolyer and W. E. Anderson, Perforated foil bags: Partial trans-
parency and excellent ESD protection, in Proc. EOS/ESD Symp.,
vol. EOS-7, Sept. 1985, pp. 111117.
[48] A. F. Murello and L. R. Avery, Study of antistatically coated
shipping tubes using static decay and triboelectric tests, in Proc.
EOS/ESD Symp., vol. EOS-8, Sept. 1986, pp. 156158.
[49] G. C. Holmes, P. J. Huff, and R. L. Johnson, An experimental
study of the ESD screening effectiveness of anti-static bags, in
Proc. EOS/ESD Symp., vol. EOS-6, Sept. 1984, pp. 7884.
[50] J. M. Kolyer and W. E. Anderson, Permanence of the anti-static
property of commercial anti-static bags and tote boxes, in Proc.
EOS/ESD Symp., vol. EOS-5, Sept. 1983, pp. 8794.
[51] , Selection of packaging materials for electrostatic discharge
sensitive (ESDS) items, in Proc. EOS/ESD Symp., vol. EOS-3, Sept.
1981, pp. 7584.
[52] B. Unger, R. Chemelli, P. Bossard, and M. Hudock, Evaluation of
integrated circuit shipping tubes, in Proc. EOS/ESD Symp., vol.
EOS-3, Sept. 1981, pp. 5764.
[53] E. D. Tenzer, H. C. Hartman, and M. A. Johnson, An analysis of
anti-static cushioning materials, in Proc. EOS/ESD Symp., vol.
EOS-3, Sept. 1981, pp. 4448.
[54] W. H. Tan, Minimizing ESD hazards in IC test handlers and auto-
matic trim/form machines, in Proc. EOS/ESD Symp., vol. EOS-15,
Sept. 1993, pp. 5764.
[55] J. P. Sauers, Test equipmentA source of ESD, in Proc. EOS/ESD
Symp., vol. EOS-6, Sept. 1984, pp. 2021.
[56] A. Steinman and J. A. Montoya, Developing an exit charge spec-
ification for production equipment, in Proc. EOS/ESD Symp., vol.
EOS-18, Sept. 1996, pp. 145149.
[57] J. Bernier, S. Morrison, and C. Phillips, CDM events in automated
test handlers and environmental testingA case history, in Proc.
EOS/ESD Symp., vol. EOS-16, Sept. 1994, pp. 214220.
[58] J. Bernier and B. Hesher, ESD improvements for familiar auto-
mated handlers, in Proc. EOS/ESD Symp., vol. EOS-15, Sept. 1995,
pp. 110117.
[59] J. M. Kolyer, R. Rushworth, and W. E. Anderson, Electrostatic dis-
charge (ESD) control in an automated process, in Proc. EOS/ESD
Symp., vol. EOS-9, Sept. 1987, pp. 4150.
VINSON AND LIOU: ELECTROSTATIC DISCHARGE IN SEMICONDUCTOR DEVICES
[60] L. Ow and W. Tan, Evaluating and qualifying automated test han-
dlers in a semiconductor company, in Proc. EOS/ESD Symp., vol.
EOS-16, Sept. 1994, pp. 2227.
[61] M. Honda and T. Kinoshita, New approaches to indirect ESD
testing, in Proc. EOS/ESD Symp., vol. EOS-17, Sept. 1995, pp.
8689.
[62] A. Amerasekera and C. Duvvury, The impact of technology scaling
on ESD robustness and protection circuit design, in Proc. EOS/ESD
Symp., vol. EOS-16, 1994, pp. 237245.
[63] J. E. Murguia and J. B. Bernstein, Short-time failure of metal inter-
connect caused by current pulses, IEEE Electron Device Lett., vol.
14, no. 10, 1993.
[64] D. G. Pierce, Modeling metallization burnout of integrated
circuits, in Proc. EOS/ESD Symp., vol. EOS-4, 1982, pp. 5661.
[65] K. Banerjee, S. Rzepka, A. Amerasekera, N. Cheung, and C. Hu,
Thermal analysis of the fusion limits of metal interconnect under
short duration current, in Int. Integrated Reliability Workshop Final
Rep. Proc., Oct. 1996, pp. 98102.
[66] K. Banerjee, A. Amerasekera, and C. Hu, Characterization of VLSI
circuit interconnect heating and failure under ESD conditions, in
Int. Reliability Physics Symp. Proc., 1996, pp. 237245.
[67] T. J. Maloney, Integrated circuit metal in the charged device model:
Bootstrap heating, melt damage, scaling laws, in Proc. EOS/ESD
Symp., vol. EOS-14, 1992, pp. 129134.
[68] O. J. McAteer, Pulse evaluation of integrated circuit metallization
as an alternative to SEM, in Proc. Int. Reliability Physics Symp.,
1997, pp. 217224.
[69] K. Yamaoto and T. Tsuru, Time-dependent temperature calcula-
tions of aluminum lines applied with electrical overstress pulses,
Jpn. J. Appl. Phys., pt. 1, vol. 35, pp. 38523857, July 1996.
[70] D. C. Wunsh, The application of electrical overstress models to gate
protective networks, in Proc. Int. Reliability Physics Symp., 1978,
pp. 4755.
[71] J. E. Vinson, Aluminum interconnect response to electrical over-
stress, in Proc. 24th Int. Symp. Testing and Failure Analysis, Nov.
1998.
[72] J. E. Voldman, et al., A strategy for characterization and evaluation
of ESD robustness of CMOS semiconductor technologies, in Proc.
EOS/ESD Symp., vol. EOS-21, Sept. 1999, pp. 212224.
[73] R. N. Rountree, ESD protection for submicron CMOS circuits is-
sues and solutions, IEDM, pp. 580583, 1988.
[74] C. Duvvury and A. Amerasekera, ESD: A pervasive reliability con-
cern for IC technologies, Proc. IEEE, vol. 81, no. 5, pp. 690702,
1993.
[75] K. Chen, G. Giles, and D. B. Scott, Electrostatic discharge pro-
tection for one micron CMOS devices and circuits, in IEDM, pp.
484487, 1986.
[76] C. Duvvury, ESD on-chip protection in advanced CMOS technolo-
gies, in Tutorial B 1999 EOS/ESD Symp., Sept. 1999.
[77] L. Teems and J. Bernier, ESD protection using active area bonding,
in Proc. 24th Int. Symp. Testing and Failure Analysis, Nov. 1998.
[78] W. R. Anderson, W. M. Gonzalez, S. S. Knecht, and W. Fowler,
ESD protection under wire bonding pads, in Proc. EOS/ESD
Symp., vol. EOS-21, Sept. 1999, pp. 8894.
[79] A. Amerasekera, RF protection circuit design approaches, in Tu-
torial G 1999 EOS/ESD Symp., Sept. 1999.
[80] W. D. Mack and R. Meyer, New ESD protection schemes for
BiCMOS process with application to cellular radio designs, in
Proc. IEEE Int. Symp. Circuits and Systems, 1992, pp. 26992701.
[81] J. Z. Chen, X. Y. Zhang, A. Amerasekera, and T. Vrotsos, De-
sign and layout of a high performance NPN structure for submicron
BiCMOS/bipolar circuits, in Proc. 34th IRPS, 1996, pp. 227232.
[82] N. Tandan and G. Conner, ESD trigger circuit, in Proc. 16th
EOS/ESD Symp., 1994, pp. 120124.
[83] K. Banerjee, A. Amerasekera, and C. Hu, Characterization of
VLSI circuit interconnect heating and failure under ESD
conditions, in Proc. 34th Annu. Int. Reliability Physics Symp.,
1996, pp. 237245.
[84] G. Krieger, Diffused resistors characteristics at high current density
levelsAnalysis and applications, IEEE Trans. Electron Devices,
vol. 36, no. 2, pp. 416423, 1989.
[85] C. Duvvury, R. N. Rountree, and O. Adams, Internal chip ESD phe-
nomena beyond the protection circuit, IEEE Trans. Electron De-
vices, vol. 35, no. 12, pp. 21332139, 1988.
[86] A. J. Walash and T. H. Hughbanks, Capacitive coupling effects in
sparkgap devices, in Proc. EOS/ESD Symp., vol. EOS-16, 1994, pp.
273278.
1899
 [87] L. W. Linhom and R. F. Plachy, Electrostatic gate protection using
an arc gap device, pp. 198202.
[88] S. H. Cohen and G. K. Caswell, An improved input protection cir-
cuit for C-MOS/SOS arrays, IEEE Trans. Electron Devices, vol.
ED-25, no. 8, pp. 926932, 1978.
[89] C. Richier, N. Maene, G. Mabboux, and R. Bellens, Study of the
ESD behavior of different clamp configurations in a 0.35mm CMOS
technology, in Proc. EOS/ESD Symp., vol. EOS-19, Sept. 1997, pp.
240245.
[90] X. Guggenmos and R. Holzner, A new ESD protection concept
for VLSI CMOS circuits avoiding circuit stress, in Proc. EOS/ESD
Symp., vol. EOS-13, 1991, pp. 7482.
[91] M. Corsi, R. Nimmo, and F. Fattori, ESD protection of BiCMOS
integrated circuits which need to operate in the harsh environments
of automotive or industrial, in Proc. EOS/ESD Symp., vol. EOS-15,
1993, pp. 209213.
[92] J. R. M. Luchies, C. G. C. M. deKort, and J. F. Verweij, Fast turn-on
of an NMOS ESD protection transistor: Measurements and simula-
tions, in Proc. EOS/ESD Symp., vol. EOS-16, 1994, pp. 266272.
[93] C. Duvvury and R. Rountree, A synthesis of ESD input protection
scheme, in Proc. EOS/ESD Symp., vol. EOS-13, 1991, pp. 8897.
[94] Y. Fong and C. Hu, Internal ESD transients in input protection cir-
cuits, in Proc. Int. Reliability Physics Symp., 1989, pp. 7781.
[95] H. Ishizuka, K. Okuyama, K. Kubota, M. Komuto, and Y. Hara, A
study of ESD protection devices for input pins, in Proc. EOS/ESD
Symp., vol. EOS-19, 1997, pp. 255262.
[96] G. D. Croft, ESD protection using a variable voltage supply clamp,
in Proc. EOS/ESD Symp., vol. EOS-16, 1994, pp. 135140.
[97] B. G. Carbajal III, R. A. Cline, and B. H. Anderson, A successful
HBM protection circuit for micron and sub-micron level CMOS, in
Proc. EOS/ESD Symp., vol. EOS-14, pp. 234242.
[98] G. D. Croft, Dual rail ESD protection using complementary SCRs,
in Proc. EOS/ESD Symp., vol. EOS-14, 1992, pp. 243249.
[99] M. Ker, C. Wu, and C. Lee, A novel CMOS ESD/EOS protec-
tion circuit with full-SCR structures, in Proc. EOS/ESD Symp., vol.
EOS-14, pp. 258264.
[100] C. Diaz and G. Motley, Bi-modal triggering for LVSCR ESD pro-
tection devices, in Proc. EOS/ESD Symp., vol. EOS-16, 1994, pp.
106112.
[101] S. Dabral, R. Aslett, and T. Maloney, Core clamps for low voltage
technologies, in Proc. EOS/ESD Symp., vol. EOS-16, 1994, pp.
141149.
[102] T. J. Maloney and S. Dabral, Novel clamp circuits for IC power
supply protection, in Proc. EOS/ESD Symp., vol. EOS-17, 1995,
pp. 112.
[103] T. J. Maloney, K. Parat, N. K. Clark, and A. Darwish, Protection
of high voltage power and programming pins, in Proc. EOS/ESD
Symp., vol. EOS-19, 1997, pp. 246254.
[104] S. Ramaswamy, C. Duvvury, A. Amerasekera, V. Reddy, and S. M.
Kang, EOS/ESD analysis of high-density logic chips, in Proc.
EOS/ESD Symp., vol. EOS-18, 1996, pp. 285290.
[105] G. D. Croft, Transient supply clamp with a variable RC time con-
stant, in Proc. EOS/ESD Symp., vol. EOS-18, 1996, pp. 276279.
[106] E. R. Worley, R. Gupta, B. Jones, R. Kjar, C. Nguyen, and M.
Tennyson, Sub-micron chip ESD protection schemes which avoid
avalanching junctions, in Proc. EOS/ESD Symp., vol. EOS-17,
1995, pp. 1320.
1900
James E. Vinson received the B.E.E. degree
from Auburn University, Auburn, AL, in 1982,
the M.S. degree in electrical engineering from
North Carolina State University, Raleigh, NC,
in 1984, and the Ph.D. degree in electrical
engineering from the University of Central
Florida, Orlando, in 1998. His areas of study
were in radiation effects and electrical overstress
failure mechanisms in semiconductor devices.
In 1984, he joined Intersil Corporation (for-
merly Harris Semiconductor), Melbourne, FL.
He is currently a Senior Principal Engineer in the Reliability Group. He has
published numerous papers on reliability, failure analysis, and single event
phenomena, including two invited papers at international conferences.
His responsibilities include reliability investigations and qualification,
as well as failure analysis of both analog and digital circuits built using
bipolar and complementary metaloxidesemiconductor technology for
military and space customers. He serves as a Design Consultant for ESD
and EOS robustness in new circuits. His current research interests include
failure mechanism modeling for failures caused by electrical overstress and
electrostatic discharge, as well as dielectric reliability.
J. J. Liou (Senior Member, IEEE) received
the B.S. (honors), M.S., and Ph.D. degrees in
electrical engineering from the University of
Florida, Gainesville, in 1982, 1983, and 1987,
respectively.
In 1987, he joined the Department of Elec-
trical and Computer Engineering, University
of Central Florida, Orlando, where he is now
a Professor. His current research interests are
semiconductor device modeling, simulation, re-
liability, and characterization. He has published
four textbooks, more than 160 journal papers, and more than 110 papers
(including 24 invited papers) in international and national conference pro-
ceedings. He has held consulting positions with research laboratories and
companies in the United States, Japan, Taiwan, and Singapore. He serves
as a technical reviewer for various journals and publishers, and serves as
a technical program committee chair or member for several international
conferences. He has so far supervised and graduated 23 M.S. and Ph.D.
students, all of whom are working in microelectronics companies, such
as Intel, Motorola, Lucent Technologies, and Intersil. In the summers of
19921994, he was selected as a Member of Summer Research Faculty at
the Air Force Research Laboratory, Wright-Patterson Air Force Base, Ohio,
where he conducted research on AlGaAsGaAs heterojunction bipolar
transistors. In the fall of 1997, he took a sabbatical leave and worked as
a Visiting Professor at the Electrical Engineering Department, National
University of Singapore.
Dr. Liou has received eight different awards on excellence in teaching and
research from the University of Central Florida. He is an associate editor for
the Simulation journal in the area of VLSI and circuit simulation, and is a re-
gional editor (in the USA) for Microelectronics Reliability, an international
journal published by Elsevier.
PROCEEDINGS OF THE IEEE, VOL. 88, NO. 12, DECEMBER 2000