Apr.
2003
TABLE OF CONTENTS
SPECIFICATIONS.............................................................2
LOCATION OF CONTROLS ..........................................4
LOCATION OF CONTROLS PARTS LIST ...................5
EXPLODED VIEW ............................................................6
EXPLODED VIEW PARTS LIST .....................................7
PARTS LIST........................................................................8
IDENTIFYING THE VERSION NUMBER ..................10
SAVING USER DATA & RELOADING SAVED
DATA................................................................................10
TEST MODE.....................................................................11
Copyright 2003 ROLAND CORPORATION
All rights reserved. No part of this publication may be reproduced in any form without the written permission
of ROLAND CORPORATION.
17058160E0
SPD-S
SERVICE NOTES
INITIALIZATION PROCEDURE .................................16
FORMATTING A COMPACTFLASH CARD.............17
RESTORING THE FACTORY SETTINGS ...................17
PROCEDURE FOR UPDATING THE SYSTEM
SOFTWARE......................................................................18
BLOCK DIAGRAM.........................................................20
CIRCUIT BOARD (MAIN) ............................................22
CIRCUIT DIAGRAM (MAIN).......................................26
CIRCUIT BOARD (PANEL) ..........................................42
CIRCUIT DIAGRAM (PANEL).....................................46
Printed in Japan (0800) (NB)
 Apr.2003

SPECIFICATIONS Dimensions
342 (W) x 282 (D) x 83 (H) mm
13-1/2 (W) x 11-1/8 (D) x 3-5/16 (H) inches
SPD-S: Sampling Pad

Pads Weight
2.1 kg
Built-in Pads: 9
4 lbs 11 oz (excluding AC adaptor)
Maximum Polyphony
Accessories
8 voices
Owners Manual English (#03129712)
Sampling Mode AC Adaptor ACI-120C (#00975767)
AC Adaptor ACI-230C (#01018312)
Fine/Standard/Long
AC Adaptor ACB-230E (#01458278)
AC Adaptor ACB-240A (#12449549)
Sampling Frequency
Sampling CD (#03129723)
44.1 kHz Stand Holder Mounting Screw x 4 (#40563778)
Security Screw x 2 (#02126156)
Input Level Hexagon Wrench (#********)
Line: -10 dBu Slit Tape (#********)
Mic: -50 dBu
Options
Input Impedance Pads (PD-120, PD-100, PD-80, PD-80R, PD-9, PD-7, PD-6, KD-7)
10 k ohm (LINE/MIC) Expression Pedal (EV-5)
Foot Switch (BOSS FS-5U)
Output Level Hi-Hat Control Pedal (FD-7)
Output: -10 dBu PCS Connecting Cord Set (PCS-31)
All Purpose Clamp Set (APC-33)
Output Impedance
The CompactFlash which can operate by SPD-S
Output: 1 k ohm
Headphones: 47 ohm CompactFlash Capacity: 16M/32M/64M/128M/256M/512M byte

Memory
0 dBu = 0.775 Vrms
Patches: 128
Waves: Internal: 399 (Pre-loaded Sound 181)
Card: 500 * In the interest of product improvement, the specifications and/or appearance of
this unit are subject to change without prior notice.
Maximum Sampling Time
12 min. approx. (Internal Memory, Long Mode)

Effects
Multi-Effects (30 types) + Ambience (System)

Display
16 characters, 1 line (backlit LCD)

Connectors
Output Jacks (L/Mono, R) (1/4 inch phone type)
Input Jacks (L/Mono, R) (1/4 inch phone type)
* LINE/MIC selectable
Headphones Jack (Stereo) (Stereo 1/4 inch phone type)
Trigger Input Jack (1/4 inch TRS phone type)
Expression Pedal (1/4 inch TRS phone type)
MIDI Connectors (IN, OUT)
Foot Switch Jack (1/4 inch TRS phone type)
CompactFlash Card Slot

Power Supply
DC 9 V: AC Adaptor

Current Draw
1,000 mA

2
SPD-S

3
 Apr.2003

LOCATION OF CONTROLS
fig.panel

20

2 2 5 6 7
3 4
8 9 10 11 12

13 14 15 16 17 12 18 19

4
 SPD-S

LOCATION OF CONTROLS PARTS LIST

[Parts]
NO. PART CODE PART NAME DESCRIPTION QTY
1 03341889 PLAYING PLATE ASSY for SC 1
2 03129489 R-KNOB for SC 2
3 03230601 9M/M ROTARY POT. EVUJFRFK1B14 1
4 F3229136 12M/M ROTARY POT. RV112B-40E1-125A-A10K for SC 1
5 03129756 PANEL SHEET ASSY for SC 1
6 03129545 TOP PANEL for SC 1
7 03129512 RUBBER SWITCH for SC 1
8 02341634 DC JACK HTJ-020-05A 1
9 03341890 BOTTOM CASE ASSY for SC 1
10 03235345 SLIDE SWITCH SSSF141300 1
11 02341712 6.5MM JACK (MONORAL) HTJ-064-10I 4
12 02897334 6.5MM JACK (STEREO) HTJ-064-10D for SC 3
13 12499175 KEY TOP for POWER SW JSPUE0011A 1
01676512 POWER SWITCH SDKLA1-B 1
14 22365714 CORD HOOK 1
15 40011312 SCREW M3x8 BINDING TAPTITE P BZC 1
16 02568867 MIDI CONNECTOR HDC-052A-12 1
17 02341645 6.5MM JACK (STEREO) HTJ-064-04A 1
18 03129556 REAR PANEL for SC 1
19 02565056 9M/M ROTARY POT. RK09K12A0D0K 2
20 03341901 CF COVER ASSY for SC 1
03121678 COMPACTFLASH CONNECTOR ICM-MA2H-SS52-R21A 1
03121689 COMPACTFLASH EJECTOR ICM-MAE-R21 1

5
 Apr.2003

EXPLODED VIEW
fig.bunkai-e

a e
2 1

b f
2
2

c
c
5
2 4

11 d
12
6
c 7
d 8
* 9

13

15 d
10
14
16
* Apply SHIELD SHEET using a
double-side tape on the reverse side

20

18
21

17
22

19

23

6
 SPD-S

EXPLODED VIEW PARTS LIST

[Parts]
NO. PART CODE PART NAME DESCRIPTION QTY
1 22365714 CORD HOOK 1
2 01344967 FOOT 4
3 03341890 BOTTOM CASE ASSY (INC. BOTTOM CASE) 1
4 ******** REAR HOLDER 1
5 12499175 KEY TOP for POWER SW JSPUE0011A 1
6 03129745 MAIN BOARD ASSY 1
7 03341901 CF COVER ASSY (INC. CF ESCUTCHEON) 1
8 03341901 CF COVER ASSY (INC. CF COVER) 1
9 03341901 CF COVER ASSY (INC. CF HOLDER) 1
10 ******** SHIELD SHEET 1
11 03129756 PANEL SHEET ASSY (INC. PANEL BOARD) 1
12 ******** WIRING 1 40 PIN 1
13 03129512 RUBBER SWITCH 1
14 03341889 PLAYING PLATE ASSY (INC. PCB SPACER CBS-19K) 3
15 03341889 PLAYING PLATE ASSY (INC. SENSOR ASSY) 2
16 03341889 PLAYING PLATE ASSY (INC. TOP CASE) 1
17 03129756 PANEL SHEET ASSY (INC. VOLUME BOARD) 1
18 ******** WIRING 2 12 PIN 1
19 03129489 R-KNOB for SC 2
20 03341889 PLAYING PLATE ASSY (INC. EDGE SHEET SENSOR for PAD 1-3) 1
21 03341889 PLAYING PLATE ASSY (INC. HEAD SHEET SENSOR for PAD 4-9) 1
22 03341889 PLAYING PLATE ASSY (INC. CUSHION) 1
23 03341889 PLAYING PLATE ASSY (INC. PLAYING PLATE) 1

[Screws]
NO. PART CODE PART NAME DESCRIPTION QTY
a 40562967 SCREW 4x16 BINDING TAPTITE P NI 4
b 40012501 SCREW 4x12 BINDING TAPTITE P BZC 11
c 40011278 SCREW 3x8 BINDING TAPTITE P ZC 16
d 40011056 SCREW 3x6 BINDING TAPTITE B ZC 9
e 40011312 SCREW 3x8 BINDING TAPTITE P BZC 1
f 02126156 SECURITY SCREW HEX CAP SCREW M3x10 TAPTITE P NI 2

7
 Apr.2003

PARTS LIST
fig.part1e

SAFETY PRECAUTIONS: CONSIDERATION ON PARTS ORDRING

The parts marked have When ordering any parts listed in the parts list, please specify the following items in the order sheet.
safety-related characteristics. Use QTY PART NUMBER DESCRIPTION MODEL NUMBER
only listed parts for replacement. Ex. 10 22575241 Sharp Key C-20/50
15 2247017300 Knob (orange) DAC-15D
Failure to completely fill the above items with correct number and description will result in delayed or even
undelivered replacement.

NOTE: The parts marked # are new. (initial parts)

CASING QTY
# 03341889 PLAYING PLATE ASSY for SC 1
NOTE : PLAYING PLATE ASSY INCLUDES TOP PANEL
# ******** EDGE SHEET SENSOR for PAD 1-3 1
# ******** HEAD SHEET SENSOR for PAD 4-9 1
# ******** CUSHON 1
# ******** PCB SPACER CBS-19K 1
# ******** PLAYING PLATE 1
# ******** SENSOR ASSY 2
# ******** TOP CASE 1
# 03129545 TOP PANEL 1

# 03341890 BOTTOM CASE ASSY for SC 1

NOTE : BOTTOM CASE ASSY INCLUDES THE FOLLOWING PARTS
******** BOTTOM CASE 1
22365714 CORD HOOK 1
01344967 FOOT ^4
# 03129556 REAR PANEL 1

# 03341901 CF COVER ASSY 1

NOTE : CF COVER ASSY INCLUDES THE FOLLOWING PARTS
# ******** CF COVER 1
# ******** CF ESCUTCHEON 1
# ******** CF HOLDER 1

KNOB, BUTTON
# 03129489 R-KNOB for SC 2
12499175 JSPUE0011A KEY TOP for POWER SW 1

JACK, EXT TERMINAL

# 03129512 RUBBER SWITCH for SC 1
01676512 PUSH SWITCH SDKLA1-B POWER SWITCH SW3 1
# 03235345 SLIDE SWITCH SSSF141300 SLIDE SWITCH SW2 1

SWITCH
02341645 HTJ-064-04A 6.5MM JACK (STEREO) JK9 1
02897334 HTJ-064-10D for SC 6.5MM JACK (STEREO) JK4,JK7,JK8 3
02341712 HTJ-064-10I 6.5MM JACK (MONORAL) JK2,JK3,JK5,JK6 4
02341634 HTJ-020-05A DC JACK JK10 1
02568867 HDC-052A-12 MIDI CONNECTOR JK1 1

PWB ASSY
# 03129745 MAIN BOARD ASSY for SC 1
# 03129756 PANEL SHEET ASSY for SC 1

POTENTIOMETER
02565056 RK09K12A0D0K 9M/M ROTARY POT. VR1,VR2 2
# 03230601 EVUJFRFK1B14 9M/M ROTARY POT. VR4 1
# F3229136 RV112B-40E1-125A-A10K for SC 12M/M ROTARY POT. VR3 1

CONNECTOR
# 03121678 COMPACTFLASH CONNECTOR ICM-MA2H-SS52-R21A CN9 1
# 03121689 COMPACTFLASH EJECTOR ICM-MAE-R21 CN9 1

8
 SPD-S

WIRIING, CABLE
# ******** WIRING 1 40 PIN 1
# ******** WIRING 2 12 PIN 1

SCREW
40011056 SCREW M3x6 BINDING TAPTITE B ZC 9
40011278 SCREW M3x8 BINDING TAPTITE P ZC 16
40011312 SCREW M3x8 BINDING TAPTITE P BZC 1
40012501 SCREW M4x12 BINDING TAPTITE P BZC 11
# 40562967 SCREW M4x16 BINDING TAPTITE P NI 4

PACKING
# 03341878 PACKING SET for SC 1

MISCELLANEOUS
22365714 CORD HOOK 1
01344967 FOOT 4
# ******** SHIELD SHEET 1

ACCESSORIES (Standard)
# 03129701 OWNERS MANUAL JAPANESE 1
# 03129712 OWNERS MANUAL ENGLISH 1
# 03343323 LEAFLET JAPANESE/ENGLISH 1
00905756 AC ADAPTOR ACI-100C 1
00905767 AC ADAPTOR ACI-120C 1
01018312 AC ADAPTOR ACI-230C 1
01458278 AC ADAPTOR ACB-230E 1
12449549 AC ADAPTOR ACB-240(A) 1
# 03129723 CD-ROM SAMPLING CD for SC 1
# 40563778 STAND HOLDER MOUNTING SCREW HEX CAP SCREW M5x12 BZC 4
02126156 SECURITY SCREW HEX CAP SCREW M3x10 TAPTITE P NI 2
# ******** HEXAGON WRENCH 4MM 1
# ******** SLIT TAPE 1
40232334 WARRANTY CARD (JAPAN ONLY) 1

9
 Apr.2003

IDENTIFYING THE VERSION SAVING USER DATA &

NUMBER RELOADING SAVED DATA
1. Hold down the [ALL SOUND OFF] and [CARD] buttons and turn on the
power to the unit.
Required equipment
2. Press the [<]/[>] buttons to sequence through the display of the
following items. MIDI sequencer
MIDI cable

CPU Version, Build Number

fig.ver-1
BULK DUMP
CPU1.00 BLD0018
Settings for SPD-S setups and patches can be saved to an external MIDI device,
such as a sequencer.
CPU Release Date Operate the external sequencer for recording ordinary performance data and
fig.ver-2
then take the following steps for the SPD-S.
CPU DATE 12/16/02

CPU Release Time See the operation manual of the external MIDI device for details on it.
fig.ver-3

CPU TIME 13:25:25

1. Connect an external MIDI sequencer (as a saving destination) to the MIDI
OUT connector on the SPD-S using a MIDI cable.
fig.dump-e
EXT ROM Version, Build Number
fig.ver-4

PRG1.01 BLD0044
MIDI IN MIDI OUT
EXT ROM Release Date
fig.ver-5

PRG DATE 04/10/03

EXT ROM Release Time

fig.ver-6 External Seqencer

PRG TIME 08:39:14

SPD-S

Factory Data Version, Build Number 2. Set the SPD-S to the patch mode or to the wave mode.
fig.ver-7
3. Press [SETUP] button to access Setup Edit.
PRE 1.17 BLD012
4. Press the PAGE buttons to select BULK DUMP, then press [ENTER]
button.

3. Turn off the power to quit. 5. Press [+] button to select ALL.

6. Start recording on the external sequencer.

7. Press [>] button to display bulk dump, sure?

Press [ENTER] button to execute bulk dumping.

During transmission, now sending is displayed.

After the transmission is finished, a complete! indication appears and the
SPD-S returns to the Dump screen in Step 2.
To cancel the transmission midstream, press [EXIT] button.

8. Stop the external sequencer to stop recording.

10
 SPD-S

Retrieving Saved Data Back to 6. To quit Test mode:

the SPD-S Turn off the power to the unit.

Retrieves the settings saved to sequencers and other external MIDI devices to
the SPD-S.
1. Connect the MIDI IN connector on the SPD-S to the MIDI OUT connector
of an external sequencer using a MIDI cable.
2. Press [PATCH] button to enter patch mode.
* In each tested item, the screen initially shows the test type for a set length of
time, the display switches to the actual test screen.
* The BelTreeD sound is played when OK is returned and the procedure
advances to the subsequent test. When a test results NG, the FlexMtl sound
is played.

Test Mode Procedure

Bulk data cannot be retrieved in any mode other than patch mode.

3. Transfer the settings data from the external sequencer to the SPD-S.
The transferred settings are restored. Executing Test mode deletes the User data; be sure to back up the data stored
in the unit beforehand.
fig.audio

TEST MODE

Required items
Expression Pedal (EV-5 etc.)
Foot switch x3 (FS-5U etc.)
PAD (With a RIM switch function) x2 (PD-7, PD-9, CY-12 etc.) Rolan
d

Y cable (PCS-31) x2
Stereo jack plug Cable x1 Stereo jack Y cable
plug cable
Mono jack plug Cable x2
MIDI cable or red white

CompactFlash (Formatting using the SPD-S)

Monitor Speaker Pad with
a rim switch
Headphone

1. Using a Y cable, connect two foot switches to the FOOT SW jack.

Basic Test Mode Operations Make sure that the polarity is set properly here (set the foot switches to
open when the pedal is pressed; this should be the reverse of the TRIG IN
1. Proceeding with series of test:
switch).
Some of tests automatically advance to the next when the result is OK.
2. Use a stereo cable to connect a pad with a rim switch to the TRIG IN jack.
Alternatively, use a Y cable to connect one foot switch to the TRIG IN
Press [>] button (the LED flashes as a prompt). jack (plug in the Y cables red connector).
Make sure that the polarity is set properly here (set the foot switches to
short (close) when the pedal is pressed).
2. To advance to the next test forcefully even when the result is NG or
while running a test: 3. Connect an expression pedal to the EXP PEDAL jack.

4. Insert a CompactFlash card in the unit for tests.

Use a CompactFlash card formatted on the SPD-S.
Hold down [SHIFT] button and press the [>] button.
If updating of the factory data is required in 0. Factory Data Update,
use a CompactFlash card containing the factory data.
3. To return to the previous test:

Press the [<] button.

4. To return to the previous test forcefully:

Hold down [SHIFT] button and press the [<] button.

5. To repeat the current test:

Press [EXIT] button.

11
 Apr.2003

Entering Test Mode 2. Device Test

fig.test2-1
1. Insert the CompactFlash card in the card slot.

2. Hold down both [PHRASEMAKER] and [CARD] buttons and turn on the 2.Device Test
power.

3. Continue to hold down the buttons until [PATCH] and [EFFECTS]

1. When the test results OK, the - symbol changes to o; if the test
buttons light.
results NG (fail), the symbol changes to a charactor to represent the
4. Release [PHRASEMAKER] and [CARD] buttons. error type.
fig.test2-2
5. Press [EXIT] button.

6. Press [ENTER] button. DEV [------]

fig.test2-3

Test Items DEV [ooSoWC] NG!

0. Factory Data Load

Checked Items
When the CompactFlash contains factory data, the instrument compares its
version with the version contained internally, and if the CompactFlash I: CPU Internal: Checksum Comparison
contains a newer version, the unit automatically switches to Update mode. P: Program ROM: Checksum Comparison
If the data stored in the instrument is the later version, this mode is skipped. S: SDRAM: Write/Read
fig.test0-1 M: MR3 Chip: Write/Read
N: NAND Flash: Write/Read/Format
New Factory Data C: CompactFlash: Format (Write/Read Check)

1. Press the [ENTER] button to begin loading.

2. Press the [>] button to show which tests failed.
fig.test0-2
If multiple tests fail, use the [<] and [>] buttons to navigate (the [<] and
[ENTER] to Update [>] buttons flash as a prompt).
fig.test2-4

Loading. CPU Internal NG!

fig.test0-3

Now Loading... fig.test2-5

Program ROM NG!

When loading fails (in this case, press [EXIT] button to return to the previous
screen).
fig.test0-4 3. If all tests result OK, the process automatically advances to the
subsequent test.
Load Failed! fig.test2-6

DEV [oooooo] OK!

2. When loading completes normally, the process automatically advances to
the subsequent test.
fig.test0-5

3. MIDI Test
Load Completed!
fig.test3-1

3.MIDI Test
1. Version Test
fig.test1-1 1. Use a MIDI cable to connect SPD-Ss MIDI IN and MIDI OUT.

1.Version Test
Before Connecting
1. Confirm the version number. fig.test3-2
fig.test1-2
MIDI OUT-x-IN
CPU1.00 PRG1.01
Connected
2. Press the [>] button to advance to the subsequent test. fig.test3-3

MIDI OUT---IN OK

2. If the test results OK, the process automatically advances to the

subsequent test.

12
 SPD-S

4. Switch/LED Test 5. Effects Control Knob Test

fig.test4-1 fig.test5-1

4.SW/LED Test 5.CtrlKnob Test

fig.test4-2
1. Turn the [EFFECTS CONTROL] knob completely to the left
(22) (counterclockwise), and confirm that the value is 0 when the knob is
fully turned.
fig.test5-2

KNOB (108)
The number of switches that have not been checked is indicated in
parentheses. The following screen appears when the knob is turned fully to the left.
At this time, confirm that the CowbMmbo sound is played.
fig.test5-3

1. Using a Y cable, connect two foot switches to the FOOT SW jack.

KNOB (0)
2. Use a stereo cable to connect a PD-7 to the TRIG IN jack.
Alternatively, use a Y cable to connect one foot switch to the TRIG IN
jack (plug in the Y cables red connector). 2. Turn the [EFFECTS CONTROL] knob completely to the right.
3. Press the panel switches individually to comfirm that the name of the At this time, confirm that the BelTreeD sound is played.
switch being pressed appears in the display and that the corresponding 3. If the test results in OK, the process automatically advances to the
sound is played. subsequent test.
If the switch includes an LED, also confirm that the LED turns off when fig.test5-4

the switch is pressed.

KNOB (127) OK!
* For pad switches, press (grasp) the rim section.
* The test doesn't result OK when two or more panel switches are pressed
simultaneously. 6. Expression Pedal Test
The test also doesn't result OK when the foot switches (or a foot switch and
fig.test6-1
pad switch) are pressed simultaneously.
fig.test4-3
6.Exp.Pedal Test
(14) ALLSOUNDOFF
1. Connect an expression pedal to the EXP PEDAL jack.
4. The PAD LEDs turn off with each press of the [+] button. 2. Confirm that the value is 0 when the pedal heel is pressed down fully.
Confirm that all of the PAD LEDs go off. fig.test6-2
fig.test4-4
PEDAL (108)
(0) + (PAD1 LED)
The following screen appears in the display when the pedal heel is
pressed down fully.
Switches At this time, confirm that the CowbMmbo sound is played.
fig.test4-5 fig.test6-2

[PATCH] [WAVE] [PLAY/STOP] [SAMPLE]

[RESAMPLE] [EXIT] [ENTER] PEDAL (0)
[EFFECTS] [ALLSOUNDOFF] [CARD] [SETUP]
[EDIT] [LEFT/<] [RIGHT/>]
[PHRASEMAKER] [FUNC] [SHIFT] [-] [+]
[FOOTSW1] [FOOTSW2] [TRIGINSW] 3. Press the pedal toe down completely.
At this time, confirm that the BelTreeD sound is played.

4. If the test results in OK, the process automatically advances to the

5. If all of the switches pass their tests, the process automatically advances
subsequent test.
to the subsequent test.
fig.test6-3
fig.test4-6

(0) OK! PEDAL (127) OK!

13
 Apr.2003

7. LCD Test 8. Trigger Test

fig.test7-1 fig.test8-1

7.LCD Test 8.Trigger Test

1. Hold down the [INC/+] button and confirm that the LCD contrast 1. Using a Y cable, connect two pads to the TRIG IN jack.
changes gradually.
Holding down the [INC/+] button and pressing the [DEC/-] button
causes the contrast to change more rapidly.
When the contrast is at the maximum level, the screen shown below To disable the trigger while connecting or disconnecting the cable, hold down
appears. the [FUNC] button; the trigger is ignored while this button is pressed.
At this time, confirm that the Agogo Hi sound is played.
fig.test7-2
fig.test8-2

Hit "Softly"

2. Hold down the [DEC/-] button and confirm that the LCD contrast fig.test8-3
changes gradually.
Holding down the [DEC/-] button and pressing the [INC/+] button
123456789AB Soft
causes the contrast to change more rapidly.
When the contrast is at the minimum level, the screen shown below
2. Sheet Sensor Check
appears.
The test automatically checks whether or not the sheet sensor is turned
At this time, confirm that the Agogo Lo sound is played.
fig.test7-3
on while the pad is not being touched.
If no pad has a sheet sensor on, nothing appears in the display, and the
______________________ procedure advances to the subsequent test.

3. Press the [ENTER] button and confirm that the entire LCD is lit (the
[ENTER] button flashes as a prompt). Do not touch the pads while the check is in progress.
At this time, confirm that the Shaker sound is played.
fig.test7-2

If there is a pad with its sheet sensor on, the pads number is displayed,
the pad LED flashes, and the test result is NG.
fig.test8-4

4. Press the [ENTER] button and confirm that the entire LCD goes dark (the oo3oo67oo Sheet
[ENTER] button flashes as a prompt).
At this time, confirm that the Maracas sound is played.
fig.test7-4 3. Check response to weak hits by striking a lightly and individually.
Confirm that the corresponding number disappears and that the
corresponding sound is played.
The LED for each corresponding pad flashes and then goes off.
fig.test8-5
* Pressing the [ENTER] button cycles through the contrast check, all LCD on,
and all LCD off tests. ___456789AB Soft

5. If all tests result in OK, press the [>] button to advance to the
subsequent test.
The procedure does not advance unless all of the above tests are
The test does not result OK when two or more pads are struck
completed.
simultaneously.

A minimum interval of 0.1 seconds is required between each stroke of the

pads.

When a pad is struck hard, the corresponding number in LCD doesnt go off
and no sound is played although the pad LED lights, and the test doesnt
result OK.

4. If all pads are OK, the process automatically advances to the

subsequent test.
fig.test8-6

Hit "Hard"!
fig.test8-7

123456789AB Hard

14
 SPD-S

5. Check response to strong hits by striking a pad hard and individually. b. Velocity Check
Confirm that the corresponding number disappears and that the Strike each pad with a stick; when a pad is struck, the pad number and
corresponding sound is played. velocity value (1--127) is displayed, and the corresponding LED flashes
The LED for each corresponding pad flashes and then goes off. and then goes off.
fig.test8-8 fig.test8-13

___456789AB Hard ( ) Velo( )

Strike [Pad5].
fig.test8-14

When a pad is struck lightly, the corresponding number in LCD doesnt go off (Pad5) Velo(115)
and no sound is played although the pad LED lights, and the test doesnt
result OK.

When a pad has faulty sheet sensors that does not turn on, there is no response
The weak and strong checks can be switched by pressing the [ENTER] button. from the pad when it is struck.

Press the [ALLSOUNDOFF] button to return to the Sheet Sensor Check.

Correspondence Between the Pads and Press the [EXIT] button to return to the beginning of the Trigger Test.
Sounds
fig.test8-9

[1: Claves 2 ]
[4: Bongo Hi ]
[2: CowbMmbo ]
[5: Conga Hi ]
[3: Agogo Hi ]
[6: Xstick 3 ] 9. Audio Input Test
[7: 808Kik 1 ] [8: eSnr ] [9: AcuHH cl ]
[A(Trig1): 909Claps ] [B(Trig2): SpokTom1 ] fig.test9-1

9.Audio In Test
6. If all pads are OK, the process automatically advances to the
subsequent test.
fig.test8-10 1. Set the [VOLUME] knob to minimum, and turn the [INPUT LEVEL] knob
on the rear panel to the maximum setting.
[___________] OK! 2. Use two mono cables to connect the INPUT L/MONO and R to the
OUTPUT L/MONO and R.
fig.test9-2

Advanced Test Mode Set Volumes MIN

To enter Advanced Test mode, press the [ALLSOUNDOFF] button during the
Trigger Test.
3. Press the [ENTER] button.
This mode, you may check the causes of failure in the above test. fig.test9-3

[MIC] <- [LINE]

a. Sheet Sensor Check
If a pads sheet sensor turns on when the pad is pressed with the hand,
fig.test9-4
the corresponding number disappear, and the pads LED goes off.
Release the pads to return them to their original state.
fig.test8-11
(Level Meter Display)
123456789 Sheet
Above level meter is displayed, and a 100-Hz signal is output at -50 dBu.
Hand-press [Pad3]. The [START/STOP] button flashes.
fig.test8-12 4. Set the [LINE/MIC] switch to MIC and turn up [VOLUME] knob.
If the signal level is correct when [VOLUME] knob is turned right fully,
12_456789 Sheet
the process automatically advances to the subsequent test.
The level meter is displayed in the LCD.
Release [Pad3]. fig.test9-4

fig.test8-11

123456789 Sheet (Level Meter Display)

Press the [ALLSOUNDOFF] button to advance to the Velocity Check.

5. The LCD shows following display, then it returns to the level meter.
fig.test9-5

[MIC] -> [LINE]

A 100-Hz signal is output at -10 dBu.

[START/STOP] button lights, and [SAMPLE] button flashes.

15
 Apr.2003

6. Set [LINE/MIC] to LINE. 11. Completing Test Mode

If the signal level is correct, the signal automatically switches to 10 kHz,
and the same test runs. 1. If all of the tests in Test mode result in OK, shutdown for the card is
The [START/STOP] and [SAMPLE] buttons light, and the [RESAMPLE] executed.
fig.test11-1
button flashes.
If the tests result is OK, the process automatically advances to the shutdown..
subsequent test.

fig.test11-2

shutdown.. OK!
In this test, signal status is normal when six squares are displayed for both the
left and right channels in the LCD.
When the following is displayed, turn off the power to the unit.
fig.test11-3
At this time, the [WAVE] button lights.
Test Completed!

10. Sound Test 2. If any of the tests fails, the following is displayed.
fig.test10-1 fig.test11-4

10.Sound Test Not All Passed

1. Confirm that no sound is being played ([ENTER] LED flashes as a

prompt).
fig.test10-2
INITIALIZATION PROCEDURE
SOUND
Resets the SPD-Ss settings to initial values, or delete all the data stored in the
SPD-S.
2. Press [ENTER] button, and confirm that a sine wave is output from both
the left and right channels of OUTPUT and PHONES (the [EDIT] button
lights).
fig.test10-3

<<L SOUND R>> If you execute INIT/DELETE to delete patches and waves from the internal
memory, the SPD-S will produce no sound.

3. Press the [EDIT] button, and confirm that the output is muted (the mute
circuits activate). 1. Set the SPD-S to the patch mode or to the wave mode.

2. Press [SETUP] button to access Setup Edit.

3. Press the PAGE buttons to select INIT/DELETE, then press [ENTER]

button.
At this time, the sound is output at a very low level; this does not indicate any
4. Press [+] button to select ALL.
malfunction (the [ENTER] LED lights as a prompt).
fig.test10-4 5. Press [>] button to display delete all, sure?

<<L MUTE R>> 6. Press [ENTER] button to start initialization or deletion.

7. During execution, now processing? is indicated.

After the execution, a complete! indication appears, and the SPD-S
4. Press [ENTER] button, and confirm that a sine wave is output only from returns to the patch mode.
the left channel of OUTPUT and PHONES (the [ENTER] LED lights as a
prompt).
fig.test10-5

<<L SOUND Do not power the SPD-S off during execution.

5. Press [ENTER] button, and confirm that a sine wave is output only from
the right channel of OUTPUT and PHONES (the [ENTER] LED lights as a
prompt).
fig.test10-6

SOUND R>>

6. Press [ENTER] button, and confirm that no sound is being output (the
[ENTER] LED lights as a prompt).
fig.test10-7

SOUND

* Press [ENTER] button to cycle through Steps 3--6.

7. If the tests result OK, press [>].

16
 SPD-S

FORMATTING A RESTORING THE FACTORY

COMPACTFLASH CARD SETTINGS
1. To insert a CompactFlash card, carefully open the card slot cover (left- The accompanying CD contains audio signals for sampling on the SPD-S and
hand side of the SPD-S). digital data for restoring the SPD-S to its factory settings.
Restoring Patches and Waves to the Factory Settings
fig.cf-1
MEMORY CARD slot

Once you execute this operation, you will lose all the patches and waves stored
in the internal memory.
Back up such data beforehand if needed.

Required items
A computer with a CD-ROM drive
CompactFla
sh A card reader that supports CompactFlash cards
The accompanying CD-ROM (P/No.03129723)
CompactFlash (Formatted using the SPD-S)

2. Select patch mode or wave mode.

3. Press [SHIFT] and [SETUP] buttons (CARD UTIL). Procedure

1. Connect the card reader to the computer to ensure that it can be used.

If no CompactFlash card has been inserted, no card! is indicated and the

SPD-S returns to the original mode.
For connecting the card reader to the computer and using them, see their
respective operation manuals.
4. Press the PAGE buttons to select CARD FORMAT, then press [ENTER]
button.
2. Load the accompanying CD into the CD-ROM drive.

3. Insert the CompactFlash card into the card reader.

4. Copy the FCTRY folder on the accompanying CD to the ROLAND

When the CompactFlash card is unformatted, only CARD FORMAT is
displayed.
5. A [>] to format. indication appears. Press [>] button. 5.
6. A format, sure? indication is displayed. Press [ENTER] button to start
formatting.
While formatting is in progress, now processing.. is displayed. Then,
the SPD-S returns to the original mode.
folder on the CompactFlash card.
If the ROLAND folder on the CompactFlash card already has a
FCTRY folder, delete the FCTRY folder before copying.
Eject the CompactFlash card to which the copying was done in Step 4
from the card reader.
Then, make sure that the SPD-S is powered off and insert it into the card
slot of the SPD-S.
6. While holding down [PATCH], [WAVE], and [CARD] button ON the
SPD-S.

After powering it on, hold down the three buttons until [ENTER] to Load
appears.

7. [ENTER] to Load appears. Release the three buttons. Next, press

[ENTER].
Data transfer from the CompactFlash card to the SPD-S begins.
It takes a few minutes until it is complete.

During the data transfer, do not eject the CompactFlash card from the card slot
and do not switch off power to the SPD-S. Doing so could not only destroy the
data, but also cause problems for the SPD-S.

8. Load Completed! appears, and the data transfer is complete.

Now, eject the CompactFlash card, power the SPD-S off, then power it on
again.

17
 Apr.2003

PROCEDURE FOR UPDATING 5. When the update is completed normally, the [START/STOP], [SAMPLE],
and [RESAMPLE] LEDs light up.
THE SYSTEM SOFTWARE fig.up-3

Update Complate
The system can be updated using CompactFlash or MIDI.

If an error occurs during the procedure, all of the LEDs light up, and an

Instructions for Updating Using fig.up-4

error message is displayed.

CompactFlash Update ERROR 15

Required items
6. Turn off the power to end the procedure.
A computer with a CD-ROM drive
A card reader that supports CompactFlash cards
UPDATE CD-ROM for CF Card (P/No.17041324)
CompactFlash (Formatted using the SPD-S) Updating Using MIDI
Required items
1. Preparation A MIDI sequencer that can play back SMF data
Prepares a CompactFlash card containing the updated system file. UPDATE CD-ROM for SMF (#17041324)
MIDI Cable

1. Insert the CompactFlash in a card reader connected to a computer.

For instructions on connecting the computer and card reader, refer to the
service notes for formatting a CompactFlash.
2. Place the updated program in the CompactFlashs root (the top level).
This completes preparation of the updater CompactFlash.
1. Preparation
The following sixteen files are required for the updater SMF; confirmed that
they are present.
p00001.mid, p00002.mid, p00003.mid, p00004.mid
p00005.mid, p00006.mid, p00007.mid, p00008.mid
p00009.mid, p00010.mid, p00011.mid, p00012.mid
p00013.mid, p00014.mid, p00015.mid, p00016.mid

2. Update Procedure 2. Update Procedure

1. Hold down the [EFFECTS] and [ENTER] buttons and turn on the power
1. Use a MIDI cable to connect the MIDI OUT connector of a sequencer
to the unit.
capable of playing back SMFs and the MIDI IN connector on the SPD-S.
2. The [PATCH] and [PHRASEMAKER] buttons flash.
2. Hold down the [WAVE] and [ENTER] buttons and turn on the power to
fig.up-1
the unit.
Card Updater 3. The [SETUP] and [EDIT] buttons flash.
fig.up-5

* To cancel the update at this point, turn off the power to the SPD-S. MIDI Updater

3. Press the [PATCH] and [PHRASEMAKER] buttons simultaneously. * To cancel the update at this point, turn off the power to the SPD-S

4. The update begins.

The process is divided into sixteen steps, and in each step, the 4. Press the [SETUP] and [EDIT] buttons simultaneously.
fig.up-6

[START/STOP] -> [SAMPLE] -> [RESAMPLE] Please Send

LEDs light in sequence.

fig.up-2
5. Play back p00001.mid through p00016.mid in sequence.

6. The update begins, and with each file, the

Update: **/16
[START/STOP] -> [SAMPLE] -> [RESAMPLE]
* The ** indicates the step number currently being processed (01--16).

LEDs light in sequence.

fig.up-2

Update: **/16

* The ** indicates the file currently being executed (01--16).

18
 SPD-S

7. When the update is completed normally, the [START/STOP], [SAMPLE],

and [RESAMPLE] LEDs light up.
fig.up-3

Update Complate

If an error occurs during the procedure, all of the LEDs light up, and an
error message is displayed.
fig.up-4

Update ERROR 15

8. Turn off the power to end the procedure.

19
 Apr.2003 SPD-S

BLOCK DIAGRAM
fig.block

A +9
RIPPLE
D +5 FILTER
RESET IC
D +5

6
120 PC410 2.2k S-80927CLMC-G6X-T2
14 1 100k D +3 . 3 D +3 . 3 D +3 . 3 D +3 . 3 D +3 . 3 D +3 . 3
4

12 5 DC-DC 2 1 XRESET
IN

VCC OUT
2

15 3 NJM2360AM Others Par ts

@40
D +5
5

4
100
SDRAM NOR FLASH ComapctFlash D +5
NC

2
MIDI 3 5

4
1 2 1 REGULATOR GND CD
XRESET
220
RT1P141C
for Cache/Work/Delay Line for Program for Patch,Wave Storage NJM78L05UA 0.1
24 10k D +5
HD74LS05FP
4

22 MIDI_IN
16Mbit 8Mbit
OUT

3
2

25 2 1 2 1 MIDI_OUT Others Par ts

@40
5

DC-DC
220 NJM2360AM
HD74LS05FP HD74LS05FP

1
A -9
CPU P O W E R SW
30
40
50
60

V850E/MA1

2
2
DC IN 1
ANI[0..7] 3

D +3 . 3 RIM[1..10] ACI or ACB

PAD 1 16bit 16bit 16bit 9V/1000mA A
P1
F S R Only P2
MXPAD BUS BUFFERS
1 2 RIM1
UPD70F3107AGJ- UEN (SPD-S 1.01)
D +3 . 3
PAD 2
F S R Only
1 2 RIM2
16bit 8 b it
D +3 . 3 D +3 . 3 D +5 D +3 . 3 D +3 . 3
PAD 3
F S R Only
1 2 RIM3
NAND FLASH Gate Array DSP
6
PAD4
-
7 ANI0 D +3 . 3 for Preset,User Wave
w. FSR
5
+ System Parameter V850E GA
BA10324AF 1 2 RIM4
128Mbit
9
- D +3 . 3
PAD5 8 ANI1
10

XP-LRCK

12
+

LRCK0
LRCK1
w. FSR

LRCK
MCK

MCK
BCK

BCK
clk=50MHz

SYI
BA10324AF 1 2 RIM5 LINE/MIC
13
- D +3 . 3
PAD6 14 ANI2 1 4 1 2

13
11
12
+
w. FSR fx=5MHz 11.2896MHz(256fs) INPUT
BA10324AF 1 2 RIM6 L E V EL 2
-

8bit
1
2 2 3 2 LINE IN

11
- D +3 . 3 - +
PAD7 1 ANI3 1 4
3 3 12 1 L(MONO)
+ + M5218AFP
w. FSR
AD/DA A

13
BA10324AF 1 2 RIM7 M5218AFP LINE -10dBu
A 6

PAD8
2
-
1 ANI4 D +3 . 3 CODEC 6
7
-
5 2
MIC -50dBu

21
- +
3 24bit/512fs/GD=15.4 7 4 LINE IN
+
w.FSR 5 22 1
+ M5218AFP R
M5218AFP
1 2 RIM8 A
M5218AFP

23
6 A
PAD9
w.FSR
5
-

+
7 ANI5 D +3 . 3
MAIN BOARD D +3 . 3 D +3 . 3
P H ONES
10 10 2 LEVEL
M5218AFP -
1 2 RIM9 1

4
3 2

11
+ -
1 2

VA
VD
2 12 3 3 P H ONES
LIN M5218AFP +
1 2 RIM10 1
9 1
SDTI RIN

13
2 M5216FP A PHONES +15dBu
-
2 9 1 ANI6 15 6 A
- LOUT -
TRIG IN 3 8 5 4 3 8 7
0Z ZCOM + SDTO
1 10 2 16 5 6

21
(1/2) + 0Y D +3 . 3 ROUT + -
12 15 7
0X YCOM M5218AFP
3 10 14 22 5
1Z LRCK VCOM M5218AFP +
BA10324AF 1 14 11
13 1Y XCOM 12 MCLK

23
13 1X 9 6 7 BCLK M5216FP
- C - DEM1
14 10 7 ANI7 6 A
B XPDN DEMO

VSS
12 11 5 13 0.1 1/50
+ A +9 A + PDN
VSS

16 7
INH

VDD VEE M5218AFP

BA10324AF

3
A +9 A
D +3 D +3
6
8

CD4053BCSJ

5 R?
4 10k
D +5
FOOT 2 P1
PANEL SHEET 2

11
SW
3
7
P2
SW Matr ix 12 3
-

+
1 2
4 OUTPUT
3

(1/2) 8
1 1 MXPAD ( RU B B E R )
1 2
(PANEL BOARD) LCD M5218AFP
1
L

13
A (MONO)
RT1N141C 16x1 Charactor A
2

LINE +4dBu
RCM2122M-1A 6

21
D +3 . 3
6
-
/RCM2122M-A LED Matrix 22 5
-

+
7 2
4 OUTPUT
7 1
2 5 1 2 R
+ M5218AFP

23
EXP PEDAL 3 A
1 A
BA10324AF
V O LUME
D +3 . 3
2
-
1

E F FECTS
CONTROL
2 3
+
1
PANEL SHEET
BA10324AF (VOLUME BOARD)
3

20 21
 Apr.2003 SPD-S

CIRCUIT BOARD (MAIN)

fig.main-comp-slk

View from components side

22 23
 Apr.2003 SPD-S

CIRCUIT BOARD (MAIN)

fig.main-foil-ptn

View from foil side

24 25
 Apr.2003 SPD-S

CIRCUIT DIAGRAM (MAIN 1/8)

fig.main1-c

A[0..9] A[0..9]
D[0..15] D[0..15]
IC2 A13
UPD70F3107AGJ-UEN (Trial)
UPD70F3107AGJ-UEN (SPD-S 1.00) (1Lot-1.99Lot)
UPD703106AGJ-066-UEN (SPD-S) (2Lot-) XDMARQ3 XDMARQ3
XDMARQ1 XDMARQ1
D +3. 3 3 D +3. 3 D +3 . 3 D +3 . 3 XDMARQ0
A2 XDMARQ0
SD4 39 116 8 9 A23 A23 8 9 2 8
40 TC3/IP113/P27 PAH7/A23 117 7 10 7 10 1 A1 VCC
SD3 A22 A22 XDMAAK[0..1]
41 TC2/IP112/P26 PAH6/A22 118 6 11 6 11 A0 C1
SD2 A21 A21

16
15
14
13
12
11
10

16
15
14
13
12
11
10
TC1/IP111/P25 PAH5/A21

9
SD1 42 119 5 12 A20 A20 5 12 EEP_SDA 5 NIU XDMAAK1
P[1..2] TC0/IP110/P24 RA1 PAH4/A20 SDA
SD0 43 120 4 13 A19 A19 4 13 RA2 EEP_SCK 6 4 RA3 RA4 XDMAAK0
44 TO02/P23 47 PAH3/A19 121 3 14 3 14 10k 7 SCL VSS
P2 A18 A18 10k 10k LDQM/XLWR
45 IP021/P22 PAH2/A18 122 2 15 2 15 WP
P1 A17 A17 XRD
46 TIO20/IP020/P21 PAH1/A17 123 1 16 1 16
A16 A16 D IC1 D

1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
NMI/P20 PAH0/A16 RA7 XGA_CS
126 8 9 A15 A15 8 9 HN58X2408FPI
PAL15/A15 22 XNF_CS
D 127 7 10 A14 A14 7 10 NIU
RIM[1..10] PAL14/A14 XCF_CS
128 6 11 A13 A13 6 11 A20 19 49 DQ15 1 16 D15 A19 16 45 D15
PAL13/A13 BA DQ15 A18 A-1/DQ15 XDSP_CS
RIM1 50 129 5 12 A12 A12 5 12 A11 20 48 DQ14 2 15 D14 A18 17 43 D14
IP122/P36 RA5 PAL12/A12 A10/AP DQ14 A17 DQ14 GA_CLK
RIM2 51 130 4 13 A11 A11 4 13 RA6 A10 32 46 DQ13 3 14 D13 A17 48 41 D13
IP121/P35 PAL11/A11 A9 DQ13 A16 DQ13 XWAIT_EN
RIM3 52 47 131 3 14 A10 A10 3 14 10k A9 31 45 DQ12 4 13 D12 A16 1 39 D12
RXD2/IP120/P34 PAL10/A10 A8 DQ12 A15 DQ12 XWAIT
RIM4 53 132 2 15 A9 A9 2 15 A8 30 43 DQ11 5 12 D11 A15 2 36 D11
54 TXD2/IP133/P33 PAL9/A9 133 1 16 1 16 29 A7 DQ11 42 6 11 3 A14 DQ11 34 GA&DSP Section
RIM5 A8 A8 A7 DQ10 D10 A14 D10
RIM6 55 SCK2/IP132/P32 PAL8/A8 136 8 9 A7 A7 8 9 A6 28 A6 DQ10 40 DQ9 7 10 D9 A13 4 A13 FLASH DQ10 32 D9
56 SI2/IP131/P31 PAL7/A7 137 7 10 7 10 27 A5 DQ9 39 8 9 5 A12 DQ9 30
RIM7 A6 A6 A5 DQ8 D8 A12 D8
RIM8 65 SO2/IP130/P30 PAL6/A6 138 6 11 A5 A5 6 11 A4 24 A4 DQ8 12 DQ7 1 16 D7 A11 6 A11 8Mb DQ8 44 D7
66 SCK1/P45 PAL5/A5 139 5 12 5 12 23 A3 DQ7 11 2 15 7 A10 DQ7 42
RIM9 A4 A4 A3 DQ6 D6 A10 D6 A[1..11]
67 RXD1/SI1/P44 RA8 PAL4/A4 140 4 13 4 13 RA9 22 A2 DQ6 9 3 14 8 A9 DQ6 40
RIM10 A3 A3 A2 DQ5 D5 A9 D5
TXD1/SO1/P43 47 PAL3/A3 141 3 14 3 14 10k 21 A1 DQ5 8 4 13 18 A8 DQ5 38
A2 A2 A1 DQ4 D4 A8 D4 D[0..15]
SW1A D +3. 3 PAL2/A2 142 2 15 2 15 A0 DQ4 6 5 12 19 A7 DQ4 35
SSSS222-01-A A1 A1 DQ3 D3 A7 D3
PAL1/A1 143 1 16 1 16 18 DQ3 5 6 11 20 A6 DQ3 33
NIU A0 A0 XSD_CS DQ2 D2 A6 D2
11 PAL0/A0 17 CS DQ2 3 7 10 21 A5 DQ2 31
SI0 XSD_RAS DQ1 D1 A5 D1 CF_XATA/IDE
13 12 R256 144 8 9 16 RAS DQ1 2 8 9 22 A4 DQ1 29
D15 XSD_CAS DQ0 D0 A4 D0 XCF_OEGATE
10k PDL15/D15 1 7 10 15 CAS DQ0 23 A3 DQ0
D14 XWE A3 XCF_CS
69 D14/PDL14 2 6 11 WE RA10 D +3 . 3 24 A2
MIDI_IN R1 100k D13 22 A2 XRD
MIDI_OUT(SO0) 70 RXD0/SIO/P41 D13/PDL13 3 5 12 D12 UDQM 36 1 A1 25 A1
TXD0/SO0/P40 R2 NIU RA11 D12/PDL12 UDQM VDD A0 LDQM/XLWR
4 4 13 D11 LDQM/XLWR 14 25
D11/PDL11 LDQM VDD XBCYST
SCK0 68 22 5 3 14 D10
SCK0/P42 D10/PDL10 6 2 15 7 D +3 . 3 9
D9 'CF_R/XB
D9/PDL9 7 1 16 VDDQ 13 NC 10
D8 'XCF_SC
D +3 . 3 D8/PDL8 10 8 9 34 VDDQ 38 NC D +3 . 3 D +3 . 3
D7 SD_CKE Q1
D7/PDL7 11 7 10 35 CKE VDDQ 44 R10
D6 SD_CLK D CF_XON/OFF
D6/PDL6 CLK VDDQ 10k D +3. 3 RN2421

2
R257 12 6 11 D5 13
D5/PDL5 VPP CF_RESET
10 13 5 12 D4 47 37 1 FL_VPP
RA12 D4/PDL4 BYTE VCC CF_RESETZ
71 14 4 13 D3 C13 XFL_CS 26
C5 AVDD/AVREF 22 D3/PDL3 15 3 14 D2 SDRAM 4 SLP@M LDQM/XLWR11
CE XCF_DETECT
C6 D2/PDL2 16 2 15 VSSQ 10 28 WE CF I/F Section
D1 XRD
SLP@M 16Mb VSSQ 10/16

3
0.1 D1/PDL1 17 1 16 41 14 OE
D0 XFL_WP
10/16
72 CPU - V850E/MA1 D0/PDL0 37 VSSQ 47 FL_R/XB 15 WP 27
AVSS 49 33 NC/RFU VSSQ 12 RY/BY GND 46
ANI[0..7] 'CF_R/XB XRESET
ADTRG/IP123/P37 NC 26 RP GND
D
73 83 VSS 50 R4
ANI7 FL_R/XB IC4 D D D XPDN
74 P77/ANI7 P52/TO03 84 RA30 VSS C7 C8 C9 C10 C11 C12 0 C14
ANI6 FL_VPP LH28F800BJE-PBTL90@ AMUTE
75 P76/ANI6 P51/IP031 85 10k D +3. 3 1 1 1 1 1 1 100p (LH28F160BJE) C2 C4 R3
ANI5 XFL_WP D D
76 P75/ANI5 P50/IP030/TI030 86 4 5 (LH28F320BFE) 0.1 0.1 10k
ANI4 CF_XATA/IDE XFL_WP IC3
77 P74/ANI4 PCM5/SELFREF 87 Audio Section
ANI3 XCF_OEGAT E CF_XATA/IDE 3 6 GLT5160L16 -7TC C3
78 P73/ANI3 PCM4/REFRQ 88
ANI2 CF_RESET XCF_OEGAT E2 7 D SLP@M
79 P72/ANI2 PCM3/HLDRQ 89
ANI1 CF_XON/OFF CF_RESET 1 8 10/16
80 P71/ANI1 PCM2/HLDAK 90 8 9
ANI0 GA_CLK GA_CLK
P70/ANI0 R9 47 PCM1/CLKO/BUSCL 91 7 10
XWAIT D
PCM0/WAIT 92 6 11
XBCYST XBCYST MIDI_IN
19 R244 47 PCT7/BCYST 93 R11
XDMARQ3 XWAIT_EN XWAIT_EN 5 12 A23 (B)
MIDI_OUT(SO0)
20 DRQ3/IP103/P07 PCT6/OE 94 4 5 4 13 RA13 (A) R12 NIU 16Mbit 64Mbit 128Mbit
XWE XWE A22
21 DRQ2/IP102/P06 PCT5/WE 95 3 6 3 14 10k NIU (B) NIU NIU 0
XDMARQ1 XRD XRD
22 DRQ1/IP101/P05 RA14 PCT4/RD 96 2 7 2 15 (B) R13 (A) NIU 0 NIU Jack Section
XDMARQ0 UDQM UDQM A22
23 DRQ0/IP100/P04 22 PCT1/UCS/UW/UDQ 97 1 8 R15 NIU
XPDN LDQM/XLWR LDQM/XLWR 1 16 A21 (A) IC3 Mounting NIU NIU
24 TO00/P03 PCT0/LCS/LW/LDQ NIU IC5 NIU Mounting Mounting
RING/XRIM IP001/P02
25 100 8 9 XDSP_CS XDSP_CS 8 9
MXPAD TIO00/IP000/P01 R17 100 PCS7/CS7
'LCDCONT 26 101 7 10 XCF_CS XCF_CS 7 10
PWM0/P00 R18 1.5k PCS6/CS6/RAS6 102 6 11 6 11
XNF_CS XNF_CS
C15 C325 R245 D +3. 3 PCS5/CS5/IORD 103 5 12 5 12
'XCF_SC SS[0..3]
Trigger Section 1 33p 10k RA15 PCS4/CS4/RAS4 104 4 13 4 13 RA16 20 53
XCF_DETECT BA2 DQ15
22 PCS3/CS3/RAS3 105 3 14 3 14 10k 21 BA0(A13) DQ15 51
XGA_CS XGA_CS BA1 DQ14 SS3
R259 R246 PCS2/CS2/IOWR 106 2 15 2 15 35 BA1(A12) DQ14 50
XSD_CS XSD_CS A12 DQ13 SS2
10k 10k PCS1/CS1/RAS1 107 1 16 1 16 22 A11 DQ13 48
D XFL_CS XFL_CS A11 DQ12 SS1
29 PCS0/CS0 108 4 5 34 A10 DQ12 47
AMUTE XSD_RAS XSD_RAS A10 DQ11 SS0 SD[0..4]
30 DMAAK3/PBD3 R19 47 PCD3/UBE/SDRAS 109 3 6 RA17 33 A9 DQ11 45
CF_RESETZ XSD_CAS XSD_CAS A9 DQ10
31 DMAAK2/PBD2 R20 47 PCD2/LBE/SDCAS 110 2 7 10k 32 A8 DQ10 44
XDMAAK1 SD_CLK SD_CLK A8 DQ9 SD4
32 DMAAK1/PBD1 R21 47 PCD1/SDCLK 111 1 8 31 A7 DQ9 42
XDMAAK0 SD_CKE SD_CKE A7 DQ8 SD3
1 8 33 DMAAK0/PBD0 R22 47 PCD0/SDCKE 114 30 A6 DQ8 13
SS3 R5 NIU EEP_SCK EEP_SCK A6 DQ7 SD2
2 7 34 TO01/P13 PAH9/A25 115 29 A5 DQ7 11
SS2 R6 NIU EEP_SDA EEP_SDA A5 DQ6 SD1
3 6 35 IP011/P12 RA46 PAH8/A24 26 A4 DQ6 10
SS1 R7 D A4 DQ5 SD0
4 5 36 TIO10/IP010/P11 47 D +3 . 3 25 A3 DQ5 8
SS0 NIU A3 DQ4
60 PWM1/P10 18 C345 24 A2 DQ4 7
FZ_VPP R8 A2 DQ3 'LCDCONT
C16 CKSEL VPP/MODE2 57 NIU 23 A1 DQ3 5
NIU A1 DQ2
22p MODE1 58 A0 DQ2 4
D DQ1
62 MODE0 C17 R23 19 DQ1 2 CN Section
XSD_CS DQ0
X2 CS DQ0
2

X1 NIU 10k D XSD_RAS 18

C18 17 RAS D +3 . 3
SD3@ XSD_CAS
22p 16 CAS 1
5MHz XWE
63 WE VDD 14
D D D
X1 39 VDD 27
UDQM
1

15 DQMU VDD
D LDQM/XLWR
D +3 . 3 134 DQML 3
D +3 . 3 61 VDD 124 VDDQ 49
C19 CVDD VDD 112 VDDQ 9
C20 VDD 98 37 VDDQ 43
SLP@M SD_CKE
R255 0.1 VDD 81 38 CKE VDDQ
10/16 SD_CLK
NIU 64 VDD 37 CLK 12
CVSS VDD 47 VSSQ 46
XFZ_RST 21 VDD 27 D +3 . 3 SDRAM VSSQ 6
D
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

23 22 59 VDD 8 36 64/128Mb VSSQ 52

XRESET RESET VDD NC VSSQ
40
SW1B C31 NC 28
SSSS222-01-A VSS
C21 41
28
48
38
82
99

SLP@M
113
125
135
9

NIU VSS
100p 10/16 54
VSS
R24 IC5 D
0 (M2V64S40DTP-7)
D D C22 C23 C24 C25 C26 C27 C28 C29 C30 (TC59SM716AFT-8 0)
XRESET 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 NIU

CPU FLASH WRITER

D +3. 3
7 FZ_VPP
7 6
6 5 XFZ_RST
5 4 C322
SCK0
4 3 SI0 WLP@M
3 2 MIDI_OUT(SO0) NIU
2 1
1
D D
CN1
B7B-PH-K-S
NIU

Under Development Only

*SW1 SSSS222-01-A
*CN1 IL-S-7P-S2T2-EF
*C322 100u
*R255 10k
*C17 0.1u
*R1,R24 Pattern cut

26 27
 Apr.2003 SPD-S

CIRCUIT DIAGRAM (MAIN 2/8)

fig.main2-c

A[0..9] D +3. 3
C32
D[0..15] SLP@M SDTI
C33 C34 10/16
0.1 0.1 LRCK
C35 C36 MCK
131 2
A19 NC 0.1 0.1 BCK
A13 A13 A13 130 3 R25 RA18
A18 NC C37 C38
A9 26 34 10k 10k
SDTO
A9 NC D +3. 3 0.1 0.1
A8 25 35
A8 NC C39 C40
A7 24 71
A7 NC 0.1 0.1 Audio Section
A6 23 74 D
A6 NC

5
6
7
8
A5 22 75 D D NF_D7 44 48

14
15
23
24
33
38
49
56
59
64
73
79
A5 NC I/O8 NC

7
A4 21 NF_D6 43 47
A4 I/O7 NC
A3 20 NF_D5 42 46

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A3 D +3 . 3 I/O6 NC
A2 17 NF_D4 41 45
XLS[0..3]
A2 I/O5 NC
A1 16 96 A4 44 74 NF_D3 32 40

4
3
2
1
A1 SW 76 45 CA4 DA3 75 31 I/O4 NC 39
A3 NF_D2 XLS3
PROTECT 82 46 CA3 AD3 69 30 I/O3 NC 38
D NF_R/XB A2 NF_D1 XLS2
15 R/B 77 47 CA2 DA2 29 I/O2 NC 35
D15 NF_CLE A1 NF_D0 XLS1
14 D15 CLE 78 48 CA1 I/O1 NC 34
D14 XNF_CE A0 XLS0
D13 13 D14 V850E GA CE 79 NF_ALE
CA0 MR3 NC 33
LD[0..6]
12 D13 ALE 80 1 NC 28
D12 XNF_RE LD6
11 D12 RE 81 27 2 NC NC 27
D11 XNF_WE D7 LD5
10 D11 WE 83 28 CD7 3 NC NC 26
D10 XNF_WP D6 LD4
9 D10 WP 29 CD6 4 NC NC 25
D9 D5 LD3
8 D9 86 30 CD5 5 NC NC 24
D8 D NF_D7 D4 LD2
7 D8 SM-D7 88 34 CD4 10 NC NC 23
D7 NF_D6 D3 LD1
6 D7 SM-D6 94 35 CD3 72 D +3 . 3 11 NC NC 22
D6 NF_D5 D2 LD0
5 D6 SM-D5 95 36 CD2 CTYPE 14 NC NC
D5 NF_D4 D1 NAND LDG LDG
4 D5 SM-D4 89 37 CD1 15 NC
D4 NF_D3 D0 LCD[0..7]
142 D4 SM-D3 87 CD0 R55 20 NC FLASH
D3 NF_D2
141 D3 SM-D2 85 78 1.5k 21 NC
D2 NF_D1 128Mb LCD7
140 D2 SM-D1 84 TESTT 32 NC
D1 NF_D0 LCD6
139 D1 SM-D0 TESTS 77 7 D +3. 3
D0 NF_R/XB LCD5
D0 102 65 TESTB 13 17 R/B 12
R28 100 MCK NF_ALE LCD4
D +3. 3 MCK 103 60 MCK TESTP 10 16 ALE VCC 37
R30 100 BCK NF_CLE LCD3
BCK 104 63 BCK PLLBP 19 CLE VCC C68
R32 100 LRCK XNF_WP LCD2
LRCK LRCK1 WP
D R37 D +3. 3
8
7
6
5

XNF_CE 9 SLP@M LCD1

RA19 C326 16 27k CE 6 10/16 LCD0
10k 22p 62 PLLVAA 17 C43 8 GND 36
XNF_RE LE
101 68 LRCK0 PLLRO 18 C42 18 RE VSS 13
D SLP@M XNF_WE R/XW
(DSP) DAOUT1 100 67 AD1 PLLLP 19 0.1 WE VSS
10/16
1
2
3
4

XDMARQ3 ADIN1 DA1 PLLAGS RS

134 99 58 20 IC13 D D
(AD) 133 DMA-REQ2 DAOUT0 98 70 AD0 PLLAGD C41 C254 C67
XDMARQ1 SDTO TC58128AFT
(DA) 132 DMA-REQ1 ADIN0 57 AD2 3900p 0.1 0.1 CN Section
XDMARQ0 SDTI R258 100 D
DMA-REQ0 DA0 1
92 55 OSC 3
XDMAAK[0..1] 512fs R43 100
137 XTAL 93 9 DIV OSCSEL
DMA-ACK2 EXTAL DIVS1
XDMAAK1 (AD) 136 C327 8 D 'XCF_WAIT
DMA-ACK1 DIVS0
XDMAAK0 (DA) 135 46 33p 5
XCF_DETECT
DMA-ACK0 SPRX-SD 45 XTO
D
SPRX-BCK R44

2
44 D C45 X2 CF I/F Section
27 SPRX-LRCK 49 76 15 18p
LDQM/XLWR CPU-WR XP-LRCK SYI SD3@
28 56 11.2896MHz
XRD CPU-RD XP-CLK
29 51 (256fs)
XGA_CS CPU-CS XP-SCK
30 50 6

1
31 XP-CS-IN XP-WCK 52 41 XTI
XNF_CS SM-CS-IN XP-SD-AR-TRG INT1
128 53 40 R46 C46 D
XCF_CS CD-CS XP-WR-AR-TRG D +5 D +5 INT0
XRD XDMARQ3 39 1M 18p
C256 50 DRQ
XDSP_CS XDSP_CS XRD
42 0.1 51 RD
LDQM/XLWR XDSP_CS
AR-SYNC-WCK CS
5

43 D LDQM/XLWR 53
138 WCK-IN 1 25 WR
INT-OUT 47 RST
5XCF_WAIT 4 XRESET 42 IC7
124 WAIT-CA 48 2 DRST TC220C120AF-006(MR3)
'XCF_WAIT
CPU-WCK WAIT-CB-XP-WAIT R48
IC37

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
32 41 0
GA_CLK PHAI PLL-SEND SN74AHCT1G08DCKR
GA_CLK 57 C47
3

PLL-RTRN R49
38 D 100p
PLL-LOCK 100
110 40

11
12
21
22
26
31
43
52
54
61
66
71
80
2
4
XWAIT_EN ENC-A S2
111 D+5V I/F 39 LDG D
XWAIT ENC-B S1
CPU Section RA20 D 97 D
100 TEST 106 D +5
8 9 123 NC 107 D
7 10 122 7SEG-D7 NC 143 RA21 R50
LD6
6 11 121 7SEG-D6 NC 100 10k
LD5
5 12 120 7SEG-D5 60 8 9
LD4 LCD7
4 13 119 7SEG-D4 LCD-D7 61 7 10 +
LD3 D+5V I/F LCD-D6 LCD6
3 14 118 7SEG-D3 62 6 11
LD2 LCD5
2 15 117 7SEG-D2 LCD-D5 63 5 12
LD1 LCD4

16
15
14
13
12
11
10
7SEG-D1 LCD-D4

9
LD0 1 16 116 64 4 13 LCD3
7SEG-D0 LCD-D3 65 3 14 RA47
LCD2
105 LCD-D2 66 2 15 10k
LCD1
4 5 115 7SEG-COM4 LCD-D1 67 1 16
XLS3 LCD0
3 6 114 7SEG-COM3 LCD-D0 68
XLS2 LE

1
2
3
4
5
6
7
8
2 7 113 7SEG-COM2 R51 NIU LCD-E 69
XLS1 R52 100 LCD-RW R/XW
1 8 112 7SEG-COM1 70
XLS0 R53 100 LCD-RS RS
7SEG-COM0 58
RA22 RESET-CTRL 59
100 LCD-POWER-UD
33 125 XGA_WAIT
XRESET RESET WAIT-OUT
XRESET 129 XCF_DETECT
R54 CD-DETECT D +3. 3
0
C48
100p 18 L46 C324 D
VDD 37 0.1
VDD 73
D
VDD 90 +
VDD 109
D +5 VDD 126 D +3. 3
54 VDD 144 + +
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VDD VDD C257

C49 C58 0.1
20

C316

5
SLP@M SLP@M D D
9 12 XSFT_WAIT 1 0.1
19
36
55
72
91

10/16 10/16
1

108
127

VCC

8 D7 Q7 13 4
7 D6 Q6 14 2
6 D5 Q5 15 IC54
C50 C51 C52 C53 C54 C55 C56 C57 5 D4 Q4 16 SN74AHC1G08DCKR
D IC6
0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 4 D3 Q3 17
LC24085B-SD1

3
3 D2 Q2 18 D
2 D1 Q1 19
XGA_WAIT
D0 Q0
XWAIT_EN 1 XWAIT
GND

11 OE
GA_CLK
CK
IC39
74LV574PW
10

D
XGA_WAIT

28 29
 Apr.2003 SPD-S

CIRCUIT DIAGRAM (MAIN 3/8)

fig.main3-c

D +3 . 3 CF_A[0..10]
A[1..11] L36 C259
0.1

20
D[0..15]
D
A10 2 18 1 16 CF_A10

VCC
3 A1 B1 17 2 15
A9 CF_A9
4 A2 B2 16 3 14
A8 CF_A8
5 A3 B3 15 4 13
A7 CF_A7
6 A4 B4 14 5 12
A6 CF_A6
7 A5 B5 13 6 11
A5 CF_A5
8 A6 B6 12 7 10
A4 CF_A4
9 A7 B7 11 8 9
A3 CF_A3
A8 B8
1 RA31

GND
19 DIR 22
XCF_G1
OE

IC40

10
D SN74LV245APWR
D +3 . 3
L37 C261
0.1

20
D C262 CF_A10
C263 100p
CF_XATA/IDE A2 9 11 8 9 CF_A2 CF_A9

VCC
CF_XATA/IDE A8 B8 100p C264
XCF_OEGAT E A1 8 12 7 10 CF_A1 CF_A8
XCF_OEGAT E A7 B7 C265 100p
XCF_CS 7 13 6 11 CF_A0 CF_A7
XCF_CS A6 B6 D +3 . 3 100p C266
XRD 6 14 5 12 CF_A6
XRD A5 B5 C267 100p
LDQM/XLWR D 5 15 4 13 4 5 CF_A5
LDQM/XLWR A4 B4 100p C268
XBCYST 4 16 3 14 'XCF_WAIT 3 6 CF_A4
XBCYST A3 B3 RA36 C269 100p
3 17 2 15 'XCF_SC 2 7 CF_A3
A2 B2 100p C270
2 18 1 16 'CF_R/XB 1 8 10k CF_A2
'CF_R/XB A1 B1 C271 100p
'XCF_SC 100p CF_A1
1 RA35 C272 CF_A0

GND
DIR 100p
XCF_G1 19 22
CF_XON/OFF OE
CF_RESET D
CF_RESETZ IC42

10
XCF_DETECT
D SN74LV245APWR
'CF_R/XB
CPU Section 'XCF_SC
'XCF_WAIT D +C F
CF_R/XB CF_R/XB 4 5
XCF_SC XCF_SC 3 6
XCF_WAIT XCF_WAIT 2 7 RA37
XCF_DETECT
'XCF_WAIT XCF_DASP 1 8 10k

GA&DSP Section D +3 . 3 CF Accsess Chart

L38 C275
0.1

20
D +C F 8
D PC Card ATA CF_A10
A10
A11 9 11 8 9 XCF_REG XCF_REG 8 9 CF_A9 10

VCC
8 A8 B8 12 7 10 A9
XCF_IOWR XCF_IOWR 7 10 Memory Mode CF_XATA/IDE A13 A12 A11 CF_A8 11
7 A7 B7 13 6 11 A8
LDQM/XLWR XCF_WE XCF_WE 6 11 Attribute Memory Area (w. external Wait) 0 0 0 0 CF_A7 12
6 A6 B6 14 5 12 A7
XCF_IORD XCF_IORD 5 12 Attribute Memory Area (w. internal Wait) 0 1 0 0 CF_A6 14
5 A5 B5 15 4 13 13 RA39 A6
XCF_CE2 XCF_CE2 4 Common Memory Area (w. external Wait) 0 0 0 1 CF_A5 15
4 A4 B4 16 3 14 A5
XCF_CS XCF_CS XCF_CE1 XCF_CE1 3 14 10k Common Memory Area (w. internal Wait) 0 1 0 1 CF_A4 16
3 A3 B3 17 2 15 2 15 17 A4
CF_A3
2 A2 B2 18 1 16 1 16 18 A3
CF_A2
A1 B1 19 A2
CF_A1
1 RA38 20 A1
CF_A0

GND
19 DIR 22 A0
XCF_G1
OE
C276 XCF_CE2 XCF_CE2 32
IC45 C277 100p CE2/CE2/CS1
XCF_CE1 XCF_CE1 7

10
D +3 . 3 R265 100p CE1/CE1/CS0
CF_XATA/IDE 1 D SN74LV245APWR C278
100p XCF_OE XCF_OE 9
6 7 22 C279 36 OE/OE/ATASEL
XCF_OEGATE XCF_OE 100p XCF_WE XCF_WE
3 2 C280 34 WE
100p XCF_IORD XCF_IORD
C281 IORD
8

XRD 5 XCF_IOWR XCF_IOWR 35

100p C282 IOWR
XCF_REG XCF_REG 44
C284 100p REG
C283 IC46A CF_R/XB CF_R/XB 37
IC46B 100p C285 RDYBSY/IREQ/INTRQ
0.1 SN74LVC2G02DCTR XCF_DASP XCF_DASP 45
SN74LVC2G02DCTR C286 100p BVD2/SPKR/DASP
XCF_SC XCF_SC 46
100p C287 BVD1/STSCHG/PDIAG
XCF_WAIT XCF_WAIT 42
100p WAIT/WAIT/IORDY
39
4

CSEL
D
D D
IC46C
SN74LVC2G02DCTR CF_D[0..15]
D +3. 3 C288 CF_D15 CF_D15 31
C289 100p D15
XCF_OEGATE CF_D14 CF_D14 30
14

100p C290 D14

CF_D13 CF_D13 29
D +3 . 3 C291 100p D13
28

CompactFlash
CF_D12 CF_D12
VCC

L39 C292 100p C293 D12

CF_D11 CF_D11 27
RA40 C296 100p D11
C295 0.1 CF_D10 CF_D10 49

20
D +C F 100p C297 D10
0.1 47 D CF_D9 CF_D9 48
GND

C298 100p D9
D10 8 9 9 11 8 9 CF_D10 CF_D10 8 9 CF_D8 CF_D8 47

VCC
D +3 . 3 D +3 . 3 A8 B8 100p C299 D8
D9 7 10 8 12 7 10 CF_D9 CF_D9 7 10 CF_D7 CF_D7 6
A7 B7 C300 100p D7
D2 6 11 7 13 6 11 CF_D2 CF_D2 6 11 CF_D6 CF_D6 5
A6 B6 100p C301 D6
D8 5 12 6 14 5 12 CF_D8 CF_D8 5 12 CF_D5 CF_D5 4
7

A5 B5 100p D5
13 RA42 C302
4

IC48C D D1 4 13 5 15 4 13 CF_D1 CF_D1 4 CF_D4 CF_D4 3

A4 B4 100p C303 D4
SN74LV74APWR 2 5 D0 3 14 4 16 3 14 CF_D0 CF_D0 3 14 10k CF_D3 CF_D3 2
PR

D Q A3 B3 C304 100p D3
XCF_CS 5 D7 2 15 3 17 2 15 CF_D7 CF_D7 2 15 CF_D2 CF_D2 23
A2 B2 100p C305 D2
4 3 D15 1 16 2 18 1 16 CF_D15 CF_D15 1 16 CF_D1 CF_D1 22
D +3 . 3 CK R266 A1 B1 C306 100p D1
XRD 6 CF_D0 CF_D0 21
47 RA41 100p D0
6 CF_AB/XBA 1
GND

Q DIR
R

IC50B XCF_G2 19 22 D
14

SN74LV02APWR OE 1 D +3. 3
IC48A
3 SN74LV74APWR XCF_G1 3
1

IC49 R249
1 C307 XBCYST 2
10

2 0.1 D SN74LV245APWR R247 R248 220

D +3 . 3 IC51A 100k 100k R250
SN74LV32APWR 220
D IC50A
SN74LV02APWR IC50E L40 C308 5 XCD225
SN74LV02APWR RA43 0.1 6 CD2
XCF_DETECT
20
7

47 D D +C F 4 XCD126
8 9 9 11 8 9 8 9 CD1
D D14 CF_D14 CF_D14
VCC

7 10 8 A8 B8 12 7 10 7 10 IC51B C309 C310

D6 CF_D6 CF_D6 SN74LV32APWR
6 11 7 A7 B7 13 6 11 6 11 22p 22p 24
D13 CF_D13 CF_D13
D +3 . 3 5 12 6 A6 B6 14 5 12 5 12 33 WP/IOIS16/IOIS16
D5 CF_D5 CF_D5
4 13 5 A5 B5 15 4 13 4 13 RA45 40 VS1
D12 CF_D12 CF_D12
3 14 4 A4 B4 16 3 14 3 14 10k 43 VS2
D4 CF_D4 CF_D4 D
14

D +3. 3 D +3. 3 2 15 3 A3 B3 17 2 15 2 15 INPACK

D11 CF_D11 CF_D11
9 1 16 2 A2 B2 18 1 16 1 16
D3 CF_D3 CF_D3
8 C311 11 A1 B1 D +C F
10

R267 RA44
10 0.1 1313 CF_AB/XBA 1 13
GND

100 DIR VCC

12 9 12 11 XCF_G2 19 22 38
PR

D Q OE VCC
D IC51C
SN74LV32APWR
IC51E
SN74LV32APWR XCF_CS 9 12
10 11 IC50D C328
7

CK IC51D IC52 Q29 D +C F D +C F

LDQM/XLWR 8 SN74LV02APWR D +3 . 3 0.1 C313
10

SN74LV32APWR
D 8 D SN74LV245APWR XP132A1275SR
SLP@M 1 70
IC50C Q GND CNGND2
R

XCF_G1 3 5 L41 10/16 50 60

SN74LV02APWR
2 S3 D1 GND CNGND1

5
IC48B 6 FBM-11-201209-601A20T D
SN74LV74APWR 1 S2 D2 8 D
13

S1 D4 7 2 4 41
XBCYST CF_RESET 'CF_RESET
R251 D3 R252 C312 C314 C315 RESET/RESET/RESET

G1
100k 100k SLP@M 0.1 0.1
CF_XON/OFF 10/16 CF_RESETZ C321 CN9
NIU ICM-MA2H-SS52-R21A D D

1
3
D D R268 R269
IC55 NIU NIU
SN74AHC1G125DCKR D

30 31
 Apr.2003 SPD-S

CIRCUIT DIAGRAM (MAIN 4/8)

fig.main4-c

R63 R64 A
47k 47k R65 C71 R66 R67
WLP@M
47k 100/16 390 220k
C74 C72 13 12
WLP@M R68 C75
100/16 10p 2 C329 C73 11
220 - WLP@M C76
1 100p 100/16 10p 2 C330 A
- SW2A R69 WLP@M
3 1 100p 100/16
+ SSSF141300 470
3
IC16A + IN_L
R70
M5218AFP IC17A
4.7k R71 R72
DA49
INPUT M5218AFP
NIU 10k

1
VR DA3 43 42

22
A LINE -8.32dBu (+1.68dB)
D +3. 3 DAP202U
DAN202U 41
MIC -8.31dBu (+41.69dB)

2
3 3 LINE/MIC -2.30dBu (+6.02dB) 23 VR1A A
DA48 1 A +9 SW2D
RK09K12A@ SSSF141300
DAN202U D 13 3 3
R73 R74 10kAx2
A A
47k 47k R75 C77 R76 R77 A -9
1

WLP@M
47k 390 220k

12
C80 100/16 DA4
C78 33 32

1
WLP@M R78 C81 DAP202U
100/16 10p 6 C331 C79 31
220 - WLP@M C82
7 100p 100/16 10p 6 C332 A
- SW2C R79 WLP@M
5 7 100p 100/16
+ SSSF141300 470
5
IC16B + IN_R
R80
M5218AFP IC17B C333
4.7k R81 R82

20

10
VR1B M5218AFP
0.1 NIU 10k
D +3. 3 A
RK09K12A@ 23 22
10kAx2
21
D A A A
R263 R264 SW2E SW2B

20

10
SSSF141300 SSSF141300
10 10
A
+4.89dBu (+6.02dB)
A R83 R84
C83 C84 R85 C85 C86 R86 R87 10k 22k
0.1 NIU 0.1 10k 10k
WLP@M WLP@M R88
C87 C88 RCT20@J
100/16 100/16 C89 C90 WLP@M
D D D D C334 C335 2 100p NIU 47 (1/2W)
C91 WLP@M WLP@M -
5

WLP@M A 100p 2
- 100/16 100/16 100p 1
PHONES_L
R90 R91 1 3
100/16
VA
VD

4.7k 8.2k +

3
1 15 3
RIN LOUT + R260 1 R92 R93
ADC -0.64dBu typ. DAC -1.13dBu typ. IC19A PHONES 1k 4.7k
IC18A
M5216FP 100k
D +3. 3 CODEC R94 C92
M5218AFP
VR Q2
2 16 27k 1000p RN1441

22
A A

2
LIN ROUT
PHONES +15dBu Max A
9 8 VR2A 23
SDTI SDTI SDTO C93 1 (+10.10dB)
A A
10 14 1000p RK09K12A@ 13
LRCK LRCK VCOM 10kAx2
11 A A R95 R96
MCK MCLK R97 R98
12 10k 22k
BCK BCLK 10k 10k
7 R99

12
6 DEM1 C94 C97
WLP@M RCT20@J
VSS

13 DEMO C95 C336 C98 C99 C337 6 100p

WLP@M WLP@M - NIU 47 (1/2W)
PDN 0.1 C101
WLP@M A 100p 6
- 100/16 100/16 100p 7
PHONES_R
R101 R102 7 5
100/16 4.7k 8.2k +

3
IC20 5
3

+ R261
AK4552VT 1 R103 IC18B R104
D D C100 IC19B 1k 4.7k M5216FP 100k
A A M5218AFP VR2B
NIU R105 C102 Q3
27k 1000p RK09K12A@ RN1441 A A

2
SDTO 10kAx2
A
C96
GA&DSP Section A A C103

10

20
WLP@M
2.2/50 1000p
A

ADP V C104 R106 R107

DA7 WLP@M
100/16 470 470
3

DA204U
SEND_L RETURN_L OUT_L
1 2

3
C105 R108 1 Q4
WLP@M 10k RN1441
R109 R110 R111
470 27k 27k 100/16
CPU Section A

2
2

A A
R113
3

C106 1 Q5
XPDN 10k 2SA1037KR
1 Q6 SLP@M
AMUTE 2SC3052 R112
10/16 10k
R114
3

27k
2

R115 C107 R116 R117

A A A WLP@M
27k 100/16 470 470
SEND_R RETURN_R OUT_R

3
A -9
R118 1 Q7
CN Section 10k RN1441 Jack Section

2
A A
A +9 A +9 A +9 A +9 A +9 MUTE

C108 C109 C110 C111 C112

8

WLP@M 0.1 0.1 0.1 0.1

100/16 - - - -

+ + + +
A A A A A D C348 A D C349 A
C113 IC17C C114 IC16C C115 IC19C C116 IC18C C117 NIU NIU
M5218AFP M5218AFP M5218AFP
WLP@M 0.1 0.1 0.1 M5216FP 0.1
4

100/16

A -9 A -9 A -9 A -9 A -9

32 33
 Apr.2003 SPD-S

CIRCUIT DIAGRAM (MAIN 5/8)

fig.main5-c

'RIM[1..9]

'PAD[4..9] DA8
DA204U RA25 C347 D +3. 3
+
'CTRLVR
2 1 R119 EXB2HVJV@0.1 D 3. 3

2
12k 100k
R120 R121 R122 1 RING/XRIM
CN Section 68k 390k NIU D +3. 3 D D +3. 3

3
Q8
1 2 ANI0
RT1P141C

10
11
12
13
14
15
16

3
A +9 A +9

9
R129 C120 R130 C118 DA9 C119 R123 C346
NIU 0.22 120k 10p 0.47 NIU 0.1 R124 R125 R126 R127 R128

3
'PAD4 2 DA204U 100k 5.6k 5.6k 270k 100k
- DA11 RA49
1 D D D C122 C123
DAP202U

4
C124 R131 C121 3 10k D 0.1 0.1

8
7
6
5
4
3
2
1
+ D +3. 3 NIU
1000p 100k 0.01 IC21A 'RIM1 1 8
- -
BA10324AF 3 3 'RIM2 2 7 1 16 13 12 RIM1
D D D DA10 'RIM3 3 6 2 15 DA14 + +
DA12 DAN202U D 4 5 3 14 IC23F IC21E D IC22E D
DAP202U

2
DA204U 'RIM4 1 16 4 13 C125 SN74LV14APWR BA10324AF C126 BA10324AF C127
2 1 R132 'RIM5 2 15 5 12 0.047 D +3 . 3 NIU 0.1 0.1

11

11
2

1
12k 'RIM6 3 14 6 11 3 3
R133 R134 R135 'RIM7 4 13 7 10 DA13
68k 390k NIU 'RIM8 5 12 8 9 D DAN202U D A -9 A -9

3
1 2 ANI1 'RIM9 6 11 NIU
7 10

1
R141 C130 R142 C128 DA15 C129 R138 8 9 11 10 RIM2
NIU 0.22 120k 10p 0.47 NIU RING A +9 A +9 A +9

3
'PAD5 6 DA204U 'P1 IC23E
-
7 D D 'P2 RA26 C132 SN74LV14APWR
C133 R143 C131 5 EXB2HVJV@ 0.047 C134 C135 C136
+ RA48

8
1000p 100k 0.01 IC21B 1k 0.1 0.1 WLP@M
BA10324AF 10k R136
- - 100/16
D D D 1k D
DA16 R137
+ +
DA204U 100k D D D
2 1 R144 R139 9 8 RIM3 IC24C C137 IC25C C138 C139
M5218AFP M5218AFP
12k 1k 0.1 0.1 WLP@M

4
DA19
R145 R146 R147 R140 IC23D 100/16
DAP202U

2
68k 390k NIU 1k C140 SN74LV14APWR

3
1 2 ANI2 0.047 D +3 . 3 NIU A -9 A -9 A -9
3 3
R149 C143 R150 C141 DA17 C142 R148 DA18
NIU 0.22 120k 10p 0.47 NIU D DAN202U D

3
'PAD6 9 DA204U
- DA21 NIU
8 D D

1
DAP202U

2
C145 R151 C144 10 5 6 RIM4
+ D +3. 3 NIU
1000p 100k 0.01 IC21C 3 4
BA10324AF 3 3 IC23C
D D D DA20 C146 SN74LV14APWR IC23B
DA22 DAN202U D 0.047 D SN74LV14APWR
DA204U
2 1 R152

1
12k D 1 2
R153 R154 R155
68k 390k NIU IC23A
3

1 2 ANI3 13 12 RIM5 D SN74LV14APWR

DA25
R157 C150 R158 C147 DA23 C148 R156 IC26F
DAP202U D +3 . 3 D +3. 3

2
NIU 0.22 120k 10p 0.47 NIU C149 SN74LV14APWR
3

'PAD7 13 DA204U 0.047 D +3 . 3 NIU

-
14 3 3

14

14
D D
C152 R159 C151 12 DA24
+
1000p 100k 0.01 IC21D D DAN202U D C153 C154
BA10324AF NIU 0.1 0.1
D D D IC26G IC23G

1
DA26 11 10 RIM6 SN74LV14APWR SN74LV14APWR

7
DA204U
2 1 R160 IC26E D D
12k C155 SN74LV14APWR
R161 R162 R163 0.047
68k 390k NIU
3

1 2 ANI4
D
R165 C158 R166 C156 DA27 C157 R164
NIU 0.22 120k 10p 0.47 NIU
3

'PAD8 2 DA204U 9 8 RIM7

- DA29
1 D D DA31
DAP202U
1

C160 R167 C159 3 IC26D

+ D +3. 3 NIU DAP202U

2
1000p 100k 0.01 C161 SN74LV14APWR
IC25A 3 3 0.047 D +3 . 3 NIU
M5218AFP
D D D DA28 3 3
DA32 DAN202U D DA30
DA204U D DAN202U D
2 1 R168 NIU
2

12k

1
R169 R170 R171 5 6 RIM8
68k 390k NIU
3

1 2 ANI5 IC26C
C162 SN74LV14APWR
R173 C165 R174 C163 DA33 C164 R172 0.047
NIU 0.22 120k 10p 0.47 NIU
3

'PAD9 6 DA204U
-
7 D D D
C167 R175 C166 5
+
1000p 100k 0.01
IC25B 3 4 RIM9
M5218AFP
D D D DA36
DA34 IC26B
IC24A DAP202U

2
DA204U C168 SN74LV14APWR
A +9 M5218AFP D +3 . 3 NIU
2 1 R176 0.047
12k IC27 C169 R179 3 3
R177 R178 R180 CD4053BCSJ 0.1 2 100 DA35
16

-
68k 390k NIU D 1 ANI6 D DAN202U D
3

1 2 5 4 3 NIU
VDD

0Z ZCOM +
PEDAL 3 R182

1
'P1 1Z DA39
1

R183 C172 R184 C170 C171 R181 2 15 C338 NIU 2 1 2 RIM10

'P2 DA37 0Y YCOM
NIU 0.22 120k 10p 0.47 NIU CTRLVR 1 100p D +3. 3 DAP202U
3

DA204U 1Y D +3 . 3

3
9 12 14 3 3 IC26A
TIP - 0X XCOM IC24B
8 D D 13 DA38 C174 2 1 SN74LV14APWR
1X M5218AFP
C175 R185 C173 10 DAN202U D 1000p
RING +
NIU 100k 0.01 IC22C 9 D
C DA40
BA10324AF 10 6
2

'PEDAL B - DA204U
D D D 11 7 ANI7 D
VSS

VEE

6 A 5
DA41 +
Jack Section INH R188 R186
DA204U
2 1 R187 C339 NIU 100 P1
12k 100p
8

R189 R190 R191 C176

DA44

2
68k 390k NIU D D NIU C177
3

1 2 1000p D +3 . 3 DAP202U
R192 3 3
R195 C180 R196 C178 DA42 C179 R193 0 DA43
NIU 0.22 120k 10p 0.47 NIU R194 D D DAN202U D
3

13 DA204U NIU
-
14 D D

1
C182 R197 C181 12 P2
+
NIU 100k 0.01 IC22D A -9 CPU Section
RING BA10324AF A +9
D D D C183
RING/XRIM
1000p
R198
RIM[1..10]
10k
D P[1..2]

ANI[0..7]
3

D +3. 3 C340 1
MXPAD
100p Q10
D +3 . 3
R199 2 1 RT1N141C
2

100k 6 D
R201 -
D 7
1k 5
3

+
IC22B
C184 DA45 BA10324AF
0.1 DA204U
C341
D 100p

2
R202 -
1
100 3
'CTRLVR +
IC22A
C185 BA10324AF
0.1

34 35
 Apr.2003 SPD-S

CIRCUIT DIAGRAM (MAIN 6/8)

fig.main6-c

LINE IN
L(MONO)
L2
2
MIDI IN/OUT DA46
IN_L
4
1
DAN202U C188 D +5 C186
2 1 D +5 0.1 1000p L3 JK2
JK1 HTJ-064-10I
NIU
HDC-052A-12 R203
R204

6
23 L4 D 2.2k A A A

3
25 120 1
3
5

22 5 LINE -10dBu
OUT

MIDI_IN
2
IN

24 3
MIC -50dBu
4

21 IC28
1

29 R205 PC410KT
20
L5
100 LINE IN

4
13 R206
15
L6
220
D
L7
R
3
5

12 2
OUT
IN

D +5 IN_R
2

14 Q11 4
4

11 1
1

R207 RT1P141C R208

2
19 L8 C189
10 220 1 2 1 0 1000p L9 JK3
XRESET HTJ-064-10I
NIU
C191
IC29A 100p A A A
30
40
50
60

3
SN74LS05NSR
D +5 D
D

R209
10k

4 3 12 13 L10
PHONES
MIDI_OUT(SO0)
2
PHONES_L
3
IC29B IC29F CPU Section 1
SN74LS05NSR SN74LS05NSR
C192
D +5 1000p L11 JK4
HTJ-064-10D
NIU
IC29E 10 11
14

SN74LS05NSR
A A A
IC29C 6 5 C194
SN74LS05NSR
0.1 PHONES +15dBu
IC29D 8 9
SN74LS05NSR
7

C343
D D IC29G
SN74LS05NSR
0.1

L12
PHONES_R A F
TRIGGER INPUT
L13 C195 C344
L14 1000p 0.1
2
TIP
3
RING
1 A A F

JK7 L15 C196 C197

HTJ-064-10D NIU NIU NIU C198
D +3. 3 0.1 D +3. 3
OUTPUT
R210
D D D
L(MONO)
2

D 4.7k
Q12 1 L16
3

2
EXP PEDAL RT1P141C 1
Q13 OUT_L
4
L18 RT1N141C 1
3

L19 C199
2 D 1000p L17 JK5
2

'PEDAL HTJ-064-10I
3 NIU
1
A A A
JK8 L20 C201 C202
HTJ-064-10D NIU NIU NIU LINE +4dBu

D D D
OUTPUT
R
FOOT SW L21
2
OUT_R
5 L23 4
4 L24 1
2 C203
'P1 L22 JK6
3 Audio Section 1000p
'P2 HTJ-064-10I
7 NIU
8
1 Trigger Section A A A
C205 C206
JK9 L25 NIU NIU
HTJ-064-04A NIU

D D D

36 37
 Apr.2003 SPD-S

CIRCUIT DIAGRAM (MAIN 7/8)

fig.main7-c

D +5 RA27 5SS3 40
100 40
4 5SS2 39
SS[0..3] LCD[0..7] 39
6 4 5 5SS3 5SS1 38
5 3 6 37 38
SS3 5SS2 LCD7 5SS0
2 7 36 37
5SS1 LCD6 5SD4
1 8 35 36
IC53B 5SS0 LCD5 5SD3
SN74AHCT08PWR 34 35
LCD4 5SD2
1 33 34
LCD3 5SD1
3 32 33
LCD2 5SD0
2 D +5 31 32
SS2 LCD1 'LS0
30 31
LCD0 'LS1
29 30
IC53A LE 'LS2

14
LE 29
SN74AHCT08PWR D D R/XW 'LS3 28
R/XW 28
9 D D RS 'LDG 27
RS 27
8 C207 C208 C211 'LD0 26
26
SS1 10 1000p 1000p 0.1 'LD1 25
C209 C210 GA&DSP Section 24 25
'LD2
1000p 1000p 23 24
IC53C IC53E 'LD3
SN74AHCT08PWR SN74AHCT08PWR 22 23
'LD4

7
12 21 22
'LD5 PANEL BOARD
11 20 21
D D D D D D D 'LD6
20
SS0 13 D D D D D LCDCONT 19
C212 C213 C214 C215 C216 C217 18 19
RS

FBM-11-201209-601A20T

FBM-11-201209-601A20T
C223 D +5 100p NIU 220p 220p 220p 220p 17 18
IC53D R/XW
SN74AHCT08PWR D +3. 3 NIU C218 C219 C220 C221 C222 16 17
LE
100p 220p 220p 220p 220p 15 16
LCD0
15

5
6
7
8
LCD1 14
20

R211 RA28 D +5 D +3. 3 13 14

D LCD2
9 11 10k D +3. 3 12 13
10k LCD3
VCC

8 A8 B8 12 R212 11 12
SD[0..4] LCD4
7 A7 B7 13 100 L48 10 11
LCD5

4
3
2
1
A6 B6 10

L35

L26
SD4 6 14 5SD4 LCD6 9
5 A5 B5 15 4 5 A +9 8 9
SD3 5SD3 LCD7
4 A4 B4 16 3 6 12 7 8
SD2 5SD2
3 A3 B3 17 2 7 11 12 6 7
SD1 5SD1 RETURN_L
2 A2 B2 18 1 8 10 11 5 6
SD0 5SD0
A1 B1 9 10 4 5
RETURN_R 9 4
19 8 3
GND

1 OE RA29 7 8 2 3
DIR 100 SEND_L
6 7 PANEL BOARD 1 2
5 6 1
SEND_R 5
IC31 4 C253 C225 D
10

SN74LV245APWR Audio Section 3 4 C252 0.1 C224 0.1 CN5

D D D D 52045-4045
NIU 2 3
D D SLP@M SLP@M
C226 C227 C228 1 2
1 10/16 10/16
1000p 1000p 1000p
C229 C230 A -9 A D
D +5 'CTRLVR CN10
1000p 1000p
12FE-BT-VK-N
Q14 C342
'PAD[4..9]
3

2SC3052 D 0.1
1 'PAD6 4
'LCDCONT L27 4
'PAD5 3
2 3 PIEZO ASSY
LCDCONT 'PAD4
CPU Section R213 1 2
(PAD4-6)
2

3.3k R214 C231 1

100 1000p D
CN8
04FE-BT-VK-N
D D D
'PAD9 4
C232 3 4
'PAD8
D +3. 3 0.1 2 3 PIEZO ASSY
'PAD7
1 2
L28 1 (PAD7-9)
XLS[0..3] L29
2

D D
XLS0 1 Q15 L30 CN7
DTB113ZK L31 04FE-BT-VK-N
'LS0 1
'RIM[1..9] 1
'LS1 2
3

3 2
'LS2 'RIM3
3
2

'LS3 4
XLS1 1 Q16 'RIM2 5 4 RIM SENSOR
DTB113ZK 6 5 (PAD1-3)
7 6
'RIM1
8 7
3

8
2

D
XLS2 1 Q17 D D CN11
DTB113ZK SLP8R-5
D D
C233 C234 'RIM6 1
1000p 1000p Trigger Section 2 1
3

C235 C236 3 2
'RIM5
3
2

1000p 1000p 4
1 Q18 5 4
XLS3 'RIM4
DTB113ZK 6 5
7 6
8 7
3

9 8
'RIM9 RIM SENSOR
10 9
'LDG
11 10 (PAD4-9)
'LD0 'RIM8
12 11
'LD1
13 12
'LD2 'RIM7
14 13
'LD3
15 14
LD[0..6] 'LD4
16 15
'LD5
16
LD6 'LD6
LD5 D
LD4 R215 56 CN12
R216 27 SLP16R-5
LD3
LD2 R218 27
LD1 R217 27
R219 39
LD0 R220 39
LDG LDG R221 39
3

R222 39
1 1 1 1 1 1 1 1
2

D D D D D D D D

Q19 Q20 Q21 Q22 Q23 Q24 Q25 Q26

RT1N141C RT1N141C RT1N141C RT1N141C RT1N141C RT1N141C RT1N141C RT1N141C

38 39
 Apr.2003 SPD-S

CIRCUIT DIAGRAM (MAIN 8/8)

fig.main8-c

DA47

1
DAN202U
NIU
3
ACI,ACB Adaptor ADP V
(9V/1000mA)

2
L32 SW3A D1 IC32 D +5
SDKLA1-B
EXCELDR35V SS5819 NJM78L05UA
2 2 1 1 2 3 1 D+5V
1 IN OUT

COM
3
JK10
HTJ-020-05A C237 C240
C241 WLP@M C238 C239 WLP@M

2
0.1 220/16 0.1 0.1 220/16

A D
SW3B
SDKLA1-B
10

20

R223
100
R224

1
ADP V
270 3 IC34
Q27 L33 L43 D +3. 3 D +3. 3 S-80927CLMC-G6X-T2 R243
L42 2SA1706T
LA-DR080-150
15uH (7.8*6.4)
LA-DR080-150
15uH (7.8*6.4)
D+3.3V 'A NIU 'B
LA-DR080-150 8 1 'C 999 2 1

32
CD CS VDD OUT XRESET
15uH (7.8*6.4) D2

999

999
7 C318 R227 C242 C244 3 4

CD
IPK SB07-03C VSS NC
2 WLP@M RCT03@F WLP@M 0.1
C317 ES 'D 999
220/16 3.3k 220/16
WLP@M 6 D D D

5
VCC 5 +
220/16 D
VIN- R228 C245 C255
R226
RCT25@J C323 0.1 + NIU
RCT03@F
D 0.18 4 3 NIU 2k R242
GND CT NIU
C246

5
D IC33 D D D
NJM2360AM 150p 999 1
A 4 999
2 B
IC36 +

EVQ11A05R
1
TC7S08F 999
NIU C

3
Q28

SW4
999

NIU
ADP V 2SC3265Y A +9 D
3 2
A+9V

2
*Only under development
R229
1k
1

C247 C248
WLP@M WLP@M
220/16 220/16

A
ADP V R231
2
R232
L44 NIU
R233
LA-DR080-331 NIU
330uH (8*5) L34
LA-DR080-331
330uH (8*5)
C319 8 1 3 1
CD CS
WLP@M D3
220/16 7
IPK SB07-03C
2 R236
ES 3.3k
A 6 A
VCC 5
VIN-

4 3 R237
GND CT 22k A-9V
IC35
NJM2360AM
L45
A LA-DR080-331
330uH (8*5)

C250 C251 C320 C249 R262

150p NIU WLP@M WLP@M 1k
220/16 220/16
A A A
A -9

40 41
 Apr.2003 SPD-S

CIRCUIT BOARD (PANEL)

fig.panel-comp-ptn

View from components side

42 43
 Apr.2003 SPD-S

CIRCUIT BOARD (PANEL)

fig.panel-foil-ptn

View from foil side

44 45
 Apr.2003 SPD-S

CIRCUIT DIAGRAM (PANEL)

fig.panel-c

1 '5SS3 '5SD4
1 2 '5SS2 '5SD3
2 3 '5SS1 '5SD2
3 4 '5SS0 '5SD1
4 5 '5SD4 '5SD0 'LCD7
5 6 '5SD3 '5SS3 'LCD6
6 7 '5SD2 'LCD5
7 8 '5SD1 WAVE START / SAMPLING RESAMPLE EXIT 'LCD4
8 9 '5SD0 'LCD3
9 10 STOP
''LS0 'LCD2
10 11 ''LS1 SW1A SW2A SW3A SW4A SW5A 'LCD1
11 12 11 12 11 12 11 12 11 12 11 12
''LS2 'LCD0
12 13 21 22 21 22 21 22 21 22 21 22
''LS3 'LE
13 14 ''LDG 'R/XW
14 15 ''LD0 '5SS2 'RS
15

1
16 ''LD1 DA1 DA2 DA3 DA4 DA5 'LCDCONT
16 17 ''LD2
17 18 DAP202U 3 DAP202U 3 DAP202U 3 DAP202U 3 DAP202U 3
''LD3
18 19 ''LD4 PATCH EFFECTS SETUP EDIT <
to MAIN BOARD 19
20
20
21
''LD5 D +5(P)
''LD6
21 22 11 12 11 12 11 12 11 12 11 12
'LCDCONT

2
22 23 21 22 21 22 21 22 21 22 21 22
'RS
23 24 C1
'R/XW SW6A SW7A SW8A SW9A SW10A
24 25 0.1
'LE '5SS1
25 26 'LCD0
26 27 'LCD1 CARD

10
11
12
13
14
27 ALL SND FUNC SHIFT >

1
2
3
4
5
6
7
8
9
28 'LCD2
28 OFF SW14A CN2
29 'LCD3 D(P)

10
11
12
13
14
1
2
3
4
5
6
7
8
9
29 30 11 12 12 11 52043-1410
'LCD4
30 31 1 2 21 22 1 2 1 2 22 21
'LCD5
31 32 'LCD6 SW15 SW16A SW12 SW13
32 33 D + 5(P) D + 3.3(P)
4 1 1
'LCD7 '5SS0
33 34
34 DA6 DA7 DA8 DA9 DA10

2
35
35 36 DAP202U DAP202U DAP202U DAP202U DAP202U
36 37 C3 3 3 3 3 3
37 38 NIU
PHRASE - /INC + /DEC ENTER
38 39 MAKER 16x1 Character LCD
39 40 11 12 11 12 11 12 12 11
40 21 22 21 22 21 22 22 21

1
RCM2122M-A
D(P) SW17A SW18A
CN1 C2 SW11A SW19A LCD1
52044-4045
RV2-V@M-R
PANEL BOARD 10/16
*SMD
''LS0 D + 3.3(P)

2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1
LED1 LED2 LED3 LED4 LED5 LED6 LED15 LED8
19-21SDRC/A2 19-21SDRC/A2 19-21SDRC/A2 19-21SDRC/A2 19-21UYOC/A2 19-21UYOC/A2 19-21UYOC/A2 19-21SYGC/E1
D + 3.3(V)
VOLUME BOARD TR2 TR1 FS1 FS2 PATCH CARD < START /
A + 9(V) *SMD ''LS1 STOP
C4
CN3 RV2-V@M-R
100/16 2 1 2 1 2 1 2 1 2 1 2 1 2 1
12FE-ST-VK-N
1 LED9 LED10 LED11 LED19 LED13 LED35 LED21
1 19-21SDRC/A2 19-21SDRC/A2 19-21SDRC/A2 19-21SDRC/A2 19-21UYOC/A2 19-21UYOC/A2 19-21UYOC/A2
2 'RETURN_L
2 3
3 4
PAD9 PAD8 PAD7 RESAMPLE WAVE EDIT > D + 3.3(P) D + 3.3(P)
'RETURN_R
4 5 LCD
''LS2
5 6 BACKLIGHT
'SEND_L
to MAIN BOARD 6
7
7 2 1 2 1 2 1 2 1 2 1 2 1 2 1 MODULE
8 'SEND_R R4 R5 R1 R2
8 9 LED16 LED17 LED18 LED12 LED20 LED14 LED33 56 56 *IF=20mA 56 56
9 19-21SDRC/A2 19-21SDRC/A2 19-21SDRC/A2 19-21SDRC/A2 19-21UYOC/A2 19-21UYOC/A2 19-21UYOC/A2
10 ''CTRLVR @VF=2.2V
10 11
11 12
PAD6 PAD5 PAD4 SAMPLING EFFECTS SETUP ENTER
12
''LS3

D(V) A(V) 2 1 2 1 2 1 2 1 2 1
LED28 LED29 LED30 LED31 LED32

6
4

3
1
C5
19-21SDRC/A2 19-21SDRC/A2 19-21SDRC/A2 19-21SDRC/A2 19-21SDRC/A2
RV2-V@M-R LED34B LED34A
100/16 PAD3 PAD2 PAD1 MARK PHRASE BLB-6519I-YG BLB-6519I-YG
A - 9(V) *SMD ''LD6
''LD5 MAKER

2
''LD4 R15 D(P) D(P)
A(V) R9 R10 ''LD3 RPC05T@J
NIU NIU ''LD2 NIU
''LD1
'SEND_L C11 C6 ''LD0
47p 6 NIU ''LDG
23

-
VR3B 7 'RETURN_L
22 5
RV112B-40E1@ +
10 VR3C
SPD-S9-10k R11 IC1B
M5218AFP RV112B-40E1@
4.7k 20 SPD-S9-10k
21

A(V) A(V) A(V)

VOLUME D + 3.3(V)
LINE +4.89dBu Max
3

(0dB) A + 9(V) ''CTRLVR 2 VR4A

A(V) R12 R13 EVUF2J@ C10
NIU NIU PCKS1-10kB NIU
C8
1
8

'SEND_R C12 C7 0.1

47p 2 NIU D(V)
13

- -
1 'RETURN_R
VR3A
12 3 CONTROL
RV112B-40E1@ + +
A(V) 10
SPD-S9-10k R14 IC1A IC1C C9 VR4B
M5218AFP M5218AFP
4.7k 0.1 20 EVUF2J@
11

PCKS1-10kB
A(V) A(V)
A - 9(V) D(V)

46 47
Apr.2003

48