FPGA Based 32 Bit ALU for Automatic Antenna
Control Unit
Syed Muhammad Adnan
Department of Electrical Engineering,
Pakistan Navy Engineering College,
sm_adnan21@hotmail.com
AbstractArithmetic logical unit is a critical part of all
microprocessor based equipments as it performs all the
primary functions. This paper focuses the implementation
of 32 bit ALU on FPGA for the Antenna Control Unit
processor. Antenna control unit is a subsystem used in
telecommunication to automatically track, monitor and
control the RF signals. Our ALU is implemented by using
modular approach i.e. Control Unit, Logical Unit,
Arithmetic Unit, Relational Operations Unit. Control Unit
is a state machine that issues commands for all the
operations. Arithmetic Unit performs all mathematical
functions and Logical Unit performs binary logic
operations on the 16 bit operands. The post place route
results on Virtex-6 uses are 85 Slices, with Fmax of
703.7MHz while using Virtex-5 it uses 97 Slices with
Fmax of 553.08MHz.
KeywordsArithmetic Logic Unit, Logical Unit, FPGA,
Efficient implementation.
I. INTRODUCTION
ALU is the most critical part of Processor as it is
responsible for all Arithmetic, Logical and Relational
operations within processor. It includes all the major
arithmetic operations like addition, multiplication and
division, logical operations include AND, XOR, NOT,
OR, NAND, NOR, XNOR and also performs Relational
operations like Compare, Shift and Rotate.
This paper is focusing the implementation of ALU on
FPGA platform. FPGA is becoming a standard device
for evaluating and cost effective implementation of the
project due to low time of processing, embedded
resources and reconfigurable. Implementation is done
using modular approach without using any dedicated
resources of FPGA for simplicity and fair performance
evaluation. The software platform used is Xilinx ISE
13.1 and the devices used are both Spartan and Virtex.
The rest of paper is summarized as in the next section
related work is discussed while section-III covers ALU
working. In section-IV design review is presented
followed by section-V where designed architecture is
discussed. In last section implementation results are
given.
II. RELATED WORK
Previous work on FPGA based ALU implementation
mostly consists of three types of data path i.e. 4 bits, 8
bits or 32 bits. All the designed data paths target either 4
bits instruction set or 3 bits instruction set approach.
This paper is concerned with both approaches of both
instruction sets. In the subsequent paragraphs literature
related to this work is presented.
In [6] Ateeq A. Khan implemented 4 bit ALU on FPGA
for high processing speed and low power. The design is
coded and simulated in VHDL. Instruction set is defined
to perform 15 different operations including Addition,
Increment, Subtraction, Complement and Logic
Functions. Design is completely carried out using
combinational logic only.
In [7] Shikha Khurana and Kanika Kaur also
implemented 4 bit ALU on Spartan 3E platform without
using any dedicated FPGA resource. The design has
instruction set to perform 16 operations which are
mainly arithmetic and logical operations.
In [8] Geetanjali and Nishant Tripathi implemented
32bit ALU without using any dedicated FPGA
resources. The instruction set performs 16 operations
including both logical and arithmetic operations.
Simulation is carried out using Modelsim5.4a to verify
all operations.
In [9] Suchita Kamble and N. N. Mhala implemented 8
bit ALU on Spartan device for network interface card. It
is coded and simulated using Xilinx Synthesis tool ISE
13.1. The maximum propagation delay is 13.588ns and
power dissipation is 38mW.
In [10] S.Kaliamurthy and U.Sowmmiya designed ALU
for both 8 bits and 16 bits data path. The instruction set
is of 5 bits to perform 21 operations. The ALU is coded
on Quartus-II for implementation on Spartan 3 device.
A status flag is also designed with the features such as
indication of overflow, carry, borrow and zero value
III. ALU WORKING
Arithmetic Logical Unit is designed to perform all
arithmetic, logical and relation operations on data path
of 32 bits. The top level diagram of our design is
shown in fig.1. IN1, IN2 are two 32bits inputs, OPC is
the operation code that is used to control the operation.
OPC is of 5bits wide to cover both 4bits and 3 bits
instruction sets. OUT1 is 64 bits wide output register
that holds the result of both arithmetic and logical
operations. It also gives the result of Shift, Rotate, B. Control Unit
Increment, and Decrement on IN1 and IN2. Control Unit (CU) in the ALU is used to decode
Relational operation output is given by three different operation code and generate the command signals for
outputs which are IN1 Equal to IN2 (EE), IN1Greater respective operation.CU is implemented by using Finite
than IN2 (GT) and IN1 Less than IN2 (LT). All three State Machine (FSM), which is designed using one hot
outputs are single bit. coding with maximum of 32 states. Instruction table of
23 operations is given in table I. CU receives operation
codes (OPC) through the I/O interface. Received OPC
CLK
is then decoded by FSM to generate respective enable
CONTROL UNIT and command signals for AU, LU and RU. If the OPC
EN CLK
INPUTS EN
received does not belong to any code then FSM returns
EN EN EN to idle state and wait for nest OPC. Architectural block
CLK & & &
CMD CMD CMD OUTPUT diagram with respective signals is shown in fig 3.
INPUT FIFO
FIFO
ARITHMETIC LOGICAL RELATIONAL
UNIT UNIT UNIT

OPC CLK
MUX

Figure 1. Top Level ALU Block Diagram

FSM
Top level diagram of LAU is subdivided into four parts
which are shown in fig.2. In fig.2 the main part is
Control unit which is in supervisory position and takes
all actions. Rests of three parts are functional modules
which are Arithmetic Unit, Logical Unit and Relational
Unit. Detail design review is presented in next section. EN_AU EN_LU EN_RU CM_CODE

IV.
DESIGN REVIEW
Design of our ALU is based on modular approach. All
the command and supervisory actions are taken by
Control Unit (CU). CU generates signals for Arithmetic
Unit (AU), Logical Unit (LU) and Relational Unit
(RU). All these units are implemented as separate
modules. The design also uses Input / Output FIFOs for
implementation due to limitation of I/O pins of the
device. Fig. 2 shows the block diagram with all three
modules. In the subsequent paragraphs all these
modules are explained.
CONTROL UNIT
Figure 3. Control Unit Architecture
C. Arithmetic Unit
Arithmetic Unit (AU) performs addition of two
numbers, subtraction of two numbers, multiplication of
two numbers and squaring of the number. It also
performs increment and decrement of both numbers.
Thus there are total 9 functions performed by AU.
Architectural block diagram of AU with interfaces is
shown in fig 4.
AU is designed using only combinational and LUTs
logic without using any dedicated resources. Slice
utilization by AU is shown in table II.

IN1 IN2 EN_AU CM_CODE

LOGICAL ARITHMETIC RELATIONAL

UNIT UNIT UNIT
IN1+IN2 IN1*IN2 IN1+1 IN2+1 IN2*IN2

Figure 2. ALU Block Diagram

IN1-IN2 IN1-1 IN2-1 IN1*IN1

A. Input/Output FIFOs
OUT1
To realize design easily in limited I/O pins, Input/
Output FIFOs are developed. These FIFOs are
developed using Block Memory by core generator tool.
Figure 4. Arithmetic Unit Architecture
Instruction Operation Function
Code Arithmetic Slices # Registers Fmax %Utilization
Unit LUTs MHz
Arithmetic Unit Utilization
Virtex-5 204 3 645.16 0.2%
5d0 IN1+IN2 Add two inputs
Virtex-6 194 4 671.1 0.13%
5d1 IN1-IN2 Subtract two inputs
TABLE II. Arithmetic Unit Slice utilization
5d2 IN1*IN2 Multiply two inputs

5d3 IN1+1 Increment input 1

D. Logical Unit
5d4 IN2+1 Increment input 2
Logical Unit (LU) performs AND, OR, XOR, XNOR,
5d5 IN1-1 decrement input 1 NAND, NOR operations on IN1 & IN2. Logical NOT
operation is performed on both inputs separately. Shift
5d6 IN2-1 decrement input 2 Right, Shift Left and Rotate operations are also
performed by LU on both inputs IN1 and IN2. Thus
5d7 IN1*IN1 Square input 1 there are total 12 logical operations are executed in
Logical unit. Control unit generate enable and
5d8 IN2*IN2 Square input 2 command signal for LU to perform any one of these
fourteen operations on inputs. The architectural block
Logical Unit diagram is shown in fig 5. Slice utilization of Logical
unit is given in table III.
5d9 IN1& IN2 AND two inputs

5d10 ~ (IN1& NAND two inputs

Logical Slices # Registers Fmax %Utilization
IN2)
Unit LUTs MHz
Utilization
5d11 IN1||IN2 OR two inputs
Virtex-5 66 0 645.16 0.08%
5d12 ~ NOR two inputs Virtex-6 66 0 668.8 0.02%
(IN1||IN2)

5d13 IN1^IN2 XOR two inputs TABLE III. Logical Unit Slice utilization

5d14 ~ XNOR two inputs

(IN1^IN2) E. Relational Unit
5d15 ~ IN1 NOT input 1 Relational Unit (RU) executes comparison operations
of greater than (GT), less than (LT) and equal to (EE)
5d16 ~ IN2 NOT input 2 on IN1 and IN2. Relational unit is developed using
LUTs only. Slice utilization is of relational unit is
5d17 IN1>> SHIFT right input 1 given in table IV. Internal architecture of relational unit
is given in fig 6. Enable signal from CU FSM activate
5d18 IN1<< SHIFT left input 1 the RU and gives it the respective command signal for
one of the operations.
5d19 IN2>> SHIFT right input 2

5d20 IN2<< SHIFT left input 2

IN1 IN2 EN_LU CM_CODE
Relational Unit

5d21 IN1<IN2 Compare input 1 is greater than IN1 & IN2 IN1^IN2 ~IN1 IN1|IN2 IN2>> IN2<<
input 2

5d22 IN>IN2 Compare input 1 is smaller than IN1 IN2 IN1 IN2 ~IN2 IN1IN2 IN1>> IN1<<
input 2

5d23 IN1==IN2 Compare two inputs are equal

OUT1

Table I. Instruction Set with functions summary

Figure 5. Logical Unit Architecture
 IN1 IN2 EN_RU CM_CODE
Timing # Slices # Registers Fmax %Utilization
Performance MHz
Strategy
IN1== IN2 IN1<IN2 IN1> IN2 Virtex-5 101 38 456.6 0.1%

Virtex-6 88 10 .703.7 0.08%

Table VI. Timing Performance Strategy Slice Utilization summary

OUT1

C. Balanced Strategy Results

Balanced strategy is applied to implement the design
Figure 6. Relational Unit Internal Architecture for optimum efficiency utilizing the tradeoff between
area and throughput. It is the software embedded tool
in Xilinx 13.1. Results of this strategy are shown in
table VII.
Relational Slices # Registers Fmax %Utilization
Unit LUTs MHz
Utilization
Virtex-5 19 0 645.16 0% Balanced # Slices # Registers Fmax %Utilization
Strategy MHz
Virtex-6 18 0 671.1 0%

Table IV. Relational Unit Slice Utilization Virtex-5 132 38 553.08 0.11%

Virtex-6 95 3 1671.1 0.09%

Table VII. Balanced Strategy Slice Utilization summary

V. OUR IMPLEMENTATION
Implementation is carried out on Virtex-5 and Virtex-6
platforms. Devices used are Xc5vlx50T-3ff and
Xc6vcx75T-2ff. Three design approaches are applied in
the synthesis and implementation steps, which are area
reduction, timing performance and balanced strategy.
Implementation and Simulation is done is using ISE
Xilinx Tool 13.1. Simulation graphs of our work are
shown in fig 6 & 7.
CONCLUSION
The paper focuses on detail design review of ALU
implementation on Virtex family. Results in Table V,
VI and VII shows that our work is efficient in terms of
both device utilization and maximum achievable
frequency.

ACKNOWLEDGMENT
VI. RESULTS This work is achieved due to continuous
encouragement of my project manager and team
Post, place and route results using Xc6vcx75t-2ff484 members.
of Virtex-6 and Xc5vlx50t-3ff1136 of Virtex-5 are
given in table V, VI and VII.

A. Area Reduction Strategy Results

REFERENCES
Area reduction strategy is applied to reduce area of
[1] B.Stephen Brown, V. Zvonko, Fundamentals of digital logic
ALU design. It is the software embedded tool in Xilinx with VHDL Design, 2nd Edition, McGraw Hill International
13.1. Results of this strategy are shown in table V. Edition, 2005.
Area # Slices # Registers Fmax %Utilization [2] Behrooz Parhami Computer Arithmetic Algorithms and
Reduction MHz Hardware Designs, Published by Oxford University press,
Strategy 2000
Virtex-5 97 38 480.7 0.08% [3] Milios D. Ercegovac, Tomas Lang, Digital Arithmetic,
Published by Morgan Kaufmann, 2004
Virtex-6 85 7 670.2 0.06% [4] Ronald J. Tocci, Neal S. Widmer and Gregory L.Moss,Digital
systems principles and applications, 2007.
Table V. Area Reduction Strategy Slice Utilization summary
[5] Samir palnitkar, Verilog HDL A guide to digital design and
Synthesis, second edition 2003 Pearson education
B. Timing Performance Strategy Results [6] Ateeq A. Khan, An Improved Design of ALU Targeted to
Timing performance strategy is applied to implement State-of-the-Art FPGAs, European Journal of Scientific
the design for optimum throughput. It is the software Research(EJSR),Vol.63 No.3 (2011), pp. 456-463
[7] Shikha Khurana and Kanika Kaur, "Implementation of ALU
embedded tool in Xilinx 13.1. Results of this strategy using FPGA, International Journal of Emerging Trends &
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2, July August 2012
[8] Geetanjali and Nishant Tripathi," VHDL Implementation of Engineering, Electrical and Electronics
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ICETIE 2012 [11] Vitex-5 family overview and reference guide
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[10] S.Kaliamurthy and U.Sowmmiya, VHDL Design of FPGA 0.pdf
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Figure 6. Arithmetic Unit simulation Results

Figure 7. Logical and Relation Units simulation Results