Gate Level Simulation (GLS)

Introduction
Need
Flow
Challenges
Project Cycle
Introduction
Gate level simulation is to increase the level of
confidence about a design implementation.
Helps to verify dynamic circuit behavior that cannot be
accurately verified with static methods.
A representative subset of RTL testcases run on the
final netlist with SDF back-annotation, under different
timing corners.
Need
To check if reset release, initialization sequence and
boot-up is proper.

To check if there is any unintended dependencies on

initial conditions.

To check if there is any issues in asynchronous paths/

interfaces (not analyzed in STA).

A sanity check on the timing constraints:

-can show up missing or wrong constraints.

It's an excellent feel good quotient that the design has

been implemented correctly.
Flow Netlist (Verilog)

List of the Flops with out preset/clear

GLS Environment
List of the synch Flops
Setup

N
Zero/Unit delay o
Gate level All
Simulation & Reports Tests
Debug Pass
Yes

Timing simulation SDFs for required Timing corners

& Debug IO min/max delay from IO specs

Reports

All
N
o Tests
Pass
Pass

Signoff
Flow contd.
Select a subset of the RTL functional tests to get:
- Good toggle coverage at IO level.
- Good coverage of major functional/boot modes.
- Good exception coverage.
List of synchronizing flops for which timing should
be disabled.
List of non resettable flops/latches whose outputs
should be initialized.
Simulate the netlist with no timing check, to make
sure netlist and GLS setup have no issues.
MIN SDF, for HOLD violations.
MAX SDF, for SETUP violations.
Challenges
Propagation of X due to uninitialized flops /
memory.
- Identify flops without reset-preset with the help of Synthesis/
timing tool and initialize them during reset.
- Manual tracing option. Initializing with either 0 or 1 should work.

X propagation due to timing violations at

synchronizer flops.
Identify synchronizers and multi-cycle paths with the help of
synthesis and timing tools and put necessary waivers.

Issues with intermediate SDF

- Debugging difficulty when SDF is not timing clean, especially hold .
- When part of the design is not closed (setup), iterative runs
needed to see the supported max frequency.
Challenges contd.

Functional failures:
Analyze timing violations and cross-check and close this w.r.to
the exceptions set in STA.
Identify timing violations due to incorrect false_path or multi-
cycle_path specifications.

Big dump files when simulation hangs or

progresses incorrectly
Add sanity checkers and stop simulation when simulation
progress is incorrect.
Project Cycle:
SoC subsystem comprising of ARM CortexA8, TI-64x+ DSP, Ethernet
MAC, DMA, PCI, SPI, UART, Timers, DDR2 interface, flash interface.
A golden list of around 50 testcases selected for GLS.
First testcase (DDR2 access) was used for checking the booting
of ARM when DSP is kept in reset.
Un-initialized flops causing X propagation were traced using Debussy
and initialized by forcing (either 1 or 0 randomly) on the Q for one
clock cycle during reset region.
Un-initialized flops distributed across different testcases, as they were
covering different functional paths.
List of synchronizers were listed from PrimeTime, and timing checks
were disabled on the first flop of the synchronizer.
Created VMC model for netlist with SDF back-annotation for
customer simulation releases. SDF files modified to disable timing
checks on synchronizers.
Project Cycle: contd.
Around 75% of the RTL test list could be run using the golden GLS
setup.
GLS was run on both subsystem level and the full-chip level.
Test vectors for silicon validation were prepared from dump of
GLS runs.

Issue Fixed 1: Timing violations were found in SPI master read

path. Issue found to be due to missing constraint on the feedback
clock.

Issue Fixed 2: Recovery-check violation found on the reset signal.

Constraint update was required.