MSP430

Hardware and software summary

MSP430 overview
MSP430 architecture
Instruction set & assembly programming
MSP430 instruction set architecture
MSP430 assembly programming
Microprocessor board/system Practice
MSP430 F5438 Features
Programming MSP430
MSP430F5438 Experimental Board
MSP430 Practices/Labs
2017/10/28 T. L. Jong, Dept. of E.E., NTHU 1
 MSP430 Overview
MSP430 Brief overview
MSP430 Typical applications
MSP430 Key features
Ultra-low power
High performance
Highly integrated intelligent peripherals
Easy to get started
MSP430 Family/Generations
MSP430 Peripheral Overview
MSP430 Architecture

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 2

 MSP430 Overview
The MSP430 family:
From Texas Instruments (TI).
Ultra-low-power 16-bit RISC mixed-signal processors
Enable system designers to simultaneously interface to analog signals,
sensors and digital components while maintaining unmatched low
power.
Provides the ultimate solution for battery-powered measurement
applications.

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 3

 MSP430 Typical Applications
Typical applications:
utility metering
portable instrumentation
intelligent sensing
consumer electronics

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 4

 MSP430 Overview

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 5

MSP430 for energy harvesting
Self- or Perpetual Power Apps
MSP430 for various applications
LowPower Networking
 MSP430 Key Features
Ultra-Low-Power + High Performance
Ultra-low power
Lowest power consumption
Standby < 1 A
including RTC and BOR
Active160 A/MIPS
Instant wakeup <1 s
Built-in voltage regulator
4 programmable voltage level
Leakage current < 50 nA pin
Highly integrated
14 to 113 pins
1-256kB Flash/ROM
10-/12-/16-bit ADC
12-bit D/A, LCD driver, RTC, DMA
ComparatorOpamp
Supply Voltage Supervisor & BOR
16-bit and 8-bit timers; WDT
I2C, SPI, UART/LIN, IrDA
USB & RF
High performance
16-bit RISC CPU up to 25MHz
Industry leading MCU program efficiency
Flexible clock system
Single instruction cycle register
operation
16 16(20)-bit registers
No accumulator bottleneck
Easy to get started
C-friendly IDE and compiler
IDE and MSP430Ware for easy software
developing
Embedded Emulator module
Trace, single-stepping, in-system debug
Intelligent peripherals
DTC, DMA, Autoscanning A/D
Free or low-cost development tools
 Ultra-low-power (ULP)
The MSP430 MCU is designed specifically for ultra-low-power
applications.
Its flexible clocking system, multiple low-power modes,
instant wakeup and intelligent autonomous peripherals
enable true ultra-low-power optimization, dramatically
extending battery life.

Low Power Active

Mode
7 Flexible Low Power
Modes
<1s wakeup time
Autonomous,
integrated peripherals

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 9

 Sources of power consumption
Dynamic power
Charging and discharging of capacitors and on switching
activity
Short circuit power
Leakage - leaking diodes and transistors

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 10

 Dynamic Power (01 transition)
CMOS inverter
CL gets charged through
PMOS
Part of the energy is
dissipated in PMOS
transistor
Remaining is stored on
load capacitor, CL

1
Energy stored in capacitor, EL C LVdd2
2

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 11

 Dynamic Power (10 transition)
CMOS inverter
The charge stored on load
capacitor, CL gets discharged
through the NMOS
transistor

Average power dissipation for a switching cycle,

Pav = CLV2dd (assuming at 1Hz)
If the frequency at which switching happens is f,
Pav = CLV2dd f
(Source : Digital Integrated Circuits, Jan Raba)
2017/10/28 T. L. Jong, Dept. of E.E., NTHU 12
 Short-Circuit Power
CMOS inverter

Pav = CLV2dd f, Psc = tscVddIpeak f = gscV2dd f < 0.1 Pav

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 13

 Leakage Power
CMOS inverter
Ideally, the static current of a
CMOS inverter is ZERO
In reality, a small leakage
current flows through the
reverse biased diode junctions
of transistors, located between
the source or drain and the
substrate

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 14

 Trade-off between power and speed(1
of 2)
Power consumption of CMOS circuits (ignoring leakage)

P = aCLV2dd f
where,
a= switching activity
CL = load capacitance
Vdd = supply voltage
f = frequency

Decreasing voltage reduces power consumption

(quadratically)

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 15

 Trade-off between power and speed(2
of 2)
Propagation delay of CMOS circuits(Inverter)

Higher supply voltages reduce delay but increase power

consumption (due to quadratic relation)
All of the above leads to the need for power saving
techniques
2017/10/28 T. L. Jong, Dept. of E.E., NTHU 16
 Power saving techniques(1 of 3)
Trade-off performance to save power
Reduce power supply voltage
Reduce frequency
Structural power saving techniques
Disable peripheral when not in use (E.g. Clock Gating)
Disconnect modules from power supply when not in use (E.g.
Power Gating)

Note : Dynamic Voltage Frequency Scaling (DVFS) uses both

voltage and frequency scaling for power conservation

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 17

 Power saving techniques(2 of 3)
Clock gating Deactivate clocks to unused registers
Registers in unused serial communication
Signal gating Deactivate signals that cause activity if not in
use
Address and data buses for non-memory instructions
Power gating Deactivate Vdd for unused HW blocks
Floating Point Unit (FPU) for integer program

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 18

 Power saving techniques(3 of 3)
CPUs provide multiple power down modes e.g., MSP430
LPM modes
Start-up time, it should be fast enough to wake-up quickly
and finish the job.
More details on how MSP430 achieves low power
consumption can be found in the references

Low Power Active Mode

<1s wakeup time
Autonomous, integrated peripherals
7 Flexible Low Power Modes

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 19

 Ultra-low active power

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 20

Battery life when 1% active
Battery life when 0.1% active
 Best-in-class wakeup time

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 23

 Always on Brownout Reset (BOR)

Zero-powerrownout reset

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 24

 Low power modes

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 25

 High Performance
16-bit orthogonal RISC CPU architecture up to 25MHz
The MSP430 MCUs 16-bit architecture provides the flexibility of
16 fully-addressable, single-cycle, 16(20)-bit CPU registers
(R0~R15) with the power of a RISC.
The modern design of the CPU offers versatility using only 27
easy-to-understand instructions and 7 consistent addressing
modes.
Single instruction cycle register operation
No accumulator bottleneck
Industry leading MCU program efficiency
Flexible clock system

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 26

16-bit Orthogonal RISC CPU
High performance, ultra low power CPU
16 16(20)-bit registers (R0,R1R15)
No accumulator bottleneck
7 addressing modesonly 27
instructions
Very easy to use
Designed for C and assembly program
development
Higher compilation/execution
performance
Single-cycle operations
High efficiency
Flexible and modularized system
100% compatibility
Direct Memory-to-memory addressing
Support bit , byte, and word manipulation
MSP430 CPUX can support up to 20bit
 Flexible clock system
The MSP430 MCU clock system has the ability to enable and
disable various clocks and oscillators which allow the device to
enter various low-power modes (LPMs).
The flexible clocking system optimizes overall current
consumption by only enabling the required clocks when
appropriate.
Main Clock (MCLK) CPU source that may
be driven by the internal Digitally Controlled
Oscillator (DCO) up to 25 MHz or with
external crystal.
Auxiliary Clock (ACLK) Source for
individual peripheral modules driven by the
internal low-power oscillator or external crystal.
Sub-Main Clock (SMCLK) Source for faster
individual peripheral modules that may be
driven by the internal DCO up to 25 MHz or
with external crystal.
2017/10/28 T. L. Jong, Dept. of E.E., NTHU 28
Highly Integrated intelligent peripherals
Highly Integrated
MSP430 MCUs are highly integrated and offer a wide range of high
performance analog and digital peripherals.
Intelligent Peripherals
The MSP430 MCUs peripherals have been designed to assure maximum
functionality and provide system-level interrupts, resets and bus
arbitration at the lowest power. Many peripherals may function
autonomously, thereby minimizing CPU time spent in active mode.
High-Performance Integration
The 500+ MSP430 devices offer high-performance integration including
USB, RF, LCD controllers and Sigma-Delta ADCs. The scalable portfolio
allows designers to find the appropriate MSP430 device for many low
power applications. The MSP430 MCUs high integration also enables
solutions with smaller physical footprints and minimizes the overall bill
2017/10/28
of materials. T. L. Jong, Dept. of E.E., NTHU 29
Highly Integrated intelligent peripherals
14 to 113 pins
1-256kB Flash/ROM
128 B 16 kB SRAM
10-/12-/16-bit ADC
12-bit D/A, LCD driver, RTC, DMA
ComparatorOpamp
Supply Voltage Supervisor (SVS) & BOR (Brown out reset)
16-bit and 8-bit timers; WDT
I2C, SPI, UART/LIN, IrDA
USB & RF

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 30

 Integrated intelligent peripherals

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 31

 Fast flexible 10- 12-bit ADCs

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 32

 16-bit Sigma-Delta ADCs

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 33

 DAC12

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 34

 Analog Comparator

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 35

 LCD Controller

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 36

 USCI: Serial Communication I/F

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 37

 Do more in low power modes

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 38

 Easy to Get Started
C-friendly IDE and compiler
Embedded Emulation Module (EEM)
Trace, single-stepping, in-system debug
Intelligent peripherals
RTC, DMA, Autoscanning A/D, , etc.
Complete Development Ecosystem
The MSP430 development environment is affordable, seamless and easy-
to-use.
Get started with the $4.30 MSP430 Value Line LaunchPad development
kit, or use the adaptable MSP-FET430UIF that supports development on
all MSP430 devices.
Also, download free IDE options such as TIs Code Composer Studio IDE,
IAR Embedded Workbench or the open-source MSPGCC.
MSP430Ware is also available, which is a complete collection of all
MSP430 MCU related design resources.
2017/10/28 T. L. Jong, Dept. of E.E., NTHU 39
 MSP430 Development Ecosystem
MSP430 Hardware Tools

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 40

 MSP430 Development Ecosystem
MSP430 Hardware Tools

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 41

 MSP430 Development Ecosystem
MSP430 Hardware Tools

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 42

 MSP430 Development Ecosystem
Integrated Development Environment

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 43

 MSP430 Development Ecosystem
Enhanced libraries

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 44

 MSP430 Development Ecosystem
Enhanced libraries

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 45

 MSP430 Development Ecosystem
Scalable toolchain

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 46

 MSP430 Family
The MSP430 family: FRAM ()
1 series
MSP430
2 series FRAM (flash
Value Line 1000)(flash
250)
4 series

5 series FRAMEEPROM
6 series 30%1
Flash10
FRAM series
Low Voltage series
RF SoC series EEPROMMRAM
FRAM
Fixed Function
Automotive
Extended Temperature

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 47

 MSP430 Generations
Within the MSP430 platform, it includes 5 generations of ultra-low power,
highly integrated microcontrollers spanning over 500 devices.
Each generation offers various levels of analog integration, digital
peripherals, and communication protocols to help developers find the
right microcontroller for various applications.

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 48

MSP430 Roadmap
MSP430 Roadmap
 MSP430 Generations

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 51

 MSP430 Generations

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 MSP430 Generations

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 53

 MSP430 Part Number Decoder

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 54

 Main Advantages of F2xx
Clock: up to 16MHz
Memory: up to 120K flash, 8k RAM
Voltage: 1.8~3.6V
Smart Analog and digital:
Scan interface
24-bit S-D ADC
Low power
200 A/MHz active
0.7 A RTC mode
0.1 A RAM retention
Ultra-fast wake-up from standby mode in <6 s
Almost no power consumption BOR
Failsafe oscillator
Enhanced watchdog
Pull-up/pull-down resistor
Hack-prevented boot loader
2.2V Flash write voltage
Temperature extends to 105C
Same instruction set, same architecture

slau144j.pdf
 The Outside View of F2xx

Pin-out of the MSP430F2003 and F2013, taken from the data sheet.
P1.0P1.7, P2.6, and P2.7 are for digital input and output, grouped into ports P1 and P2.
TACLK, TA0, and TA1 are associated with Timer_A; TACLK can be used as the clock input to the timer, while TA0
and TA1 can be either inputs or outputs.
A0, A0+, and so on, up to A4, are inputs to the analog-to-digital converter.
SCLK, SDO, and SCL are used for the universal serial interface, which communicates with external devices
using the serial peripheral interface (SPI) or inter-integrated circuit (I2C) bus.
TCK, TMS, TCLK, TDI, TDO, and TEST form the full JTAG interface, used to program and debug the device.
SBWTDIO and SBWTCK provide the Spy-Bi-Wire interface, an alternative to the usual JTAG connection that
saves pins.
 The Inside View of F2xx

Block diagram of the MSP430F2003 and F2013, taken from the data sheet.
 MSP430F2xx Series
Other Integrated Price
Family Flash RAM I/O 16-bit Timers ADC Comm.
Peripherals USD 1kU
F20x1 2 KB 128 B 10 A2, WDT Slope Comp $0.55 $0.80
F20x2 2 KB 128 B 10 A2, WDT ADC10 USI $0.80 $0.95
F20x3 2 KB 128 B 10 A2, WDT SD16 USI $1.20 $1.30
F21x1 8 KB 256 B 10 A2, A3, WDT Slope Comp $0.65 $0.95
F21x2 8 KB 512 B 10 A2, A3, WDT ADC10 USCI $1.20 $1.50
F22x2 32 KB 1 KB 10 B3, A3, WDT ADC10 USCI $1.75 $2.20
F22x4 32 KB 1 KB 10 B3, A3, WDT ADC10 USCI 2 Op Amp $2.00 $2.65
F23x0 32 KB 2 KB 10 B3, A3, WDT Slope USCI Comp, MPY $1.80 $2.25
F23x 16 KB 2 KB 10 B3, A3, WDT ADC12 USCI SVS, Comp, MPY $2.15 $2.45
F241x 120 KB 4 KB 48 B7, A3, WDT ADC12 2 USCI SVS, Comp, MPY $4.70 $5.30
F24x 56 KB 4 KB 10 B7, A3, WDT ADC12 2 USCI SVS, Comp, MPY $3.40 $4.60
F24x1 60 KB 2 KB 10 B7, A3, WDT Slope 2 USCI SVS, Comp, MPY $3.15 $3.80
SVS, Comp, MPY,
F261x 120 KB 4 KB 48 B7, A3, WDT ADC12 2 USCI $5.85 $6.65
2 DAC12, 3 DMA

USCI_A : UART + SPI USCI_B: I2C + SPI USI: I2C + SPI USART: SPI + UART
 F4xx Key Features
The MSP430F4xx generation
features: ultra-low power, highly-
integrated, flash-based.
<1mA standby LPM3
<1ms, up to 16MHz CPU speed
Flash: 4-120kB, RAM: up to 8kB
Zero-power BOR
Built-in LCD driver
GPIO: 14 80, pull-up/down R,
Ideal for metering and medical-
specific apps
Featuring SD16, OpAmps, ESP430,
LCD, and more
Same ISA
slau056j.pdf
2017/10/28 T. L. Jong, Dept. of E.E., NTHU 59
 F4xx Block Diagram

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 60

 The Inside View of F4xx

Block diagram of the MSP430F415 and F417, taken from the data sheet.
 Main Advantages of 5xx
Ultra low power MSP430F5xx Block Diagram
165 A/MIPS
2.5 A standby mode(LPM3) Unified Clock
System
16-bit
RISC CPU
Built-in LDO, BOR, WDT+, RTC DMA
Controller
Flash

12 MHz @ 1.8V Power Management

Enhanced
Embedded
Wake-up <5 s Module Emulation System
Control/
Supply Supervisors JTAG Watchdog RAM
Increased performance Supply Monitors
Brownout
Spy Bi-Wire
Interface
Up to 25 MHz
1.8V ISP Flash erase and write Computation Timing and Control Signal Chain Communication I/O &Display

Fail-safe flexible clock system General Purpose Universal Serial General

Hardware
Timers /Capture Communication Purpose /IO,
32x32 Compare PWM Comparators
Interfaces Pull-Up/Down,
User-defined Bootstrap Loader Multiplier Outputs (SPI, UART, I2C) High Drive

over 1MB linear memory address Basic Timer USB 2.0 Segmented
space CRC + ADC (Full Speed) LCD, Static,
RTC Engine+ PHY Muxed

Innovative features
Multichannel DMA supports data AEC DAC RF Transceivers

movement in standby mode

Industry leading code density Operational
Includes more peripherals such as
Amplifiers

USB, RF, encryption, LCD.

 Whats New in 5xx
MSP430F51xx HiResPWM,
Applications include:
CompB, 5V I/O LED lighting Applications with AC inputs
Performance Portable LED Back Light solutions
16-bit RISC architecture, 40ns instruction Battery powered LED spatial lighting
cycle time High resolution Cap Touch
Ultra-Low-Power, Integrated Analog, and
Easy-to-Use

Features
F5xx Architecture
Ultra-low power in active and sleep modes,
ultrafast wake-up from standby in <1 s
1.8-3.6V, 1.8V ISP Flash erase and write
Timer_D supporting Hi-resolution PWM
Comp_B with 16 inputs
5V tolerant push and pull Ios
38-pin DA (TSSOP); 40-pin RHA (QFN) (6mm
x 6mm)

Benefits
Precise control applications such as LED
lighting or motor control
Cap touch applications such as cell phone
keypad, legacy button replacements, PC
mouse
 MSP430F5xx
Other Integrated Price
Family Flash RAM IO 16-bit Timers ADC Comm.
Peripherals USD 1kU
F541x DMA, UCS,
128 KB 16 KB 67,87 A5,3,B7,WDT ADC12 2,4 USCI $3.30 - $3.65
18 MHz MPY(32X32)
F541xA DMA, UCS,
128 KB 16 KB 67,87 A5,3,B7,WDT ADC12 2,4 USCI $3.30 - $3.65
25 MHz MPY(32X32)
F543x DMA, UCS,
192-256 KB 16 KB 67,87 A5,3,B7 ADC12 2,4 USCI $3.90 - $4.85
18 MHz MPY(32X32)
F543xA DMA, UCS,
192-256 KB 16 KB 67,87 A5,3,B7 ADC12 2,4 USCI $3.90 - $4.85
25 MHz MPY(32X32)
USB, DMA, UCS,
F551x 64 KB 6-8 KB 48,60 A5,3,3, B7 _ USCI $3.25 - $3.35
MPY(32X32)
USB, DMA, UCS,
F552x 64-128 KB 6-8 KB 48,60 A5,3,3, B7 ADC12 2 USCI $3.55 - $4.10
MPY(32X32)

USCI_A : UART + SPI USCI_B: I2C + SPI

 MSP430F5xx Operating Range

Up to 25MHz operating 25 MHz

frequency
Operating frequency Wide Max MCLK

PMMCOREV = 2
16 MHz
adjusted according to

PMMCOREV = 1
working voltage 12 MHz

PMMCOREV = 0
VCC scope vs. F2xx
Flash ISP @ 1.8V Flash Programmable
4 MHz
12MHz @ 1.8V
Across Entire Range
25MHz @ 2.4V-3.6V
1.8V 2.0V 2.2V 3.6V
MSP430 16-bit RISC CPU
5xx MSP430Xv2 Orthogonal CPU
Unified Clock System (UCS)
5xx Operating Modes
5xx Voltage vs. Frequency Operating Range
 F5xx: Power Management Module
Built-in LDO (low-
dropout voltage
regulator) module
Programmable VCORE
Supply votage
monitoring (SVM) and
supervision (SVS), and
Zero-power Brown-
out reset (BOR)
5 supervision and
monitoring modules
SVSH, SVSL, SVMH,
SVML & BOR
5xx Memory Map
 MSP430 Peripheral Overview

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 73

5xx Peripherals The System Module (SYS)
5xx Peripherals GPIO
5xx Peripherals Port Map Module
Universal Serial Communications Interface
5xx Peripherals LCD_B & AES128
5xx + USB
5xx + Low Power RF The CC430
5xx Embedded Emulation
5xx Embedded Emulation
MSP430 Package Options
 MSP430 Architecture
A 16-bit RISC CPU, memory-mapped analog and digital
peripherals and flexible clock system are combined by using a
von-Neuman common memory address bus (MAB) and memory
data bus (MDB).

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 84

16-bit RISC CPU
High performance, ultra low power CPU
16 16(20)-bit registers (R0,R1R15)
No accumulator bottleneck
7 addressing modesonly 27
instructions
Very easy to use
Designed for C and assembly program
development
Higher compilation/execution
performance
Single-cycle operations
High efficiency
Flexible and modularized system
100% compatibility
Direct Memory-to-memory addressing
Support bit , byte, and word manipulation
MSP430 CPUX can support up to 20bit
 MSP430 Memory Architecture
Von-Neumann Architecture
Unified memory
Clear, no exception, easy to understand
Includes code, data, peripherals
High Compiler efficiency
Same instruction can access
RAM/ROM/peripherals
Program can run from RAM

Address Modes Source

 Benefits of more CPU Registers

Utilize more single instruction cycle register addressing

mode
Very useful in computation
 Byte, Word, and CPU Registers

Use CPU Register in computation or as storage for

variables
Word or byte occupy same code size
Use word operation as much as possible
Do you use 10 bits or more ADC?
Memory
10-bit
ADC 10-bits

Other MCU MSP430

movf ADCRESH,W mov ADC10MEM,RAM
movwf RAMH
bsf STATUS 0x20
movf ADCRESL,W
bcf STATUS 0x20
movwf RAML

84 bits / 24 cycles 48 bits / 6 cycles

 Atomic memory-to-memory

Direct access memory

Applicable to all instructions
 Constant generator

Hardware generated immediate constants (-1,0,1,2,4,8)

Reduce code size and execution time
Make program more efficient

And this is completely automatic

 24 Emulated instructions

Easier to understand without increasing code size or

reducing execution speed.
Use MSP430 core instruction to replace emulated
instruction in assembling.

Of course, its automatic

 Interrupt and ISR
Item1
Item2 SP Prior to ISR SPTOS (with item)

ISR hardware automatic

Item1
PC pushed to stack
Item2 SR pushed to stack
PC Interrupt vector copied to PC
SR SP GIE, CPUOFF, OSCOFF SCG1 cleared
IFG flag cleared if it comes from single
interrupt source.
Item1
Item2 SP reti automatic
PC SR popped from stack
SR (original)
PC popped from stack
 Unified Memory Map
0xFFFF Interrupt Vectors
No pages
More flexible in Flash
programming Main Segments
(x)512B
ISP Flash
Self Programming
Info Segments
JTAG / Spy-Bi-Wire
Boot Loader
BSL RAM
0x0000 Peripherals
 Interrupt and memory map
0x45BFF Flash
Main Segments
(x)512B
0xFFFF

Interrupt Vectors 0xFFFF Interrupt

0xFF80
Vectors

Flash
Main Segments Flash
(x)512B Main Segments
(x)512B

RAM

Info Segments
Info Segments

Boot Loader Boot Loader

RAM
MSP430F5438 MSP430F2013
Peripherals
Peripherals
0x0000
0x0000
 Compiler Friendly
Code Size in Bytes
7000

6000

5000
Code Size (Bytes)

4000

3000

2000

1000

0
MSP430FG4619 MSP430F149 PIC24FJ128GA PIC18F242 8051 H8/300H MaxQ20 ARM7TDMI HCS12 AT Mega 8
(Thumb)

Only 27 core instructions. Every instruction can access the

whole memory space using every addressing modes, which
not only saves power but also reduces cost.
Application report SLAA205
 How to Program Flash ROM
Via JTAG /Spy bi wire interface
Built-in in every MSP430
Can be used for flash device programming or program developing
4-wire JTAG or two-wire Spy bi wire
Security fuse for protecting IP
Via Bootstrap Loader (BSL)
Built-in in most MSP430
Can only be used for device programming and data reading
UART-based interface
Need four signal lines
IP protection through built-in features
In System Programming by the CPU
Spy Bi-Wire In-System Emulation
VCC 1 14 VSS Spy Bi-Wire
JTAG

MSP430F20xx
2 13
3 12 VCC
TMS

4 11 TEST/SBWTCK TCK
TCK
5 10 RST/SBWTDIO TDIO
TDO/TDI
6 9 GND
TCK
7 8

Used to interface with MSP430 development tools

and device programmers.
Easy to use, does not use any MCU resources,
bidirectional
Full speed execution
single-step
Hardware breakpoint
Compatible to MSP430 development environment
 References
(slas612C) MSP430f5438 MSP430F543x, MSP430F541x Mixed
Signal Microcontroller (Rev. C)
(slas655B) MSP430f5438a MIXED SIGNAL MICROCONTROLLER
(slau208k) MSP430x5xx Family User's Guide
(slau157u) Code Composer Studio v5.2 User's Guide for
MSP430
(slau138y) IAR Embedded Workbench Version 3+ for MSP430
(slau263g) MSP-EXP430F5438 Experimenter Board

2017/10/28 T. L. Jong, Dept. of E.E., NTHU 99