Company Overview

3D-IP Semiconductors Pvt Ltd is a Bangalore based semiconductor chip design company
offering IPs, engineering services & customised solutions in Memory, Mixed-Signal & Digital
design domain

Position
We are hiring DFT engineers with 2-8 years' experience for Bangalore, Hyderabad and Noida
location. If you are interested, please share your CV to this posting or to careers@3dipsemi.com

Responsibilities
Perform Scan/MBIST/BSCAN insertion
ATPG pattern generation & Simulations
Compression techniques, JTAG, Boundary scan & Memory BIST
Handling Synopsys DFT compiler, Tetramax, DFT-Max & BSD Compiler

Desired Skills

Experienced engineers with DFT flow, ATPG, Scan, BIST and Mentor TestKompress
Expert in writing test benches (Verilog, system Verilog)
Good knowledge in BSCAN, MBIST Operations
Knowledge of ATPG and different fault modules (SA, Transitions, lddg, SDD)
SoC integration & RTL modification as per DFT requirement
Knowledge of Boundary scan testing, testing of IP viz ADC, Flash, PMU in standalone mode.
Basic knowledge of Logic BIST operation, Synthesis constraints, ATE , Silicon defects and its
logical effects
Awareness of Low power ATPG, Analog BIST, Logic BIST

Address: 3D-IP Semiconductors Pvt. Ltd, Global Incubation Services, JSS Institution Campus, HAL 3rd Stage, Kodihalli,
Bangalore 560008, Karnataka - India.
Website: www.3dipsemi.com E-mail: careers@3dipsemi.com , Phone: +91-9916903643
 Our products and services
Embedded Memories

Custom & Compiler Memory (SRAM, ROM) IPs and customized solutions in FINFET,
28nm, 40nm, etc. process nodes
Patent on a novel High-Speed SRAM Memory Compiler Architecture
embedded Flash Memory

Mixed Signal

PLL, ADC, DAC, Sensors, etc. IPs and customized solutions in 28nm, 40nm, etc.
process nodes
Full Chip integration and mixed signal verification
Behavioral AMS modelling in Verilog-AMS to support ASIC flow

Digital

Offer IP and VIP for various protocols; UFS, M-PHY, Ethernet, DDR, Bluetooth etc.
Offer Electronic System Level (ESL) models; Virtual Prototyping & SystemC modelling
Expertise in IP and SOC Level verification using UVM verification methodology

Address: 3D-IP Semiconductors Pvt. Ltd, Global Incubation Services, JSS Institution Campus, HAL 3rd Stage, Kodihalli,
Bangalore 560008, Karnataka - India.
Website: www.3dipsemi.com E-mail: careers@3dipsemi.com , Phone: +91-9916903643