A 60GHz CMOS Class C Amplifier Intended for Use in Doherty Architecture

Mohammadhassan Akbarpour, Mohamed Helaoui, and Fadhel Ghannouchi

Department of Electrical and Computer Engineering, University of Calgary, Calgary, Canada
Email: makbarpo@ucalgary.ca, mhelaoui@ucalgary.ca, fadhel.ghannouchi@ucalgary.ca

Introduction

60GHz frequency band is considered to be used for wireless personal area networks (WPAN) in different
standards [1-2]. To enable high data rates and also non-line of sight (NLOS) transmission in this band,
signals having high peak to average power ratios (PAPR) are recommended in these standards. OFDM
and 64-QAM signals are examples of the high PAPR signals recommended in these standards.

CMOS is a very well established technology for digital circuits. Since there is a large tendency to
integrate all of the system components in a single chip with low cost, the RF components are needed to be
implemented in CMOS. One of the most challenging components in 60GHz transmitters is the RF power
amplifier. In high frequencies like 60GHz, CMOS power amplifiers do not have good performance in
terms of efficiency. The peak efficiencies obtained so far for the CMOS power amplifiers at 60GHz are in
order of 10-18% [3-5], but having the high PAPR signals mentioned, the efficiency of the amplifiers will
be much lower since the probability density function (PDF) of these signals are concentrated in the back-
off region where the efficiency of these power amplifiers are very low. The previous works have
efficiencies in order of 2-6% at 6dB power back-off [3-5].

The Doherty architecture solves this problem by providing high efficiency at power back-off. It is well
established in lower frequencies, but in 60GHz to the best of our knowledge there is only one published
work in 130nm CMOS [6] giving 3% of peak efficiency and lower efficiency at power back-off. The
Doherty power amplifier architecture is shown in Fig. 1. It consists of a class B or class AB biased main
amplifier and a class C peaking amplifier. One challenging component in the Doherty architecture for the
60GHz frequency band is the class C peaking amplifier. It should provide high output impedance at
power back-off not to have power leakage from the main amplifier. Having leakage into the peaking
branch will cause power loss at back-off and consequently decreasing efficiency at power back-off. On
the other hand, the peaking amplifier should have enough output power at peak input power to provide the
proper load modulation. These two requirements, combined with the low gain of class C amplifiers, make
the design of the class C peaking amplifier very difficult. In this paper, a 60GHz CMOS class C amplifier
is presented which is intended for use in the Doherty architecture. The design was performed so that both
requirements on output impedance and maximum output power are satisfied. The design procedure and
the equations needed to meet both requirements are given in the paper. Measurement results show that the
output impedance of this amplifier is high enough for use in Doherty architecture and also it has enough
output power for use in WPAN application.

Figure 1. Doherty power amplifier architecture Figure 2. Output matching network

978-1-4673-0946-2/12/$31.00 2012 Crown

 Design Procedure

The maximum transmitter output power specified in IEEE802.15.3C is 10dBm. This means that in the
Doherty amplifier, each branch should provide 7dBm of output power. Usually, the load impedance of the
Doherty architecture (RL in Fig. 1) is selected to be 25 . The standard 50 load impedance is usually
converted to 25 using a transmission line inverter. But in our design, we consider the load impedance to
be RL=50 not to need the output load impedance inverter. So the peaking amplifier will see load
impedance of 2RL=100 at peak power due to load modulation effect.

In our design, the amplifiers architecture selected to be a three-stage cascode amplifier. The bias used for
the cascode stages is selected to be 1.5V. Since there are two transistors stacked in the cascode stages, this
means that there will be 0.75V on each transistor which is less than the maximum voltage of 1.2V
specified for the technology used. To achieve safe operation of the amplifier, when turning on the
transistors, first the gate bias of the common source transistors should be applied and then the drain bias
should be increased to its final value of 1.5V. The transistors selected for the last stage are two parallel
transistors, each having 32 fingers of 2 m width. The transistors used in the second stage have 32 fingers
of 1.8 m width and the transistors used in the first stage have 24 fingers of 0.8 m width.

The design was started from the last stage which is the most important stage in this amplifier. To meet the
design criteria, the output matching network should convert the output impedance of the last stage
transistor to a high impedance. Also it should convert the load impedance of the Doherty amplifier at peak
power (i.e. 100) to an impedance close to the optimum impedance of the transistors in the last stage.
Consider the matching network shown in Fig. 2 as a lossless and reciprocal matching network. Then its
ABCD parameters can be expressed as [7]:
A B a jb
C D = jc d (1)

In which a, b, c, and d are real valued parameters. For the output admittance and transistors load we
have:
jc + aYT
Yout = (2)
d + jbYT
jc + dYL
YLT = (3)
a + jbYL
Since we need high impedance at power back-off, then (2) should be met by selecting a high value for
Yout. If we select a real value for Yout, then using (2), we will have:

c = Im(YT (a jbYout )) (4)

Re(YT (a jbYout ))
d= (5)
Yout
From reciprocity condition, we will have [7]:
ad + bc = 1 (6)
Using (4) and (5), (6) can be solved numerically in a-b plane to find the values of a and b satisfying (2).
Then from (3), the possible values of YLT can be found. The values of YLT for the last stage are shown in
Fig. 3. As can be seen from this figure, the YLT values lie on a circle. YLT can be selected to give the
highest possible peak output power. The load pull contours for the output power are also shown in Fig. 3.
In this case, YLT is selected as the intersection of the locus obtained by the analysis and the highest power
contour. By selecting YLT, the ABCD parameters can be found from the equations.
 Figure 3. the impedance transformations for the output stage Figure 4. pi network used as the matching network

Figure 5. Schematic of the final amplifier Figure 6. Photograph of the fabricated chip
To design the output matching network, we use the three-element pi network of Fig. 4. The elements of
this network can be found as described in [7]. To design the inter-stage matching networks and the input
matching network, the optimum load impedances for the first two stages and the large-signal input
impedances of three stages were obtained, and the proper impedance matching networks were
implemented. For the simulation of the transmission lines and inductors used in matching networks, the
CST Microwave Studio full-wave simulator was used. For the MIM capacitors and transistors, the models
from the design kit were used. The final amplifiers schematic is shown in Fig. 5.

Measurement Results
The amplifier was fabricated by the TSMC 65nm CMOS process. The fabricated chip is shown in Fig. 6.
The simulated and measured small signal output impedance of the amplifier are shown in Fig. 7. There is
a 7GHz frequency shift in the measurements compared to the simulations. This is caused by the model
inaccuracies for the capacitors and the transistors since the existing models in the design kit are verified
by the manufacturer only up to 30GHz frequency. Also in the EM simulations, there are some errors
because some substrate layers are very thin and with a reasonable mesh size and simulation time, the
simulator cannot simulate the substrate accurately.

The output power and the drain efficiency are shown versus input power in Fig. 8 and Fig. 9 respectively.
The matching network is designed for 100 load impedance, but the measurements are done in 50
impedance system. The simulation results for the 100 load show that the maximum output power will
be 1.8dB higher than that of the simulated amplifier having 50 load impedance. The maximum
measured output power is 5.4 dBm, so the expected output power of the fabricated power amplifier with
100 load impedance is around 7.2dBm which meets the design goal. To the best of our knowledge, this
is the first published 60GHz class C power amplifier implemented in CMOS technology.

To show suitability of the designed class C amplifier for use in the Doherty architecture, a simulation was
performed using this amplifier as the peaking branch. The main amplifier was a two-stage cascode class
AB amplifier designed at 60GHz frequency. The simulated power-added efficiency for the Doherty
amplifier is shown in Fig. 10. As can be seen from the simulation results, the PAE of the Doherty
architecture is higher than 12% at 6dB back-off which shows that the peaking amplifier has low leakage
at power back-off and enough output power to have proper performance in the final Doherty amplifier.
 Figure 7. Measured and simulated output impedance Figure 8. Measured and simulated output power

Figure 10. Simulated PAE of the Doherty architecture using

Figure 9. Measured and simulated drain efficiency the designed class C amplifier
Conclusion
A 60GHz CMOS class C power amplifier was designed and fabricated for use in Doherty architecture as
the peaking amplifier. It was designed to have high output impedance at power back-off and high output
power at peak power. The measurements showed that there is a frequency shift compared to the
simulations due to model inaccuracies, but the high output impedance was achieved along with the high
output power. Simulation results show that by using the designed power amplifier in the Doherty
architecture, a PAE of 12% can be achieved at 6dB output power back-off.

Acknowledgement
The authors would like to acknowledge the support from Canadian Microelectronics Corporation (CMC)
for CAD tools and fabrication. Also we would like to thank James Dietrich at ARFSL lab, University of
Manitoba for his collaboration in the tests.

References:
[1] IEEE standard 802.15.3c, Oct. 2009.
[2] ECMA-387 standard, second edition, Dec. 2010.
[3] J. Chen, A. M. Niknejad, "A compact 1V 18.6dBm 60GHz power amplifier in 65nm CMOS", IEEE ISSCC,
2011, pp.432-433.
[4] K. J. Kim, T. Lim, K. H. Ahn, J. W. Yu, "High gain and high efficiency CMOS power amplifier using multiple
design techniques," Electronics Letters , vol.47, no.10, pp.601-602, May 2011.
[5] D. Dawn, S. Sarkar, P. Sen, B. Perumana, M. Leung, N. Mallavarpu, S. Pinel, J. Laskar, "60GHz CMOS power
amplifier with 20-dB-gain and 12dBm Psat," IEEE MTT-S Int. Microw. Symp. Dig., 2009, pp.537-540.
[6] B. Wicks, E. Skafidas, R. Evans, "A 60-GHz fully-integrated Doherty power amplifier based on 0.13-m
CMOS process," IEEE RFIC Symp. Dig., 2008., pp.69-72.
[7] D. M. Pozar, "Microwave engineering", 2nd edition, Wiley, 1998.