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ANNAUNIVERSITY: CHENNAI-600 025

B.E/B.Tech DEGREE EXAMINATION, NOV/DEC 2017

REGULATION 2013

Third Semester

B.E ELECTRONICS AND COMMUNICATION ENGINEERING

EC6311: ANALOG AND DIGITAL CIRCUITS LABORATORY

Time: 3 Hours Maximum Marks: 100

1. a. Construct and verify the frequency response of CE amplifier.(50)


b. Design a gray to binary circuit and verify its truth table. (50)

2. a. Construct and verify the frequency response of CC amplifier.(50)


b. Design a binary to gray circuit and verify its truth table. (50)

3. Construct and verify the frequency response of CB and CS amplifier.(50+50)


4. Construct and verify the frequency response of Darlington amplifier.(100)
5. Analyze the Transfer characteristics of Differential amplifier and measure the
CMRR.(100)
6. a. Construct and verify the frequency response of Cascade amplifier.(50)
b. Design a BCD to Excess-3 code and verify its truth table. (50)

7. a. Construct and verify the frequency response of Cascode amplifier.(50)


b. Design a Excess-3 code to BCD and verify its truth table. (50)

8. a. Determine the bandwidth of single stage amplifier. (50)


b. Simulate Common emitter amplifier using spice. (50)
9. Construct and determine the bandwidth of multistage amplifier. (100)
10. a. Construct and determine the ripple factor of Half wave rectifier. (50)
b. Design a decoder using logic gates and verify its truth table. (50)

11. a. Construct and determine the ripple factor of Full wave rectifier. (50)
b. Design an encoder using logic gates and verify its truth table. (50)
12. a. Design a 3-bit synchronous up-down counter and verify its truth table. (50)

b. Simulate Common source amplifier using spice. (50)

13. Design a 4 bit Ripple, MOD -10, MOD-12 counter using JK flip-flop and verify its truth
table. (100)

14. Design a serial in serial out , serial in parallel out & parallel in parallel out shift register
and verify its truth table. (100)
15. Design the binary adder & subtractor using IC 7483 & find the output for the
following inputs. (100)
Adder : (i) 1110 + 1010
(ii) 0001 +1100
Subtractor : (i) 1000 - 1010
(ii) 1001- 0101

16. Design 4:1 MUX & 1:4 DEMUX using logic gates and verify its truth table. (100)

17. Construct a Class-A, Class-B power amplifier and determine the efficiency. (100)
.

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