724 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO.

3, MARCH 2013

A PushPull Class-C CMOS VCO

Andrea Mazzanti, Member, IEEE, and Pietro Andreani, Senior Member, IEEE

AbstractA CMOS oscillator employing differential transistor

pairs working in Class-C in pushpull configuration is presented.
The oscillator exhibits the same advantages enjoyed by comple-
mentary topologies on oscillators based on a single differential pair,
while yielding a substantial power consumption reduction thanks
to the Class-C operation. The phase-noise performance and the
fundamental conditions required to keep the transistors working in
Class-C are analyzed in detail. It is shown that, for an optimal per-
formance, both nMOS and pMOS transistors should not be pushed
into the deep triode region by the instantaneous resonator voltage,
and a simple circuit solution is proposed to accommodate a large
oscillation swing. A 0.18- m CMOS prototype of the (voltage-con-
trolled) oscillator displays an oscillation frequency from 6.09 to
7.50 GHz. The phase noise at 2-MHz offset is below 120 dBc/Hz
Fig. 1. (a) Original Class-C oscillator. (b) Pushpull Class-C oscillator.
with a power dissipation of 2.2 mW, for a state-of-the-art figure-of-
merit ranging from 189 to 191 dBc/Hz.
Index TermsClass-C, CMOS, phase noise, pushpull, voltage
controlled oscillator (VCO). the resonator (resulting from a small current conduction angle
of the transistors) leading to a high conversion efficiency of
the dc current into the fundamental harmonic current. For the
I. INTRODUCTION same dc current, the theoretical phase-noise improvement com-
pared with the standard differential-pair LC-tank oscillator is
3.9 dB; for the same power supply voltage, on the other hand,
T HE voltage-controlled oscillator (VCO) is a key building
block in high performance wireless and wireline commu-
nication systems. VCO research is steadily attracting a great in-
the Class-C oscillator ideally allows a 36% current saving for
the same (minimum) phase-noise level. Since its first introduc-
tion, the Class-C oscillator has gained an increasing popularity,
terest, leading to a proliferation of different topologies aimed
and several applications and improvements have been proposed
at improving frequency tuning range and phase noise [1][13].
in the recent literature [16][23]. All of the realizations pre-
The latter in particular deserves attention, since it determines the
sented so far are nevertheless based on a single differential pair
power consumption requirements. It has been rigorously proved
configuration, similar to the original topology in Fig. 1(a).
that the contribution of the thermal noise of the core transistors
This paper introduces a push-pull Class-C oscillator, shown
to phase noise in a generic harmonic oscillator does not, to the
in Fig. 1(b). While still preserving the superior dc-to-RF cur-
first order, depend on the transconductance of the core transis-
rent conversion efficiency of transistors working in Class-C and
tors [14], [15]; thus, although technology scaling does reduce
the same maximum theoretical phase noise figure of merit of
losses in switched-capacitor frequency tuning (which is partic-
the original Class-C VCO, the circuit displays the same advan-
ularly important for applications with a large tuning range), it
tages that, in some cases, make a complementary LC-tank os-
does not otherwise improve significantly the VCO spectral pu-
cillator (employing both nMOS and pMOS switching transis-
rity. The VCO power consumption is therefore becoming more
tors) preferable to a single differential pair oscillator [24][27].
and more dominant, compared with other system blocks directly
These advantages can be summarized as follows: 1) twice the
benefiting from technology scaling, and techniques to improve
tank voltage swing and 6-dB improvement of phase noise for
the VCO power budget without deteriorating its phase noise are
the same current consumption and resonator, provided the oscil-
of the greatest interest. Among different solutions, the Class-C
lator is working in the current-limited regime1; 2) a larger loop
oscillator of Fig. 1(a) has been proposed [14]. In this harmonic
gain due to the contribution of both nMOS and pMOS transcon-
oscillator, active devices deliver short and tall current pulses to
ductance; and 3) a voltage swing always within the supply rail,
avoiding reliability issues.
Manuscript received July 27, 2012; revised October 01, 2012; accepted
A 0.18- m CMOS test chip has been realized. Drawing
November 05, 2012. Date of publication December 20, 2012; date of current
version February 20, 2013. This paper was approved by Associate Editor 1.2 mA from a 1.8-V supply, the pushpull Class-C VCO is
Woogeun Rhee. tunable from 6.09 to 7.50 GHz, with a phase noise at 2-MHz
A. Mazzanti is with the Universit di Pavia, Dipartimento di Ingegneria
Industriale e dellInformazione, 27100 Pavia, Italy (e-mail: andrea.maz- 1Complementary oscillators do not improve the phase noise figure of merit,
zanti@unipv.it). compared to single-differential-pair oscillators. In fact, the maximum allowed
P. Andreani is with Department of Electrical and Information Technology, voltage swing in complementary oscillators to operate in the current-limited re-
Lund University, SE-221 00 Lund, Sweden (e-mail: piero@eit.lth.se). gion is one half that in single-differential-pair oscillators, leading to the same
Color versions of one or more of the figures in this paper are available online optimal phase noise normalized to power dissipation. This result has been de-
at http://ieeexplore.ieee.org. rived in [27] and exploited in [26] for the traditional differential pair oscillator
Digital Object Identifier 10.1109/JSSC.2012.2230542 topologies.

0018-9200/$31.00 2012 IEEE

MAZZANTI AND ANDREANI: PUSHPULL CLASS-C CMOS VCO 725

offset from the carrier better than 120 dBc/Hz. Despite

the moderate overall tank quality factor of approximately
10, the oscillator displays a remarkable peak phase noise
figure-of-merit (FoM) of 191 dBc/Hz.
The paper is organized as follows. Section II reviews the prin-
ciple of operation of the Class-C oscillator and introduces the
theoretical framework for the push-pull configuration. A large
signal analysis of the circuit is carried out, deriving the condi-
tions under which short current pulses and high DC-to-RF con-
version efficiency is preserved in the complementary topology.
Section III analyzes the phase noise of the push-pull oscillator
and discusses non-ideal effects that should be considered to
Fig. 2. Current and voltage waveforms in the pushpull Class-C oscillator. (a)
avoid unwanted phase noise degradation. Section IV presents a First half and (b) second half of the oscillation period.
modification of the push-pull Class-C oscillator, able to accom-
modate a large voltage swing without phase noise penalty, as
well as a comparison with the standard complementary CMOS where is the tank common-mode dc voltage and
oscillator. The design and experimental results of a circuit pro- , where is the angular frequency of oscillation. Assuming
totype are presented in Section V, while Conclusions follow. a moderately large resonator quality factor, the differential tank
voltage can be approximated as a sinusoid with amplitude2
II. LARGE SIGNAL ANALYSIS
as
The large-signal operation of the pushpull Class-C oscillator
is presented in this section, deriving the conditions required to
preserve a highly efficient pulsed tank current. The fundamental (2)
difference between the standard differential-pair LC-tank oscil-
lator and the Class-C LC-tank oscillator in Fig. 1(a) is the rela- We assume that the transistors do not leave the saturation region,
tively large capacitance ( ) connected between the common i.e., a suitably low is selected for the nMOS transistors,
source node of the nMOS transistor pair and ground. keeps while the following condition holds for the pMOS transistors:
the voltage of the common source node (almost) constant.
As a result, the nMOS devices are active (i.e., they conduct cur- (3)
rent) only when (where are the gate
voltages of the two transistors of the differential pair and where is the pMOS threshold voltage. Looking at
is the nMOS threshold voltage), a condition occurring over a Fig. 2(a), in the first half of the oscillation cycle when and
small fraction of the oscillation period. The tank current is then are conducting, the drain currents are
made of short and tall current pulses with a fundamental com-
ponent roughly equal to , i.e., 3.9 dB larger than in the case
without , where transistors are active for half the oscilla-
tion period and the tank current resembles very closely a square (4a)
wave with a fundamental component of . As discussed
thoroughly in [14], to preserve the pulsed current shape, it is (4b)
very important that the nMOS transistors do not enter the triode
region. Therefore, to maximize the allowed tank voltage swing, where and (where
an RC network is introduced to provide a bias voltage to the is the electron/hole mobility, is the gate-oxide ca-
gates ( ) lower than the tank common-mode voltage. pacitance per unit area, and and are the transistor width
Turning to the complementary topology in Fig. 1(b), the and length, respectively), while and
nMOS transistors deliver current pulses to the differential tank, (where is the gatesource
and the same pulses flow through the cross-coupled pMOS pair. voltage of the n/pMOS transistor) are the average overdrive
Under steady-state conditions, the voltage waveform across the voltages in steady state for the nMOS and pMOS transistors,
tank settles so that opposite nMOS and pMOS transistors have respectively.
exactly the same conduction angle and current shape. The tank From (1) and (2), . Re-
voltages, transistor conduction angle, and current shape are placing the latter in (4b) and solving leads to
then determined by the aspect ratios of both nMOS and pMOS
transistors. To gain insight, Fig. 2 highlights the transistors
conducting current in the two half-cycles of one oscillation
(5)
period. The single-ended tank voltages can be written as
2The adopted notation here is different from [14]. The pushpull Class-C os-

(1a) cillator has a single differential tank while the resonator of the single-differential
pair Class-C oscillator in [14] is made of two single-ended tanks. The amplitude
(1b) calculated in [14] is for one of the two tanks.
726
Fig. 3. Voltage and current waveforms in the pushpull Class-C oscillator with
transistors working always in saturation (solid curves) and with pMOS transis-
tors entering deeply into the triode region (dotted curves).
Interestingly, if nMOS and pMOS transistors have different
gains (i.e., ), the peak values of the tank voltages
expressed by (6) are different. For symmetry, the analysis of
the circuit in the second half of the oscillation period, i.e., for
, when and are active, as depicted in
Fig. 2(b), leads to tank voltages with opposite magnitude as
The above analysis has been checked by means of circuit sim-
ulations reported in Fig. 3. The continuous lines represent the
tank voltages (top plot) and the MOS currents (bottom plot) for a
design where 0.9 V, 1.2 mA, and
The supply voltage is adjusted for a steady-state common-mode
tank voltage 1 V, and the threshold of the pMOS tran-
sistors has been artificially increased to 1 V by means of a dc
voltage source in series with the pMOS gates to avoid triode
operation. The simulated tank voltages are in very good agree-
ment with (6) and (7) and the difference between positive and
negative peaks, due to the different gains of pMOS and nMOS
transistors, is clearly evident. The origin of this asymmetry finds
also a very intuitive explanation. Since the circuit forces the
same current in opposite nMOS and pMOS transistors, different
voltage amplitudes are required to compensate for the different
transistor gains. Focusing for example on the first half of the os-
cillation period, since the nMOS has more gain than the pMOS
transistor ( ), the voltage driving the nMOS
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 3, MARCH 2013
Fig. 4. Simulated current conversion efficiency when the pMOS transistors
enter the triode region, for different transistors gains.
transistor is lower (in magnitude) than the voltage driving
the pMOS transistor. In the second half of the period, the situa-
tion is reversed.
The device conduction angle ( ) and the fundamental com-
ponent of the drain current ( ) can be derived from (4)(6)
following the same approach presented in [28] for the analysis
of the CMOS Colpitts oscillator, leading to
(6a)
(8)
(6b)
(9)
An analysis of the circuit if the pMOS transistors enter the triode
region is much more involved, and does not lead to simple
closed-form equations. The intuitive view discussed above is
nevertheless still useful to explain the behavior in this case. The
results of a simulation with 0.25 V are shown with
the dotted lines in Fig. 3. The gain of the pMOS transistors is
now much lower, since they operate in triode for most of the
time, but the drain current shape must still match the drain cur-
rent of the opposite nMOS transistors. As a result, the ampli-
tude of the tank voltage driving the nMOS transistors (i.e.,
and in the first and second half of the period respectively)
(7)
drops significantly. As shown by the bottom plots in Fig. 3,
the conduction angle of the devices increases and the drain cur-
rent pulses are widened, losing the high dc-to-RF conversion
efficiency of the narrow pulses. To gain further insight, Fig. 4
plots the simulated magnitude of the fundamental component of
the drain current normalized to the bias current (i.e., )
.
versus for different gain factors of the transistors. For
, the pMOS transistors do not leave the saturation
region, while for they enter gradually into the
triode region; the lower , the larger the fraction of the
oscillation period with pMOS transistors in triode. The current
conduction angle increases with decreasing , gradu-
ally losing the high dc-to-RF conversion efficiency. In the limit
case of , the conduction angle is approximately
and , which is the same as in the standard
complementary CMOS oscillator.
III. PHASE NOISE
Following the linear time-variant (LTV) analysis approach
proposed by Hajimiry and Lee, the phase noise of a generic
MAZZANTI AND ANDREANI: PUSHPULL CLASS-C CMOS VCO
harmonic oscillator at an offset frequency from the carrier
can be expressed as [8], [29], [30]
(10)
where is the oscillation amplitude across the resonator, al-
ready introduced in (2), is the tank capacitance, and, for white
noise sources, (simply referred to as effective noise here-
after) is given by
(11)
where is the oscillation period, is the white current
noise power spectral density (either stationary or cyclo-sta-
tionary) produced by the th device, and is the corre-
sponding impulse sensitivity function (ISF), encoding the
time-dependent sensitivity of the phase of the oscillation to
. It has been shown that the ISF of the noise current
source associated with the tank loss resistance is, with very
good approximation, a sinusoid in quadrature with the tank
voltage and with a magnitude inversely proportional to the
number of resonators in the oscillator [31]. Since we have
assumed a sinusoidal tank voltage with zero initial phase [see
(2)] and the oscillator in Fig. 1(b) comprises a single resonator,
the tank ISF is . The stationary current
noise power spectral density of the tank loss resistance ( )
is (where and are the Boltzmans
constant and the absolute temperature, respectively) and the
tank effective noise follows immediately by calculating
the integral of (11) to yield
(12)
To calculate the effective noise produced by the thermal noise
of nMOS and pMOS pairs, we can exploit the powerful general
property of phase noise in harmonic oscillators presented in [14]
and [32]. In particular, it has been proved that, if the core tran-
sistors do not leave the active (saturation) region, their effective
noise is independent of transistor type, size, and shape of the
drain current, but depends only on the oscillator topology and
can be related to the tank effective noise by means of the fol-
lowing equation:
(13)
where is the proportionality constant linking the transistors
thermal noise to their transconductance, is the ratio between
the voltage swing at the output of the active pair to the oscilla-
tion amplitude across the tank, and is the ratio between the
voltage swing driving each active pair to the tank voltage. In
the pushpull oscillator of Fig. 1(b), there are two distinct dif-
ferential pairs driving the resonator. Obviously, because
the differential output of each pair is directly connected to the
tank. On the other hand, the use of two complementary active
pairs leads to a feedback oscillation amplitude across each pair
727
that is twice the amplitude that would be available with a single
differential pair, yielding .
The effective noise contributed by each active pair is there-
fore
(14)
The contribution to phase noise of the tail current source is quite
negligible, since its white noise is almost totally filtered out by
the large tail capacitance required for Class-C operation. This
is a further significant advantage of the Class-C oscillator com-
pared to the traditional differential pair topology, where the con-
tribution of the biasing transistor to phase noise is in general
non-negligible [12], [28].
Finally, the oscillation amplitude is given by the product
of the tank resistance and the fundamental current component,
, which is the sum of the nMOS and pMOS currents, i.e.,
twice the current given by (9),
(15)
Substituting (12), (14), and (15) into (10), the closed-form
phase-noise expression for the pushpull Class-C oscillator is
(16)
The results of the phase-noise analysis have been compared
against Spectre-RF simulations for a design example where we
have assumed a tank inductance of 1 nH with a quality factor
, 600 fF, 1.2 mA. The oscillation fre-
quency is 6.5 GHz. The bias voltage for the nMOS transis-
tors has been selected to avoid their entering the triode region.
The simulated oscillation amplitude, effective noise contribu-
tions and phase noise at 2 MHz offset from the carrier are re-
ported in Table I for different values of . The effective
noise contributions predicted by (12) and (14) are
10 A Hz and, assuming , we obtain
A
Hz
The calculated phase noise by (16) is 125.3 dBc/Hz. These re-
sults are in very good agreement with simulations, reported in
the first row of Table I, for , i.e., with pMOS tran-
sistors not leaving the saturation region. The small discrepancy
( 1 dB) between calculated and simulated phase noise is due
to the approximation in (9), which leads to a slight
overestimation of the oscillation amplitude in (15). In particular,
the calculated is 990 mV, which is 1 dB higher than the
simulated value of 890 mV.
More interestingly, these simulations point out a gradual de-
terioration of phase noise if the pMOS transistors are allowed
to enter the triode region, rising up to 7 dB in the limit case of
. The reason is twofold: 1) the reduction of the os-
cillation amplitude, reported in Table I, which is due to the much
lower DC-to-RF current conversion efficiency, as discussed in
the previous section, and 2) a significant increase, of more than
four times, of the effective noise generated by the transistors. It
728 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 3, MARCH 2013

TABLE I
SIMULATED OSCILLATION AMPLITUDE, NOISE CONTRIBUTIONS, AND PHASE
NOISE OF THE PUSHPULL CLASS-C OSCILLATOR FOR DIFFERENT VALUES
OF

is worth noticing the proportional increase of both nMOS and Fig. 5. Pushpull Class-C oscillator modified to accommodate a large voltage
pMOS contributions, even if the former never leave the satura- swing.
tion region. The primary mechanism behind the increased con-
tribution of transistors effective noise is the larger current con-
duction angle, when pMOS transistors enter the triode region, as waveforms depicted in Fig. 5. During the first half of the os-
previously shown in Fig. 3. As a result, both nMOS and pMOS cillation cycle, transistors and are pushed toward the
transistors inject thermal noise into the tank over a wider frac- triode region. The boundary condition for saturation of ,
tion of the oscillation period, leading to a larger integral noise , can be written as
expressed by (11). , where and are the peak voltage
We have focused our attention on the transistors of the pMOS magnitudes at the two tank nodes in the first half of the oscilla-
pair, but the same discussion, with similar qualitative results, is tion cycle, as shown in Fig. 5. Given the differential oscillation
also valid for the transistors of the nMOS pair. For an optimal amplitude , the minimum required to
phase-noise performance, it is therefore very important to avoid keep in saturation is
any transistors entering the deep triode region.
(17)
IV. PUSHPULL CLASS-C OSCILLATOR FOR
Looking now at , the saturation condition
LARGE VOLTAGE SWING
requires . Assuming the
To avoid excessive phase noise penalty, the zero-peak differ- external bias voltage for the nMOS pair is selected at the min-
ential voltage swing across the resonator must be comparable imum possible value, i.e., ,
or lower than a pMOS threshold voltage. While this limitation where is the minimum voltage to keep the tail current
can be acceptable in ultrascaled technologies having a supply source in saturation), the upper bound for the tank voltage swing
voltage of 1 V with 0.50.6-V high- transistor options, it is:
represents a significant penalty for realizations in less scaled
technology nodes. A modified pushpull Class-C oscillator ac- (18)
commodating a larger voltage swing is presented in Fig. 5. An
additional RC network is introduced to provide a dc bias voltage The tank steady-state dc common-mode voltage is set by the
for the gates of the pMOS pair ( ) higher than the tank pMOS pair and the level shifter
common-mode voltage, allowing a larger resonator swing be-
(19)
fore the pMOS pair is pushed into the triode region. This is the
same technique adopted to bias the nMOS pair, with the differ- Assuming is selected at the optimal value given by (17),
ence that is not applied externally, but is generated by and replacing (19) in (18), the constraint on the maximum tank
offsetting upward the tank common-mode voltage, , by voltage swing to ensure transistors do not enter the triode region
, with transistor working as level shifter. This is nec- is
essary to preserve a low common-mode tank impedance and a
well-defined common-mode voltage. The power required to bias
the level shifter is negligible, compared with the overall dissi-
pation in the oscillator. (20)
By selecting a moderately high time constant for the RC bi-
asing networks, the noise impressed on and the noise The absolute value of and is introduced in the last
generated by the level shifter providing are low-pass fil- expression to highlight that the steady-state overdrive voltage of
tered and do not deteriorate the oscillator phase noise. nMOS (pMOS) transistors working in Class-C is negative (pos-
itive). For practical transistor sizes, the magnitude of the over-
A. Maximum Oscillation Amplitude drives is in the range of 50100 mV. The tail current source
To estimate the optimal design value for and the max- transistor in the Class-C oscillator can be sized very large, since
imum allowed oscillation amplitude, we refer to the voltage its drain parasitic capacitance is absorbed in . The required
MAZZANTI AND ANDREANI: PUSHPULL CLASS-C CMOS VCO
minimum drain voltage for saturation ( ) is therefore of
the order of 100 mV or even less, leading to a maximum tank
voltage swing, from (20), which is roughly half of the supply
voltage.3 This is nevertheless quite a pessimistic estimate. In
fact, in deep-submicron technologies, the velocity saturation of
the charge carriers prevails on the channel pinch-off to deter-
mine saturation of the drain current, and a magnitude of
lower than what has been assumed in the above derivation is
therefore sufficient to keep the transistors in the active region.
B. Comparison With the Standard Complementary
Differential-Pairs CMOS Oscillator
The maximum theoretical oscillation amplitude for the stan-
dard LC-tank oscillator with complementary differential pairs
is - [27]. Thus, this oscillator theoretically allows
a larger maximum amplitude than the pushpull Class-C os-
cillator of Fig. 5. However, it should be noticed that, unlike
in the Class-C oscillator, cannot be selected below
a few hundred millivolts, because the tail-current-source tran-
sistor must be designed with a relatively small aspect ratio and a
correspondingly large overdrive voltage to yield a low transcon-
ductance, since its high-frequency thermal noise (proportional
to its transconductance) is not filtered out, impacting the os-
cillator phase noise [28]. Furthermore, the noise from the
tail-current-source transistor is an issue as well [12].
The phase noise of the standard complementary oscillator is
also severely impaired by capacitors connected single-ended
to the resonator, i.e., capacitors connected between the differ-
ential outputs and ground [15], [27]. Assuming a tail-biased
standard complementary oscillator topology, at large oscilla-
tion amplitude the on-resistance of the pMOS transistors, en-
tering the triode region, appears in parallel to the single ended
tank capacitors, thus degrading the loaded tank and there-
fore phase noise. In a typical design, this mechanism leads to a
significant phase noise penalty if the single-ended capacitance
is a non-negligible fraction of the total tank capacitance [27]
(and up to 10-dB penalty in the case of 100% single-ended
tank capacitance [15]). This issue leads to a severe tradeoff be-
tween frequency tuning range and phase noise, since the com-
ponents mostly responsible for introducing single-ended tank
capacitances are the varactors in the case of continuous fre-
quency tuning, and, if a switched-capacitor bank is used for dis-
crete tuning, the parasitic capacitances of the switches [7]. How-
ever, since the core transistors of a correctly designed pushpull
Class-C oscillator never leave the saturation region, its pMOS
transistors cannot discharge the single-ended parasitic capaci-
tances, allowing a large frequency tuning range without a sig-
nificant phase-noise penalty.
In summary, even if the maximum oscillation amplitude
for the standard complementary differential-pair oscillator is
theoretically larger than for the Class-C oscillator, the higher
dc-to-RF current conversion efficiency, the use of a large
explicit capacitance at the common-source node, allowing a
very low and filtering-out the bias current noise, and
3The maximum tank voltage swing of the pushpull Class-C oscillator is half
that of the originally reported Class-C oscillator based on a single differential
pair [14]. Following the same analysis reported in [27], the two oscillators have
the same maximum phase noise FoM.
729
the robustness against single-ended tank capacitance, lead to
a significant improvement of the spectral purity for a given
power dissipation in favor of the Class-C oscillator. This will
be also evident from the comparison of experimental results
against the performances of recently reported complementary
LC-tank oscillators, presented in Section V.
V. EXPERIMENTAL RESULTS
A VCO based on the large-swing Class-C topology of Fig. 5
has been designed in 0.18- m CMOS. To keep a low VCO
gain, the tank capacitance is made of a small varactor for fine
tuning and a bank of four digitally switched and binary-sized
metal-fringe capacitors for coarse tuning. The 1-nH inductor is
a two-turn coil, and the estimated tank is 10. From (20), the
optimal oscillation amplitude is approximately half of the
supply voltage. Given a nominal supply of 1.8 V, the biasing
current is set to 1.2 mA, leading to a simulated of
900 mV. The aspect ratio of the nMOS ( - ) and pMOS
( - ) core transistors is, respectively, 42 m/0.18 m and
60 m/0.18 m. Transistor is 15 m/0.2 m and is biased
close to the threshold voltage with a 10- A current, providing
a voltage shift of 470 mV. The VCO drives directly a pair
of open-drain buffers, supplied off-chip with bias-tees, to drive
the 50- impedance of the measurement setup.
The tail current source is realized with a transistor
having an aspect ratio of 500 m/0.8 m. A nonminimum
channel length is selected to limit the generation of
noise, which would be (at least partially) translated into
phase noise. At the same time, the very large width leads
to a minimum drain voltage for saturation, of only
80 mV. The total tail capacitance , comprising the parasitic
drain junction capacitance of the tail transistor and an explicit
metal-fringe capacitance, is 1.1 pF. This value is sufficiently
large to keep an almost constant steady-state tail voltage, the
fundamental condition for Class-C operation of the core tran-
sistors. On the other hand, similar to the single-differential-pair
Class-C oscillator, too large a tail capacitance would lead to an
instability of the oscillation amplitude, a phenomenon referred
to as squegging [14]. Simulations indicate that squegging
appears for 1.7 pF, indicating a sufficiently safe sta-
bility margin with 1.1 pF. No squegging is observed
in measurements.
Fig. 6 shows the chip photograph. The die area, including
pads, is 650 m 430 m. Fig. 7 shows the tuning curves. The
VCO is tunable from 6.09 to 7.50 GHz in 16 widely overlapping
bands. The maximum gain, at the center of the tuning curves,
ranges from 110 to 164 MHz/V.
Phase-noise measurements are carried out with 1.8 V
and a current consumption of 1.2 mA, corresponding to a power
dissipation of 2.16 mW. Fig. 8 shows a typical phase-noise plot.
The bias voltage for the nMOS pair , provided off-chip,
is set to a nominal value of 0.65 V. This value, which is slightly
higher than the optimal minimum value calculated in the pre-
vious section, sets a small-signal device transconductance suffi-
ciently large to ensure a robust oscillator start-up. On the other
hand, as it has been discussed in [14] for the single-differential-
pair Class-C oscillator, the sensitivity of phase noise to
730
Fig. 6. Chip photograph.
Fig. 7. Tuning curves of the pushpull Class-C VCO.
is very low and no appreciable phase noise variations are ob-
served for ranging from 0.6 to 0.7 V. Eventually, a ded-
icated start-up circuit, as proposed recently for the single-dif-
ferential-pair Class-C oscillator, may be adopted to further op-
timize the design [19][23].
The measured phase noise at different offset frequen-
cies, in each subband of the VCO, is compared with sim-
ulations in Fig. 9. The measured phase noise at 200-kHz,
2-MHz, and 20-MHz offsets ranges, respectively, from 97.5
to 101 dBc/Hz, 120 to 123 dBc/Hz, and 140.3 to
143.4 dBc/Hz. The phase noise corner is slightly
larger than expected, as visible in Fig. 9 by the larger dis-
crepancy between measurements and simulations at 200-kHz
offset, where noise is dominant. Possibly, this is caused
by wanting device noise models. The smaller discrep-
ancy between measurements and simulations in the
region, at 2-MHz and 20-MHz offsets, is likely due to a
slight overestimation of the tank quality factor. The FoM
normalizing oscillation frequency ( ), power dissipa-
tion ( ), and phase noise at the offset frequency , the rather old technology used.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 3, MARCH 2013
Fig. 8. Measured phase-noise plot.
Fig. 9. Simulated (continuous line) and measured (dots) phase noise at
200-kHz, 2-MHz, and 20-MHz offset from the carrier in each subband of the
pushpull Class-C VCO.
, cal-
culated at 2 MHz or 20 MHz, ranges from 189 to
191 dBc/Hz across the tuning range.
Finally, measurement results are summarized and compared
with recently reported complementary oscillators (i.e., oscil-
lators employing both nMOS and pMOS transistor pairs) fea-
turing a tuning range of more than 10% in Table II. The designs
in [26] and [33] are standard complementary oscillators with a
pMOS top biasing current source. In [34], a filtering technique
for the bias noise employing an additional inductor is used. In
[35] the tail transistor is removed, while in [36] it is replaced by
a pair of parallel LC resonators. The best peak phase-noise FoM,
among all realizations, is 187 dBc/Hz. On average, the FoM of
the Class-C complementary topology is more than 3 dB higher,
meaning that, for the same oscillation frequency and phase noise
target, the proposed solution saves more than half of the power.
Yet another popular (albeit somewhat arbitrary) figure-of-
merit takes into account the tuning range TR as well, and is
defined as , where is ex-
pressed in percent. Also in this case the push-pull Class-C VCO
compares well with the state-of-the-art (see Table II again),
especially if we consider the high frequency of operation and
MAZZANTI AND ANDREANI: PUSHPULL CLASS-C CMOS VCO
TABLE II
PERFORMANCE SUMMARY AND COMPARISON WITH RECENTLY REPORTED CMOS VCOS EMPLOYING COMPLEMENTARY DIFFERENTIAL PAIRS
VI. CONCLUSION
Complementary VCOs are preferable, in some circum-
stances, to topologies employing a single differential pair. A
Class-C VCO adopting CMOS differential pairs in a pushpull
configuration has been introduced and analyzed, providing
insight on circuit operation and phase noise. It has been shown
that, for an optimal phase noise performance, transistors must
not leave the saturation region. A simple technique, requiring
negligible additional dissipation, has been proposed to accom-
modate large voltage swing. As confirmed by experimental
results, thanks to the high dc-to-RF current conversion effi-
ciency and the large tail capacitance, explicitly required for
Class-C operation, which filters out the bias noise, the proposed
VCO displays an improved phase-noise performance compared
with the widely adopted standard topology of the complemen-
tary differential-pair oscillator.
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Andrea Mazzanti (M09) received the Laurea and
Ph.D. degrees in electrical engineering from the Uni-
versit di Modena and Reggio Emilia, Modena, Italy,
in 2001 and 2005, respectively.
During the summer of 2003, he was with Agere
Systems, Allentown, PA as an Intern. From 2006
to 2009, he was an Assistant Professor with the
Universit di Modena and Reggio Emilia, Modena,
Italy, where he taught a course on advanced analog
IC design. In January 2010, he joined the Universit
di Pavia, Pavia, Italy. He has authored or coauthored
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 3, MARCH 2013
over 50 technical papers. His main research interests cover device modeling
and IC design for high-speed communications and millimeter-wave systems.
Dr. Mazzanti has been a member of the Technical Program Committee of the
IEEE Custom Integrated Circuit Conference (CICC) and the IEEE International
Conference on IC Design and Technology (ICICDT) since 2008. He is currently
serving as an associate editor for the IEEE TRANSACTIONS ON CIRCUITS AND
SYSTEMSI: REGULAR PAPERS.
Pietro Andreani (SM07) received the M.S.E.E. de-
gree from the University of Pisa, Pisa, Italy, in 1988,
and the Ph.D. degree from Lund University, Lund,
Sweden, in 1999.
Between 2001 and 2007, he was Chair Professor
with the Center for Physical Electronics, Tech-
nical University of Denmark. Since 2007, he has
been an Associate Professor with the Department
of Electrical and Information Technology, Lund
University, Lund, Sweden, where he is involved
with analog/mixed-mode/RF IC design. He is also a
part-time IC Designer with ST-Ericsson, Lund.
Prof. Andreani has been a TPC member of ISSCC (20072012) and is a TPC
member of ESSCIRC.