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Differential voltage mode Sense amplifier with

Current mirror load as receiver for on-chip

Interconnect Serial links
T.Gvardhana rao1, M.Bhaskar2, B.Venkataramani3
M.Tech1-student, Sr.Lecturer 2, Professor 3
Department of Electronics and Communications Engineering
National Institute of Technology-Trichy
Trichy, INDIA.

Abstract— In the literature, differential voltage multiplexed and it consumes more area and power. Input
mode and current mode sense amplifiers are proposed for multiplexed transmitter architecture is proposed for off-chip
global interconnects in high speed serial link transceivers. interconnects in [6].
In serial links operating at data rates greater than 4Gbps, For receivers, voltage mode sense amplifiers have
the signal swing becomes inadequate for sensing for been proposed in [7&10]. A differential input stage is used in
interconnects longer than 5 mm or the capacitive load is the sense amplifiers. However at high data rate the signal
greater than 25fF. In this paper, a differential voltage swing becomes inadequate for sensing. Current mode sense
mode sense amplifier with current mirror load is proposed amplifiers proposed in [8] can operate at higher data rates
to overcome these limitations. because of their low input impedance. However, the current
The proposed receiver is implemented in TSMC sense amplifier may settle in meta-stable state which may
180nm technology and the performance is studied through prevent the recovery of the signal. Their drive capability may
simulations. An interconnect in M4 layer of length 7 mm also be less for loads greater than 10fF at higher data rates
and thickness of 0.525 µm is assumed for simulations (>4Gbps). To overcome these problems, a receiver with
before the receiver. differential voltage sense amplifier is proposed in this paper.
From the simulations, it is observed that the The organization of the paper is as follows. In section
differential voltage sense amplifier proposed in this paper II, the operation and simulation results of both current mode
has increased signal swing at the output of the receiver sense amplifier and the differential voltage sense amplifier are
from 20mV to 1.2V at 4Gbps data rate at the cost of 10 presented Section III shows the performance comparisons of
times increase in power. receivers and repeater insertion technique Section IV presents
the conclusions.

As VLSI technology progresses into the nanometer 1) Differential current Sense Amplifier
regime, interconnects play an important role in determining
the overall performance and power consumption of high speed The differential current sense amplifier used as
chips. The global interconnects are not scaled in dimension as receiver is shown in figure – 1, it consists of a common gate
compared to transistors. Because of this, the capacitance of configuration as an input stage; a pair of cross coupled
interconnects and resistance per unit length increase [1]. inverters and SR NAND Latch. Common gate configuration
Hence, the RC delay of interconnects play a significant role in has low input impedance, which minimizes the charging and
chip design and limits the high speed operations. discharging times of the capacitance at the input node of sense
In order to reduce the delay, several circuit amplifier hence it leads to less delay. This low input
techniques and signaling schemes have been proposed in the impedance acts as the termination resistor for the transmission
literature. Repeater insertion is one of the techniques to line model of interconnects.
change the delay dependence on wire length from quadratic to . Transistors M1 and M2 form the low impedance
linear [2&3]. But for long wires, the number of repeaters front end stage. Transistors M3-M6 forms the cross coupled
required is more and it suffers from placement problems. inverter pair. M7&M8, M9&M10 are pre-charge and isolation
The repeater less interconnects is reported in transistors shown in Figure 1. Isolation transistors are used to
literature [4], where the inductive behaviour is maximized and isolate the inputs from the sensing nodes of cross coupled
high data rates are achieved in on-chip interconnects. Narrow inverters during the falling edge of the clock.
current pulses are used to maximize the inductive behaviour The operation of the circuit is as follows: On the falling
using output multiplexed driver architecture [5]. The output edge of the clock, outputs are pre-charged to VDD through M7
multiplexed technique requires driver for each input to be & M8. M9 & M10 are switched OFF to isolate the inputs from
the sensing nodes. During the rising edge of the clock M9 & 2) Differential Voltage Sense Amplifier with Current
M10 are turned ON, which connects the inputs to the sensing Mirror Load
nodes. Both output nodes start to discharge but one is faster
than the other. Regenerative action takes place in the cross In order to understand the advantages of using
coupled inverters, when a small difference exists between the receiver than repeaters we have simulated the design by
two outputs. One output reaches LOW, while the other output inserting repeaters at regular intervals of metallic wire and we
reaches HIGH. The output of sense amplifier latched to the compared that with using receivers in various aspects.
output by SR NAND Latch. Differential amplifier with single ended conversion
with current mirror load is used to sense very low signals of
1mv whose gain is approximately 8.It has a bandwidth of
8GBPS for receiver alone, and the de-multiplexer circuit is
used to parallelize the serial data. The bandwidth can be
improved by loosing power by mirroring more current at the
output. So the circuit for differential amplifier is shown as
below figure 4

Figure 1 Current mode sense amplifier

Figure 4 Differential voltage sense amplifier

with current mirror load

Figure Differential voltage amplifier

Figure 2 Load versus delay for current

sense amplifier.

Figure 5 Load versus delay of differential

voltage sense amplifier



Figure 3 Current sense amplifier output wave forms Figure 6 Differential amplifier output wave form
at 4Gbps at 4GBPS
A) Delay [1] R.Ho, K.W.Mai and M.A.Horowitz, “Thefutureofwires”,
By using receiver at the end of far interconnect we can reduce Proc.IEEE,vol. 89,no. 4, pp.490-504, Apr.2001.
delay by 60% of that obtained by using repeaters. Because [2] H.B. Bakoglu, J.D. Meindl, “Optimal interconnection
regular insertion of repeater change the delay from quadratic circuits for VLSI”, IEEE Trans. Electron Devices ED-32 (5),
to linear dependence of wire length, but the repeater itself add 1985, pp. 903–909.
delay to the path, so it is advisable to use differential [3] C.J. Alpert, A. Devgan, J.P. Fishburn, S.T. Quay,
transmission and differential reception compared with repeater “Interconnect synthesis without wire tapering”, IEEE Trans.
insertion. Computer-Aided Design Integrated Circuits and Systems, 20
B) Power and area (1), 2001, pp. 90–104.
Like delay power consumed by the receiver also reduced [4] R. T. Chang, N. Talwalkar, C. P. Yue, and S.
because strong repeaters dissipate lot of power. But the S.Wong,“Near speed of light signaling over on-chip electrical
receiver consumes very less or moderate power compared to interconnects,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp.
repeaters. Area occupied by receiver is also less compared to 834–838, May 2003.
repeaters. Receiver consumes power comparable to a single [5] A. P. Jose, G. Patounakis, and K. L. Shepard, "Pulsed
strong repeater. current-mode Signaling for nearly speed-of-light intrachip
c) Process variation and mismatch communication," Solid-State Circuits, IEEE Journal of, vol.
The effect of process variations also effects delay depends on 41, pp. 772-780, Apri 2006.
number of transistors. If we use repeaters the delay varies by [6] Ming-Ju Edward Lee, William J. Dally, and Patrick
20%, where as receiver gets affected by 2%-4%. The delay Chiang, “Low-Power Area-Efficient High-Speed I/O Circuit
due to process variations depends on the proportion of number Techniques” IEEE Journal of Solid State Circuits.Vol.35.
of transistors. No.11. November 2000
[7] P. Wijetunga and A. F. J. Levi, “3.3 GHz Sense-amplifier
in 0.18μm CMOS Technology,” Advanced Interconnect and
Table- 1 Power consumption for various receiver circuits Network Technology, USC, IEEE pp.764-765, 2002.
[8] Atul Maheshwari, and Wayne Burleson,” Differential
Receivers Power consumed at Current-Sensing for On-Chip Interconnects,” IEEE
10fF load Transactions on Very Large Scale Integration (VLSI)
Voltage sense 746µW Systems,Vol. 12, No. 12, December 2004
[9] G.Anusha, P.Venkateshwarlu, P.Murugeshwari,
M.Bhaskar, B.Venkataramani, “An Input Multiplexed Current
Current sense 70µW mode transmitter for on-chip global interconnects”,
amplifier TENCON 2008.
Differential amplifier 1mW [10] P.Murugeswari, G.Anusha, P.Venkateshwarlu,
with current mirror M.Bhaskar, B.Venkataramani,“A Wide Band Voltage Mode
load Sense Amplifier Receiver for High Speed Interconnects”,
TENCON 2008.

IV Conclusion

In this paper, a differential amplifier with current

mirror load is proposed for the receiver. The differential
voltage sense amplifier proposed in this paper has increased
the signal swing at the output of the receiver from 20mV [6] to
1.2V at 4Gbps data rate at the cost of 10 times increase in
power. The proposed receiver is able to drive larger capacitive
loads and is able to produce larger signal swing at the cost of
increase in power dissipation. Hence the proposed receiver can
be used for on-chip interconnects of longer lengths, large
capacitive loads operating at high data rates.