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Center for Advanced Research in

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Engineering modeling
Introduction
CARE (Center for Advanced Research in Engineering) Private Limited deals in

Software Development and Electrical/Electronics/Computer Engineering with
focus on Communication Systems and Information Technology.
The Company employs highly motivated IT professionals, engineers and scientist with
diverse technical experience in Large scale software design, DSP, Digital Chip Design, and
Communication Systems, making it one of the best rounded technical teams. CARE team
specializes in design and development of Telecommunications, Data Communications, VoIP
based convergent networks and solutions. CARE core competencies include software design,
algorithms development, architectures design for networks and communications systems
and application-specific System on
Chip (SoC) design.
CARE team members have developed software solutions and ASICs and board-level system
solutions deployed in networks and communication products of high-profile Fortune 500
companies.
A world class team with 200+ man years experience in software and engineering project
development and management; CARE is strategically placed to be a very low cost high
technology design house for offshore outsourcing.
The team members have also implemented large complex real-time systems from concept to
completion. Examples include the Electronic Toll Collection System for Lahore-Islamabad
Motorway, 256 channels VoIP Media Processor SoC with all the software necessary to make a
high performance Media Gateway for Avaz Networks and the Automatic Call Distribution
System for Pakistan Telecommunication Limited
Company Profile
Sir Syed Memorial Building | 19 - Ataturk Avenue | G-5/1 Islamabad | T.+92.51.287-4115 / 4794 | F.+92.51..287-4614 | www.carepvtltd.com
asictelemetry EDA

SoCVoIP
fpga
testing
CARE Core Engineering Team

Dr. Farrukh Kamran :PhD in Electrical and Computer Engineering from Georgia
Institute of Technology. 11 years experience at companies like EGS, HiPo,
Torrington, Silicon Power Corporation, Enabling Technologies. His area of
expertise includes Applications and Network Software Design and
Packet/Network Processor Design.
Dr. Saeed-ur-Rehman: PhD in Electrical and Computer Engineering from Georgia Institute of Technology.
He has 9 years experience in large scale multi processor and multi-boards embedded system designing,
multiple RTOS, board layouts at Torrington, Enabling Technologies.
M. Mohsin Rahmatullah: MSEE from Georgia Institute of Technology. He has 8+ years industry experience
in the field of ASIC Design, Multi-Processor SoC Design, Media Processor and Peripheral Interface Design,
Wireless and Telecomm Algorithms Development from GTRI, AMD, TechTools, and Enabling Technologies.
Dr. Aamer Iqbal Bhatti: PhD in Electrical Engineering from Leicester University. He has 5+ years experience
in Signal Processing, Modeling and Simulation, guidence and control system design at Ford Motor,
Caterpillar and Enabling Technologies.
Zaheer Ahmed: MS Computer Engineering from NUST. He has 12 years industry experience in Large-Scale
software designing for networks and realtime systems at various organizations. Area of expertise include
digital design, embedded and application software development and Network analysis.
Hammad A. Khan: MSEE from Iowa State University. He has 6+ years experience in Communication
Systems, Image and Signal Processing, Modem Design and DSP Optimization at Office of Naval Research US
Navy, 3Com/ US Robotics and Enabling Technologies.
Dr. Amir Qayyum: PhD in Mobile Networking from University of Paris-Sud, France. Active member of the
MANET (Mobile Ad-hoc Network) group at IETF. He has 6+ years industry experience at CWO, INRIA France
and Enabling Technologies for designing and developing networking protocols for wireless networks.
Durdana Habib: MS Computer Engineering from NUST. 12 years of industry experience in the embedded
system design and DSP tools development at CTI and Enabling Technologies.
Dr. Imtiaz Taj: PhD in Electrical Engineering from University of Hokkaido, Japan. 3 years of experience in
multimedia algorithm, software and system designing at University of Hokkaido and Enabling echnologies.
Sheikh Farhan: MS Computer Engineering from NUST. 6+ years of experience in digital design, software
development and applying quality assurance standards at Enabling Technologies.
Dr.Muddassar Farooq: Received his Doctor of Science (DSc) degree from the University of Dortmund,
Germany. He has more than 6 years of industrial research and development experience. He has served in
the German civil service and managed large scale projects including guarantee based energy efficient
scheduler and agent-based protocol engineering for fixed telecommunication networks and MANETs.
Company Profile
asictelemetry EDA

SoCVoIP
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testing
Design Services
CARE offers the following Design Services:
Software Design Services

Platforms
Processors
Application
Embedded/Firmware
Digital Hardware Design

FPGA Based
SoC
ASIC
DSP Processor
Security Processor
Network Processor
Media Processor
EDA Tools
System Design
Mutlilayer Board
Multiple RTOS
Device Drivers
Verification and Compliance Testing

Digital Hardware Verification
System Testing
Software Testing
Company Profile
asictelemetry EDA

SoCVoIP
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testing
Design Services
CARE Sspecializes in Voice/Data Communications software and application

development
Control Processing (Networking and Management)

DSP Algorithms
Code optimization
Platforms
Real time operating systems (VxWorks, RTLinux, ThreadX)
Windows
Linux
Processors
Pentium
TI C54x, ADSP 21xx, 21xxx
Power PC (PPC405GP)
RISC
ARM
Leverage the CARE advantage in areas including:
Backend IT support
Code maintanance
Call center solution
Customer Relationship Management
e-learning, and more
Company Profile
asictelemetry EDA

SoCVoIP
fpga
testing
Design Services
Application
CARE offers the variety application software development solutions for VoIP
based products, Data Communication and Networking solutions. CARE team has
developed IP V4 and IP V6 stack and signaling stacks for Carrier Class Media
Gateway solutions and IP based migrateable video conferencing systems
Networking Packet Telephony

Internet Protocol Signaling
IP QoS SIP
RTP/RTCP H.323
RoHC H.248/MeGaCo
TCP
PPP/ML-PPP Applications
ATM SIP Gateway
UNI 3.1, 4.0 SIP Soft Phone
AAL-1,-2,-5 H.248 Gateway
Traffic Shaping H.248 Soft Phone
ATM / IP / PSTN Interworking Control & Management Framework
S/W Components Manager
Management H/W Resources Manager
SNMP v1, v2, v3 SNMP Agent
Embedded Agent
Manager & GUI
MIB Integration Tools
Company Profile
asictelemetry EDA

SoCVoIP
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Design Services
Embedded/Firmware
CARE offers the broadest line of proven embedded software development

solutions. The team has developed highly optimized embedded software for the
G3 FAX, modem, speech codecs, video codecs, telephony, VoIP software. The
CARE can custom design an embedded software solution for any off-the-shelf,
general purpose, fixed or floating point processor or can map the algorithm on
any proprietary DSP
Audio Codecs Line and Acoustic Echo Cancellation

G.711
G.726 G.168 Compliant
G.729 A/B/E VAD, CNG, DTX
G.728 Data and fax tone detection
G.723 Double tone detection
Wireless Codecs QAM Burst Modem
AMR, all rates Satellite Applications

EFR
GSM-FR
QAM Continuous Modem
GSM-HR
Up to 256 QAM
Fax
V.17
V.27ter
V.29
T.38
T.30
Company Profile
asictelemetry EDA

SoCVoIP
fpga
testing
Design Services
FPGA Based
At CARE we have a rich portfolio of designing FPGA-based systems from concept
to implementation. We have designed FPGA-based systems for Nortel Networks,
NEC, STM wireless. Our complex real-time systems consist of micro-controller,
digital signal processor and FPGA. We specialize in optimally partitioning the
design into HW/SW modules. The HW modules are mapped as fully parallel,
time-shared, or micro-coded state machines on FPGA.
SoC
CARE team has designed three highly complex SoCs for technologies ranging .18
micron to .13 micron. CARE universal SoC platform can give a jump-start to any
complex SoC design. The platform has SDRAM memory I/Os, DMA, CPU
interfaces, HW embedded RTOS for multiprocessors, inter processor
communication platform.
ASIC
CARE team specializes in mapping computationally intensive algorithms in HW.
The team has experience in mapping algorithms as programmable processor
with enough flexibility to map an entire family of these algorithm on the
hardware.
Viterbi decoder with puncturing

Reed Solomon encoder and decoder
Multi channel DTMF generator and detector
Adaptive echo Canceller for VoIP applications
Speech Coders, G.711, G.729a, G.726
Data modems, V.17

Encryption, Decryption, Key exchange
JPEG
Motion estimation and compensation
Interfaces for PCI/PCI-X, DDR memory, MIPS/ARM Processors, etc
Company Profile
asictelemetry EDA
testing
SoCVoIP
fpga
Design Services

DSP Processor
A traditional DSP comes with a fixed instruction set. The design is focused on traditional DSP
applications with basic DSP functionality of Multiply Accumulate (MAC) operation. The trend is to
design a Very Long Instruction Word (VLIW)
instruction set and provide multiple MAC
operations capabilities in the hardware.

There is a range of processors available in
the market with these capabilities but they
only suit to general class of applications as
they focused a broad range of applications.
These processors are not optimized for
specific applications and hence the

performance to cost ratio of the resultant
systems is not always optimal. CARE team
has designed several application specific
DSPs which outperform general purpose
DSPs in performance and cost.
Media Processor
CARE team has designed and developed highest density Media Processor for Carrier Class
Media Gateway Applications. The Media Processor provides:
Three levels of parallelism for high-density and low-power media processing i.e.:
Scheduler
Media Switch
Processing Engine
Non-service affecting remote software
upgrades
Remote Debug and Development
Sleep unused resouces for low power
consumption
Advanced Integrated Development
Environment
Advanced memory management for high throughput Suport
for block-level and sample-by-sample processing
Rich Media Instruction Set Architecture
Dynamic swapping of software components at run time
Fully programmable solution: LEC, Voice Encoder/Decoder, etc
Software compatibilty at the API level for chip upgrades
Company Profile
asictelemetry EDA

SoCVoIP
fpga
testing
Design Services
Security Processor
CARE team has experience in designing very high data rate IPSec processing components and
complete HW/SW VPN solution. These components are easily pluggable in any networking or
computing system as soft macros. These components off load the main processor from
computationally intensive operations of IP security protocols. A list of these components are as
follows:
DES, 3DES and AES based Encryption/Decryption

DH, RSA and DSA based key generation
Main and aggressive IKE modes implemented for RSA
Signatures, as well as RSA Private and Public Key
generation methods
Remote user ID Authentication to protect against "Man
in the Middle Attacks"
SHA, MD5, RIPEMD-128/192, TIGER (with and without
HMAC) based Authentication
Network Processor
CARE team has designed and developed high throughput Network Processor
and its peripherals. The salient features of the processor are the following:
OC-3 rate Real Time Deep Packet Processing and OC-12 Aggregation
and Forwarding
QoS, Traffic Management and IP Sec with support for simultaneous
connections to ATM, IP, TDM, and back-plane switching fabric
On-chip supported interfaces include:
GMAC, POS-II, UTOPIA-II, TDMIO, PCI-X, DDR Memory Interfaces

On-chip Multiple RISC Cores and Cross Connect DMA
Complete tool-suite for application software development including C Compiler, Bit-exact
hardware simulator, hardware debugger through J-tag
Company Profile
asictelemetry EDA
testing
SoCVoIP
fpga
Design Services
EDA Tools
EDA tools are one of the most important factors that lead to the success of CARE team in developing
all first time right ASICs, SoCs, and several complex FPGA
systems. The tools are designed for internal use and help
the team in speeding up:
RTL Coding: Using code generators

Simulation: using CARE proprietary Verilog Processor
Verification: FPGA-based white box and black box
verifications
Testing: Automatic test vector generator
10
Company Profile
asictelemetry EDA

SoCVoIP
fpga
testing
IPs
Hardware
GigaBit MAC
POS/UTOPIA
RISC Interfaces
Memory Interfaces
PCI Host Bridge
Hardware RTOS
Applications Specific Processor Cores
Encryption and Authentication
Software
Speech Codes on T1 ,ADI, DSPs, Star Core

Optimized Video Codes on ARM, MIPS, Pentium Processors
H.323, SIP, Signalling Software
Optimized RTP, UDP, TCP/IP Stack for IPV4 and IPV6
OLSR Implementation for Ad-hoc Networks
11
Company Profile
asictelemetry EDA

SoCVoIP
fpga
testing
Products
G3 Fax Interface for Motorola SecTel9600

The Fax-to-Serial converter provides an interface between PSTN line (CO
Interface), regular fax machine and Motorola Secra Phone, SecTel9600. It has
three RJ11 ports and one serial port. The serial port is connected to the Secra
Phone to transmit and receive the digital fax data to and from the Secra Phone.
The three RJ11 ports are used to connect the PSTN line, the fax machine and
Secra Phone.
Universal Security Box

The Universal Security Box is a low cost solution providing clear secure voice
and data transmission using existing analog POTS line. The device
incorporates AES algorithm for encryption, proprietary speech encoding and
Group3 fax protocols through built-in dial up modem. The device's small and
lightweight design along with a single push button on/off option makes it ideal for office, banks
and enterprise use. The product supports the following features:
Clear and secure voice with Low bit rate speech encoding
Data and voice Encryption
Dialup secure modem
Secure Group3 fax
Software up-grade capability
Device status LED
3D Digital Terrain Model Generator

Digital Terrain Model representing land surface point elevations accepts
stereo image data in various input formats and output Terrain model with
elevation and their related data layers. Generation of Digital terrain model
comprises of the following major algorithms:
Rectification of scanned maps

An Image rectification procedure for image to map registration
Performance optimized Stereo matching algorithms for "correspondence problem"
Elevation computations using disparity measures
DEM Generation in regular and triangular grids
Proprietary DTM Error estimation and correction
Display of graphical representation of terrain and heights
12
Company Profile
asictelemetry EDA

SoCVoIP
fpga
testing
Products
Calling Card Gateway

An Intelligent Network based application that provides service provider IVR servers
and switching gateways along with software to manage and record the transactions.
Among various functions of the software applications are:
Generation of calling card number series

Activation of these cards once the cards reach the final sales outlets
Network management
IP Enabled Exchange
Low-cost voice communication infrastructure along with Internet connectivity for
the distant rural areas with the following features:
Scalability [100 - 500] lines

Telephony connectivity, as well as connectivity to the global IP network
Remote Configuration and Management
Modularity, capable of connectivity to a variety of access networks
Adaptability to the local harsh operating environment
Flexibility for future feature upgrades
Remote Billing
High Data Rate Industrial Telemetry Modem

PCM/FM based telemetry subsystem capable of supporting up to 2 Mbps data-rate
with the following salient features:
Turbo Codes Used for forward error correction (FEC) for channel impairments
AES Data Encryption for enhanced security level
PCM/FM modulation
Interface to RF module
Can be used as Standalone System
Intelligent Routers for Mobile Wireless Ad-hoc Networks

Adhoc Network based communication solution underlying the following features:
Integrated mobile and land link network design

Mesh Network Architecture
Robustness and Redundancy
Remote Configuration
Self Diagnostics and Self Healing
13
Company Profile
asictelemetry EDA
SoC testing
Engineering fpga modeling
VoIP
Products
Toll Collection System

More than hundred toll collection positions networked together over a distance of
400 Km. Each vehicle entering the tollway (motorway) is dispensed with a magnetic
ticket at the entry booth that bears information about the vehicle, location and time
and date. When leaving the tollway, the same ticket is read by a magnetic reader
and the information is processed to generate the toll amount. Once the motorist
pays toll, a receipt is printed and barrier is lifted allowing the motorist to pass
through.
At each exit loction, a local network and database server, polls the booth machines
and collects transaction data. This is entered into a local database which is,
synchronized with data from all the other Exits distributed along the tollway. A 64
kbits per second radio data link connects all the locations in real time.
The project was conceived as a functional prototype in less than a month time and
was installed and made operational in three months time after signing of the
contract.
14
Company Profile

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Center for Advanced Research in

CARE (Center for Advanced Research in Engineering) Private Limited deals in

Center for Advanced Research in

CARE Core Engineering Team

Center for Advanced Research in

CARE offers the following Design Services:

Software Design Services

Digital Hardware Design

Verification and Compliance Testing

Center for Advanced Research in

Software Design Services

CARE Sspecializes in Voice/Data Communications software and application

Control Processing (Networking and Management)

Leverage the CARE advantage in areas including:

Center for Advanced Research in

Software Design Services

Networking Packet Telephony

Center for Advanced Research in

Software Design Services

CARE offers the broadest line of proven embedded software development

Audio Codecs Line and Acoustic Echo Cancellation

Wireless Codecs QAM Burst Modem

AMR, all rates Satellite Applications

Center for Advanced Research in

Digital Hardware Design

Viterbi decoder with puncturing

Data modems, V.17

Digital Hardware Design

operations capabilities in the hardware.

specific applications and hence the

Center for Advanced Research in

Digital Hardware Design

DES, 3DES and AES based Encryption/Decryption

On-chip supported interfaces include:

GMAC, POS-II, UTOPIA-II, TDMIO, PCI-X, DDR Memory Interfaces

RTL Coding: Using code generators

Center for Advanced Research in

Speech Codes on T1 ,ADI, DSPs, Star Core

Center for Advanced Research in

G3 Fax Interface for Motorola SecTel9600

Universal Security Box

3D Digital Terrain Model Generator

Rectification of scanned maps

Center for Advanced Research in

Calling Card Gateway

Generation of calling card number series

Scalability [100 - 500] lines

High Data Rate Industrial Telemetry Modem

Intelligent Routers for Mobile Wireless Ad-hoc Networks

Integrated mobile and land link network design

Toll Collection System

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