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 ITRS Technical Requirements - Electrostatics

Year Technology 2002 2003 2004 2005 2006 2007 2008 2009 2012 2015 2018
Node 130nm 100nm 90nm 80nm 70nm 65nm 55nm 50nm 32nm 25nm 18nm
Maximum allowable
electrostatic field on 150 V/cm 125 V/cm 100 V/cm 90 V/cm 80 V/cm 70 V/cm 60 V/cm 50 V/cm 35 V/cm 25 V/cm 18 V/cm
facility surfaces
Maximum allowable
2.0 nC 1.5 nC 1.0 nC 0.8 nC 0.65 nC 0.5 nC 0.35 nC 0.25 nC 0.125 nC 0.10 nC 0.08 nC
static charge on
(200V) (150V) (100V) (80V) (65V) (50V) (35V) (25V) (12.5V) (10V) (8V)
devices
Maximum allowable
electrostatic field on 150 V/cm 125 V/cm 100 V/cm 90 V/cm 80 V/cm 70 V/cm 60 V/cm 50 V/cm 35 V/cm 25 V/cm 18 V/cm
wafer and
photomask surfaces
Commander Brian Martinez USN
Note: Person Grounded by Wriststrap
8,330 volts
FoD
 ESD Foams
Antistatic Polyurethane (Flexible Polyether)
Black Conductive Dipped Foam
Excessive Carbon Rub off
Conductivity can vary from batch to batch
Not chemical resistant - does not accept components well
Pink Surfactant Antistatic Foam
Depends upon moisture for performance
Conductive Polyethylene (Closed Cell Cross linked Polyethylene)
Use in some clean rooms and little rub off
Very conductive grades and Volume Resistivity
Good chemical resistance and permanent conductive
Out of Spec Black Conductive
Polyethylene Carbon Dipped
Foam Particles Shedding

2011 RMV Technology Group LLC ,All rights Reserved.

Pink Poly Bag = FOD
ESD Sensitive
Circuit Cards
 Blue Plastic Trash Bin at 1 Distance
from Satellite 2 with Peak Voltages of
Greater than +/-10235 Volts

2011-RMV Technology Group, LLC

All Rights Reserved
 Corrugated =
FOD in Low RH Staples =FOD
FODs in ESD Protected Areas
Out of Spec Dip Tubes = FOD
 Additional Reference Material
The Dip Tube
Interference Technology
By Bob Vermillion, CPP/Fellow
June 1, 2010
This article illustrates that removal of ESD sensitive components from
non-conforming or suspect dip tubes will generate ESD events.

JEDEC and Tape & Reel Issues

Interference Technology UK
by Bob Vermillion, CPP/Fellow
November 2010
Handling todays architectures in combination with ultra sensitive electronic

components packaged in suspect counterfeit or non-conforming materials leads

to issues during the inspection process and in use. Issues in the handling of
ultra sensitive (Class 0) ESD devices are discussed in this
groundbreaking article.