EMT 125/3

DIGITAL ELECTRONIC PRINCIPLES

INTRODUCTION TO SEQUENTIAL
LOGIC CIRCUIT

SITI ZARINA BINTI MD NAZIRI | SCHOOL OF MICROELECTRONIC ENGINEERING | UniMAP

 Sequential Logic Circuit

Describe and explain Latches, Gated Latches

and Edge triggered flip flops characteristic.

Illustrate the output of Latches, Gated Latches

and Edge triggered flip flops.

Explain and demonstrate the applications of

flip flops.

2
 Chapter Overview

Latches
Gated Latches
Edge-triggered flip-flops
Flip-flop operating characteristics
Flip-flop applications
 EMT 125/3
DIGITAL ELECTRONIC PRINCIPLES

LATCHES

SITI ZARINA BINTI MD NAZIRI | SCHOOL OF MICROELECTRONIC ENGINEERING | UniMAP

 Introduction

Latches and flip-flops (FFs) are the basic single-bit

memory elements used to build sequential circuit with
one or two inputs/outputs, designed using individual
logic gates and feedback loops.

Latches are bistable devices whose state normally

depend on asynchronous input.

Edge triggered FFs are bistable devices which

synchronous input whose state depend on the input only
at triggering transition of clock pulse.
 Introduction (cont..)
Latches:
The output of a latch depends on its current inputs and on its
previous output and its change of state can happen at anytime
when its inputs change.

Flip-Flop:
The output of a flip-flop also depends on current inputs and its
previous output but the change of state occurs at specific times
determined by a clock input.

The basic difference between Latches & FFs:

The way in which they are changed from one state to another
state.
 Introduction (cont..)

Latches:
S-R Latch(active high input & active low input)
Gated S-R Latch
Gated D Latch

Flip-Flops:
Edge-triggered flip-flop (S-R, J-K, D)
(eg., J-KFFs = a type of FFs that can operate inset, reset, no
change and toggle modes.
Asynchronous Inputs
Master-Slave Flip-Flop
Flip-flop operating characteristics
Flip-flop applications
 Latches

Type of temporary storage device that has two stable (bi-stable) states.

Similar to flip-flop the outputs are connected back to opposite inputs.

S-R latch, Gated/Enabled S-R latch and Gated D latch.

(i)Eg,activehighinputSRlatchformwith2cross-coupledNORgates.
(ii)Eg,activelowinputSRlatchformwith2cross-coupledNANDgates.

Output of each gate is connected to an input of opposite gate.

Output of latch always complement of each others:

-when Q is high, Q is low.
-when Q is low, Q is high.
S-R Latch (Set-Reset Latch)
 Active HIGH S-R Latch

Logic Diagram

S R Q Q
1 0 1 0
0 0 1 0 Set state
0 1 0 1
0 0 0 1 Reset state
1 1 0 0 Undefined Two Logic Symbols
Function table
 Active LOW S-R Latch

Logic Diagram

S R Q Q
0 1 1 0
1 1 1 0 Set state
1 0 0 1
1 1 0 1 Reset state
Two Logic Symbols
0 0 1 1 Undefined

Function table
 S-R Latch (cont)

Example 1:
If S and R waveform is applied to the input of latch in
given figures, determine the waveform that will be observed
on the Q output. Assume Q is initially LOW.
 S-R Latch (cont)

Answer 1:
 Gated S-R Latch

Logic Diagram

EN S R Q Q
0 X X Q Q No change
1 0 0 Q Q No change
1 0 1 0 1 Reset state EN EN
1 1 0 1 0 Set state
1 1 1 1 1 Undefined

Function table Two Logic Symbols

 Gated S-R Latch (cont)

Example 2:
Determine the Q output waveform if the inputs shown are
applied to Gated S-R Latch that is initially RESET.
 Gated S-R Latch (cont)

Answer 2:
 Gated D (data) Latch

Logic Diagram

EN D Q Q
0 X Q Q No change
1 0 0 1 Reset state
1 1 0 1 Set state

Function table Logic Symbol

 Gated D Latch (cont)

Example 3:
Determine the Q output waveform if the inputs shown are
applied to a Gated D Latch which is initially RESET.
 Gated D Latch (cont)

Answer: