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Novel Current Mode Electronically Tunable

lossless Integrator Employing VDTA

Mayank Srivastava, Gaurav Chitranshi, Prateek Sengar Dinesh Prasad

Deptt. of ECE, Deptt. of ECE,
Amity University Uttar Pradesh Jamia Millia Islamia, New Delhi

Deptt. of ECE,
ABES Engineering College,

Abstract This paper proposes a new lossless current-mode one active element (ii) use of more than one passive element
(CM) integrator employing one VDTA and single grounded (iii) use of floating capacitors which occupy large chip area in
capacitor. The single active element based configuration has low monolithic integration.(iii) lack of electronic control(iv)
power dissipation and less requirement of chip area and the use requirement(s) of external passive component matching
of grounded capacitor is favorable from monolithic integration constraints (v) degraded performance under non ideal
point of view. The advantageous feature of proposed integrator conditions(vi)unavailability of explicit current output at high
are; (i) purely a resister-less realization (ii) facility of electronic impedance terminal (in case of CM integrator).
control (iii) availability of explicit current output at high
impedance port and (iv)very good non-ideal performance. The Therefore, the aim of this paper is to present a lossless CM
workability of proposed CM integrator is demonstrated by integrator configuration with following positive features:
SPICE simulations with TSMC CMOS .18 m process
(i) Use of only one VDTA
Keywordsvoltage differencing transconductance amplifie
(VDTA); Integrator; grounded capacitor,electronic tunability. (ii) Use of only one capacitor
(iii) Purely resistor-less realization
(iv) Use of grounded capacitor
Active RC Integrator is a very useful circuit configuration,
finds applications in Synthesis and development of several (v) Electronically tunable gain
analog signal generation and signal processing circuits such as
(vi) Improved non-ideal performance
quadrature oscillators, active filters, waveform generators
etc. Many current/voltage mode lossy/lossless integrator (vii) Availability of explicit current output signal at high
circuits based on different active components such as impedance port.
operational amplifiers (OP-AMP)[1], second generation
current conveyors (CCII) )[2, 3, 12, 13, 15], differential The VDTA is a popular active building block proposed in
voltage current conveyor (DVCC) )[4], differential difference [16] finds several applications in analog filter designing [17-
current conveyor (DDCC) [8], multiplication mode current 19], oscillators [20-22] and inductor simulators [21]. A single
conveyor (MMCC)[6], current follower transconductance VDTA based trans-admittance mode integrator has been
amplifier(CFTA)[10], current feedback amplifiers(CFOA) proposed in [23] but there is no current-mode integrator
[14], current controlled current conveyor transconductance employing VDTA is available in literature. So, This
amplifier(CCCCTA)[11], current differencing communication is an effort to fill this void.
transconductance amplifiers (CDTA)[9], and current Fig. 1 shows the symbolic representation VDTA, where N
differencing buffered amplifier (CDBA) )[5] and current and P are input ports and X-, Z and X+ are output terminals.
controlled current differencing buffered amplifier All the ports of VDTA are at high impedance levels.
(CCCDBA)[7] have been proposed in the literature.
Unfortunately these available circuit configurations bear
one or more of following disadvantages:(i) use of more than

978-1-4673-6540-6/15/$31.00 2015 IEEE

The proposed integrator circuit is shown in Fig. 3. A
straightforward analysis of this circuit yields the following
expression for output current;

I out = 1 I in (7)
Fig. 1 Symbolic representation of VDTA From equation (7), it is clear that gain of proposed
integrator is electronically tunable by gm1 and the value of gm1
The terminal current -voltage relationships of VDTA can can be adjust by bias currents of VDTA. Fig. 3 shows that
be given by following set of equations: output current Iout is explicitly available at high impedance
I z = g m1 (V p Vn ) (1) Z port. Hence, no additional current follower is required to
use this output.
I x + = g m2 V z (2) The current transfer function achieved from equation (7)
I x = g m2 V z (3)
I out g m1
The CMOS implementation of VDTA [17] is shown in = (8)
Fig. 2. I in sC0
For sinusoidal steady state
I out ( j ) g m1 j 900 (9)
= e
I in ( j ) sC0
From equation (9) it is clear that phase difference between
Iout and Iin is -900.


Fig. 2 CMOS implementation of VDTA [16]
Under the influence of VDTA non-idealities, the defining
The trans-conductance gains gm1 and gm2 of CMOS VDTA equations of VDTA are modified as
shown in Fig 2 are given as
I z = z g m1 (V p Vn ) (8)
g3 + g 4 (4)
g m1 =
2 I x + = x + g m2 (Vz Vv ) (9)

g 5 + g8 or g + g7 I x = x g m2 (Vz Vv ) (10)
g m2 = g m2 = 6 (5)
2 2
Where z, x+ and x- are the trans-conductance error gains
Where, gn is the transconductance of nth MOS transistor and there values are very slightly less than unity.
given as
The output current transfer of proposed configuration
W (6) under non ideal conditions is found as
g n = I Bn n COX
L n
gm z
where, n is carrier mobility, COX is capacitance of gate- I out = 1 I in (11)
oxide layer per unit area, W is MOS transistorss effective sC0
channel width, L is effective channel length and IBn is bias It is clear from equation (11) that even under the non-ideal
current of nth transistor. conditions, the proposed configuration simulates an ideal CM
integrator with electronically tunable gain. So, the behavior of
II. PROPOSED CURRENT-MODE INTEGRATOR proposed circuit does not effected in non-ideal environment.


The validity of proposed circuit is confirmed by simulating it

by employing CMOS VDTA shown in Fig. 2 with gm1 = gm2 =
636.3A/V. the value of capacitor C0 is 10nF.
A rectangular current signal Iin with swing from -1.0 mA to
+1.0 mA and time period of 4 s is used as an input signal
(shown in Fig. 4). The output current signal (Iout) is shown in
Fig. 5, is a triangular signal, which confirms the workability of
Fig. 3 Proposed CM Integrator presented circuit.
x 10

A VDTA based CM lossless integrator circuit employing


0 single VDTA and one grounded capacitor has been proposed.

-0.5 The proposed circuit is a resistor-less realization and offers
-1 electronic control of gain by VDTA transconductance, explicit
0 0.5 1 1.5 CM output available at a high impedance port which is suitable
for cascading and no requirement of any component matching
x 10

constraint. The proposed configuration exhibit very good non-

Fig.4 Input Current (Iin)
ideal behavior and even under the influence of VDTA non-
idealities, it simulate a lossless CM integrator. The theoretical
x 10
analysis has been confirmed by SPICE simulation with TSMC
CMOS .0.18m process parameters

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